Update version for v2.4.0 release
[qemu.git] / target-i386 / fpu_helper.c
1 /*
2 * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <math.h>
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "qemu/host-utils.h"
24 #include "exec/cpu_ldst.h"
25
26 #define FPU_RC_MASK 0xc00
27 #define FPU_RC_NEAR 0x000
28 #define FPU_RC_DOWN 0x400
29 #define FPU_RC_UP 0x800
30 #define FPU_RC_CHOP 0xc00
31
32 #define MAXTAN 9223372036854775808.0
33
34 /* the following deal with x86 long double-precision numbers */
35 #define MAXEXPD 0x7fff
36 #define EXPBIAS 16383
37 #define EXPD(fp) (fp.l.upper & 0x7fff)
38 #define SIGND(fp) ((fp.l.upper) & 0x8000)
39 #define MANTD(fp) (fp.l.lower)
40 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
41
42 #define FPUS_IE (1 << 0)
43 #define FPUS_DE (1 << 1)
44 #define FPUS_ZE (1 << 2)
45 #define FPUS_OE (1 << 3)
46 #define FPUS_UE (1 << 4)
47 #define FPUS_PE (1 << 5)
48 #define FPUS_SF (1 << 6)
49 #define FPUS_SE (1 << 7)
50 #define FPUS_B (1 << 15)
51
52 #define FPUC_EM 0x3f
53
54 #define floatx80_lg2 make_floatx80(0x3ffd, 0x9a209a84fbcff799LL)
55 #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
56 #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
57
58 static inline void fpush(CPUX86State *env)
59 {
60 env->fpstt = (env->fpstt - 1) & 7;
61 env->fptags[env->fpstt] = 0; /* validate stack entry */
62 }
63
64 static inline void fpop(CPUX86State *env)
65 {
66 env->fptags[env->fpstt] = 1; /* invalidate stack entry */
67 env->fpstt = (env->fpstt + 1) & 7;
68 }
69
70 static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr)
71 {
72 CPU_LDoubleU temp;
73
74 temp.l.lower = cpu_ldq_data(env, ptr);
75 temp.l.upper = cpu_lduw_data(env, ptr + 8);
76 return temp.d;
77 }
78
79 static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong ptr)
80 {
81 CPU_LDoubleU temp;
82
83 temp.d = f;
84 cpu_stq_data(env, ptr, temp.l.lower);
85 cpu_stw_data(env, ptr + 8, temp.l.upper);
86 }
87
88 /* x87 FPU helpers */
89
90 static inline double floatx80_to_double(CPUX86State *env, floatx80 a)
91 {
92 union {
93 float64 f64;
94 double d;
95 } u;
96
97 u.f64 = floatx80_to_float64(a, &env->fp_status);
98 return u.d;
99 }
100
101 static inline floatx80 double_to_floatx80(CPUX86State *env, double a)
102 {
103 union {
104 float64 f64;
105 double d;
106 } u;
107
108 u.d = a;
109 return float64_to_floatx80(u.f64, &env->fp_status);
110 }
111
112 static void fpu_set_exception(CPUX86State *env, int mask)
113 {
114 env->fpus |= mask;
115 if (env->fpus & (~env->fpuc & FPUC_EM)) {
116 env->fpus |= FPUS_SE | FPUS_B;
117 }
118 }
119
120 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
121 {
122 if (floatx80_is_zero(b)) {
123 fpu_set_exception(env, FPUS_ZE);
124 }
125 return floatx80_div(a, b, &env->fp_status);
126 }
127
128 static void fpu_raise_exception(CPUX86State *env)
129 {
130 if (env->cr[0] & CR0_NE_MASK) {
131 raise_exception(env, EXCP10_COPR);
132 }
133 #if !defined(CONFIG_USER_ONLY)
134 else {
135 cpu_set_ferr(env);
136 }
137 #endif
138 }
139
140 void helper_flds_FT0(CPUX86State *env, uint32_t val)
141 {
142 union {
143 float32 f;
144 uint32_t i;
145 } u;
146
147 u.i = val;
148 FT0 = float32_to_floatx80(u.f, &env->fp_status);
149 }
150
151 void helper_fldl_FT0(CPUX86State *env, uint64_t val)
152 {
153 union {
154 float64 f;
155 uint64_t i;
156 } u;
157
158 u.i = val;
159 FT0 = float64_to_floatx80(u.f, &env->fp_status);
160 }
161
162 void helper_fildl_FT0(CPUX86State *env, int32_t val)
163 {
164 FT0 = int32_to_floatx80(val, &env->fp_status);
165 }
166
167 void helper_flds_ST0(CPUX86State *env, uint32_t val)
168 {
169 int new_fpstt;
170 union {
171 float32 f;
172 uint32_t i;
173 } u;
174
175 new_fpstt = (env->fpstt - 1) & 7;
176 u.i = val;
177 env->fpregs[new_fpstt].d = float32_to_floatx80(u.f, &env->fp_status);
178 env->fpstt = new_fpstt;
179 env->fptags[new_fpstt] = 0; /* validate stack entry */
180 }
181
182 void helper_fldl_ST0(CPUX86State *env, uint64_t val)
183 {
184 int new_fpstt;
185 union {
186 float64 f;
187 uint64_t i;
188 } u;
189
190 new_fpstt = (env->fpstt - 1) & 7;
191 u.i = val;
192 env->fpregs[new_fpstt].d = float64_to_floatx80(u.f, &env->fp_status);
193 env->fpstt = new_fpstt;
194 env->fptags[new_fpstt] = 0; /* validate stack entry */
195 }
196
197 void helper_fildl_ST0(CPUX86State *env, int32_t val)
198 {
199 int new_fpstt;
200
201 new_fpstt = (env->fpstt - 1) & 7;
202 env->fpregs[new_fpstt].d = int32_to_floatx80(val, &env->fp_status);
203 env->fpstt = new_fpstt;
204 env->fptags[new_fpstt] = 0; /* validate stack entry */
205 }
206
207 void helper_fildll_ST0(CPUX86State *env, int64_t val)
208 {
209 int new_fpstt;
210
211 new_fpstt = (env->fpstt - 1) & 7;
212 env->fpregs[new_fpstt].d = int64_to_floatx80(val, &env->fp_status);
213 env->fpstt = new_fpstt;
214 env->fptags[new_fpstt] = 0; /* validate stack entry */
215 }
216
217 uint32_t helper_fsts_ST0(CPUX86State *env)
218 {
219 union {
220 float32 f;
221 uint32_t i;
222 } u;
223
224 u.f = floatx80_to_float32(ST0, &env->fp_status);
225 return u.i;
226 }
227
228 uint64_t helper_fstl_ST0(CPUX86State *env)
229 {
230 union {
231 float64 f;
232 uint64_t i;
233 } u;
234
235 u.f = floatx80_to_float64(ST0, &env->fp_status);
236 return u.i;
237 }
238
239 int32_t helper_fist_ST0(CPUX86State *env)
240 {
241 int32_t val;
242
243 val = floatx80_to_int32(ST0, &env->fp_status);
244 if (val != (int16_t)val) {
245 val = -32768;
246 }
247 return val;
248 }
249
250 int32_t helper_fistl_ST0(CPUX86State *env)
251 {
252 int32_t val;
253 signed char old_exp_flags;
254
255 old_exp_flags = get_float_exception_flags(&env->fp_status);
256 set_float_exception_flags(0, &env->fp_status);
257
258 val = floatx80_to_int32(ST0, &env->fp_status);
259 if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
260 val = 0x80000000;
261 }
262 set_float_exception_flags(get_float_exception_flags(&env->fp_status)
263 | old_exp_flags, &env->fp_status);
264 return val;
265 }
266
267 int64_t helper_fistll_ST0(CPUX86State *env)
268 {
269 int64_t val;
270 signed char old_exp_flags;
271
272 old_exp_flags = get_float_exception_flags(&env->fp_status);
273 set_float_exception_flags(0, &env->fp_status);
274
275 val = floatx80_to_int64(ST0, &env->fp_status);
276 if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
277 val = 0x8000000000000000ULL;
278 }
279 set_float_exception_flags(get_float_exception_flags(&env->fp_status)
280 | old_exp_flags, &env->fp_status);
281 return val;
282 }
283
284 int32_t helper_fistt_ST0(CPUX86State *env)
285 {
286 int32_t val;
287
288 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
289 if (val != (int16_t)val) {
290 val = -32768;
291 }
292 return val;
293 }
294
295 int32_t helper_fisttl_ST0(CPUX86State *env)
296 {
297 int32_t val;
298
299 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
300 return val;
301 }
302
303 int64_t helper_fisttll_ST0(CPUX86State *env)
304 {
305 int64_t val;
306
307 val = floatx80_to_int64_round_to_zero(ST0, &env->fp_status);
308 return val;
309 }
310
311 void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)
312 {
313 int new_fpstt;
314
315 new_fpstt = (env->fpstt - 1) & 7;
316 env->fpregs[new_fpstt].d = helper_fldt(env, ptr);
317 env->fpstt = new_fpstt;
318 env->fptags[new_fpstt] = 0; /* validate stack entry */
319 }
320
321 void helper_fstt_ST0(CPUX86State *env, target_ulong ptr)
322 {
323 helper_fstt(env, ST0, ptr);
324 }
325
326 void helper_fpush(CPUX86State *env)
327 {
328 fpush(env);
329 }
330
331 void helper_fpop(CPUX86State *env)
332 {
333 fpop(env);
334 }
335
336 void helper_fdecstp(CPUX86State *env)
337 {
338 env->fpstt = (env->fpstt - 1) & 7;
339 env->fpus &= ~0x4700;
340 }
341
342 void helper_fincstp(CPUX86State *env)
343 {
344 env->fpstt = (env->fpstt + 1) & 7;
345 env->fpus &= ~0x4700;
346 }
347
348 /* FPU move */
349
350 void helper_ffree_STN(CPUX86State *env, int st_index)
351 {
352 env->fptags[(env->fpstt + st_index) & 7] = 1;
353 }
354
355 void helper_fmov_ST0_FT0(CPUX86State *env)
356 {
357 ST0 = FT0;
358 }
359
360 void helper_fmov_FT0_STN(CPUX86State *env, int st_index)
361 {
362 FT0 = ST(st_index);
363 }
364
365 void helper_fmov_ST0_STN(CPUX86State *env, int st_index)
366 {
367 ST0 = ST(st_index);
368 }
369
370 void helper_fmov_STN_ST0(CPUX86State *env, int st_index)
371 {
372 ST(st_index) = ST0;
373 }
374
375 void helper_fxchg_ST0_STN(CPUX86State *env, int st_index)
376 {
377 floatx80 tmp;
378
379 tmp = ST(st_index);
380 ST(st_index) = ST0;
381 ST0 = tmp;
382 }
383
384 /* FPU operations */
385
386 static const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500};
387
388 void helper_fcom_ST0_FT0(CPUX86State *env)
389 {
390 int ret;
391
392 ret = floatx80_compare(ST0, FT0, &env->fp_status);
393 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
394 }
395
396 void helper_fucom_ST0_FT0(CPUX86State *env)
397 {
398 int ret;
399
400 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
401 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
402 }
403
404 static const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
405
406 void helper_fcomi_ST0_FT0(CPUX86State *env)
407 {
408 int eflags;
409 int ret;
410
411 ret = floatx80_compare(ST0, FT0, &env->fp_status);
412 eflags = cpu_cc_compute_all(env, CC_OP);
413 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
414 CC_SRC = eflags;
415 }
416
417 void helper_fucomi_ST0_FT0(CPUX86State *env)
418 {
419 int eflags;
420 int ret;
421
422 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
423 eflags = cpu_cc_compute_all(env, CC_OP);
424 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
425 CC_SRC = eflags;
426 }
427
428 void helper_fadd_ST0_FT0(CPUX86State *env)
429 {
430 ST0 = floatx80_add(ST0, FT0, &env->fp_status);
431 }
432
433 void helper_fmul_ST0_FT0(CPUX86State *env)
434 {
435 ST0 = floatx80_mul(ST0, FT0, &env->fp_status);
436 }
437
438 void helper_fsub_ST0_FT0(CPUX86State *env)
439 {
440 ST0 = floatx80_sub(ST0, FT0, &env->fp_status);
441 }
442
443 void helper_fsubr_ST0_FT0(CPUX86State *env)
444 {
445 ST0 = floatx80_sub(FT0, ST0, &env->fp_status);
446 }
447
448 void helper_fdiv_ST0_FT0(CPUX86State *env)
449 {
450 ST0 = helper_fdiv(env, ST0, FT0);
451 }
452
453 void helper_fdivr_ST0_FT0(CPUX86State *env)
454 {
455 ST0 = helper_fdiv(env, FT0, ST0);
456 }
457
458 /* fp operations between STN and ST0 */
459
460 void helper_fadd_STN_ST0(CPUX86State *env, int st_index)
461 {
462 ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status);
463 }
464
465 void helper_fmul_STN_ST0(CPUX86State *env, int st_index)
466 {
467 ST(st_index) = floatx80_mul(ST(st_index), ST0, &env->fp_status);
468 }
469
470 void helper_fsub_STN_ST0(CPUX86State *env, int st_index)
471 {
472 ST(st_index) = floatx80_sub(ST(st_index), ST0, &env->fp_status);
473 }
474
475 void helper_fsubr_STN_ST0(CPUX86State *env, int st_index)
476 {
477 ST(st_index) = floatx80_sub(ST0, ST(st_index), &env->fp_status);
478 }
479
480 void helper_fdiv_STN_ST0(CPUX86State *env, int st_index)
481 {
482 floatx80 *p;
483
484 p = &ST(st_index);
485 *p = helper_fdiv(env, *p, ST0);
486 }
487
488 void helper_fdivr_STN_ST0(CPUX86State *env, int st_index)
489 {
490 floatx80 *p;
491
492 p = &ST(st_index);
493 *p = helper_fdiv(env, ST0, *p);
494 }
495
496 /* misc FPU operations */
497 void helper_fchs_ST0(CPUX86State *env)
498 {
499 ST0 = floatx80_chs(ST0);
500 }
501
502 void helper_fabs_ST0(CPUX86State *env)
503 {
504 ST0 = floatx80_abs(ST0);
505 }
506
507 void helper_fld1_ST0(CPUX86State *env)
508 {
509 ST0 = floatx80_one;
510 }
511
512 void helper_fldl2t_ST0(CPUX86State *env)
513 {
514 ST0 = floatx80_l2t;
515 }
516
517 void helper_fldl2e_ST0(CPUX86State *env)
518 {
519 ST0 = floatx80_l2e;
520 }
521
522 void helper_fldpi_ST0(CPUX86State *env)
523 {
524 ST0 = floatx80_pi;
525 }
526
527 void helper_fldlg2_ST0(CPUX86State *env)
528 {
529 ST0 = floatx80_lg2;
530 }
531
532 void helper_fldln2_ST0(CPUX86State *env)
533 {
534 ST0 = floatx80_ln2;
535 }
536
537 void helper_fldz_ST0(CPUX86State *env)
538 {
539 ST0 = floatx80_zero;
540 }
541
542 void helper_fldz_FT0(CPUX86State *env)
543 {
544 FT0 = floatx80_zero;
545 }
546
547 uint32_t helper_fnstsw(CPUX86State *env)
548 {
549 return (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
550 }
551
552 uint32_t helper_fnstcw(CPUX86State *env)
553 {
554 return env->fpuc;
555 }
556
557 void update_fp_status(CPUX86State *env)
558 {
559 int rnd_type;
560
561 /* set rounding mode */
562 switch (env->fpuc & FPU_RC_MASK) {
563 default:
564 case FPU_RC_NEAR:
565 rnd_type = float_round_nearest_even;
566 break;
567 case FPU_RC_DOWN:
568 rnd_type = float_round_down;
569 break;
570 case FPU_RC_UP:
571 rnd_type = float_round_up;
572 break;
573 case FPU_RC_CHOP:
574 rnd_type = float_round_to_zero;
575 break;
576 }
577 set_float_rounding_mode(rnd_type, &env->fp_status);
578 switch ((env->fpuc >> 8) & 3) {
579 case 0:
580 rnd_type = 32;
581 break;
582 case 2:
583 rnd_type = 64;
584 break;
585 case 3:
586 default:
587 rnd_type = 80;
588 break;
589 }
590 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
591 }
592
593 void helper_fldcw(CPUX86State *env, uint32_t val)
594 {
595 cpu_set_fpuc(env, val);
596 }
597
598 void helper_fclex(CPUX86State *env)
599 {
600 env->fpus &= 0x7f00;
601 }
602
603 void helper_fwait(CPUX86State *env)
604 {
605 if (env->fpus & FPUS_SE) {
606 fpu_raise_exception(env);
607 }
608 }
609
610 void helper_fninit(CPUX86State *env)
611 {
612 env->fpus = 0;
613 env->fpstt = 0;
614 cpu_set_fpuc(env, 0x37f);
615 env->fptags[0] = 1;
616 env->fptags[1] = 1;
617 env->fptags[2] = 1;
618 env->fptags[3] = 1;
619 env->fptags[4] = 1;
620 env->fptags[5] = 1;
621 env->fptags[6] = 1;
622 env->fptags[7] = 1;
623 }
624
625 /* BCD ops */
626
627 void helper_fbld_ST0(CPUX86State *env, target_ulong ptr)
628 {
629 floatx80 tmp;
630 uint64_t val;
631 unsigned int v;
632 int i;
633
634 val = 0;
635 for (i = 8; i >= 0; i--) {
636 v = cpu_ldub_data(env, ptr + i);
637 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
638 }
639 tmp = int64_to_floatx80(val, &env->fp_status);
640 if (cpu_ldub_data(env, ptr + 9) & 0x80) {
641 tmp = floatx80_chs(tmp);
642 }
643 fpush(env);
644 ST0 = tmp;
645 }
646
647 void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
648 {
649 int v;
650 target_ulong mem_ref, mem_end;
651 int64_t val;
652
653 val = floatx80_to_int64(ST0, &env->fp_status);
654 mem_ref = ptr;
655 mem_end = mem_ref + 9;
656 if (val < 0) {
657 cpu_stb_data(env, mem_end, 0x80);
658 val = -val;
659 } else {
660 cpu_stb_data(env, mem_end, 0x00);
661 }
662 while (mem_ref < mem_end) {
663 if (val == 0) {
664 break;
665 }
666 v = val % 100;
667 val = val / 100;
668 v = ((v / 10) << 4) | (v % 10);
669 cpu_stb_data(env, mem_ref++, v);
670 }
671 while (mem_ref < mem_end) {
672 cpu_stb_data(env, mem_ref++, 0);
673 }
674 }
675
676 void helper_f2xm1(CPUX86State *env)
677 {
678 double val = floatx80_to_double(env, ST0);
679
680 val = pow(2.0, val) - 1.0;
681 ST0 = double_to_floatx80(env, val);
682 }
683
684 void helper_fyl2x(CPUX86State *env)
685 {
686 double fptemp = floatx80_to_double(env, ST0);
687
688 if (fptemp > 0.0) {
689 fptemp = log(fptemp) / log(2.0); /* log2(ST) */
690 fptemp *= floatx80_to_double(env, ST1);
691 ST1 = double_to_floatx80(env, fptemp);
692 fpop(env);
693 } else {
694 env->fpus &= ~0x4700;
695 env->fpus |= 0x400;
696 }
697 }
698
699 void helper_fptan(CPUX86State *env)
700 {
701 double fptemp = floatx80_to_double(env, ST0);
702
703 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
704 env->fpus |= 0x400;
705 } else {
706 fptemp = tan(fptemp);
707 ST0 = double_to_floatx80(env, fptemp);
708 fpush(env);
709 ST0 = floatx80_one;
710 env->fpus &= ~0x400; /* C2 <-- 0 */
711 /* the above code is for |arg| < 2**52 only */
712 }
713 }
714
715 void helper_fpatan(CPUX86State *env)
716 {
717 double fptemp, fpsrcop;
718
719 fpsrcop = floatx80_to_double(env, ST1);
720 fptemp = floatx80_to_double(env, ST0);
721 ST1 = double_to_floatx80(env, atan2(fpsrcop, fptemp));
722 fpop(env);
723 }
724
725 void helper_fxtract(CPUX86State *env)
726 {
727 CPU_LDoubleU temp;
728
729 temp.d = ST0;
730
731 if (floatx80_is_zero(ST0)) {
732 /* Easy way to generate -inf and raising division by 0 exception */
733 ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero,
734 &env->fp_status);
735 fpush(env);
736 ST0 = temp.d;
737 } else {
738 int expdif;
739
740 expdif = EXPD(temp) - EXPBIAS;
741 /* DP exponent bias */
742 ST0 = int32_to_floatx80(expdif, &env->fp_status);
743 fpush(env);
744 BIASEXPONENT(temp);
745 ST0 = temp.d;
746 }
747 }
748
749 void helper_fprem1(CPUX86State *env)
750 {
751 double st0, st1, dblq, fpsrcop, fptemp;
752 CPU_LDoubleU fpsrcop1, fptemp1;
753 int expdif;
754 signed long long int q;
755
756 st0 = floatx80_to_double(env, ST0);
757 st1 = floatx80_to_double(env, ST1);
758
759 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
760 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
761 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
762 return;
763 }
764
765 fpsrcop = st0;
766 fptemp = st1;
767 fpsrcop1.d = ST0;
768 fptemp1.d = ST1;
769 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
770
771 if (expdif < 0) {
772 /* optimisation? taken from the AMD docs */
773 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
774 /* ST0 is unchanged */
775 return;
776 }
777
778 if (expdif < 53) {
779 dblq = fpsrcop / fptemp;
780 /* round dblq towards nearest integer */
781 dblq = rint(dblq);
782 st0 = fpsrcop - fptemp * dblq;
783
784 /* convert dblq to q by truncating towards zero */
785 if (dblq < 0.0) {
786 q = (signed long long int)(-dblq);
787 } else {
788 q = (signed long long int)dblq;
789 }
790
791 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
792 /* (C0,C3,C1) <-- (q2,q1,q0) */
793 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
794 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
795 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
796 } else {
797 env->fpus |= 0x400; /* C2 <-- 1 */
798 fptemp = pow(2.0, expdif - 50);
799 fpsrcop = (st0 / st1) / fptemp;
800 /* fpsrcop = integer obtained by chopping */
801 fpsrcop = (fpsrcop < 0.0) ?
802 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
803 st0 -= (st1 * fpsrcop * fptemp);
804 }
805 ST0 = double_to_floatx80(env, st0);
806 }
807
808 void helper_fprem(CPUX86State *env)
809 {
810 double st0, st1, dblq, fpsrcop, fptemp;
811 CPU_LDoubleU fpsrcop1, fptemp1;
812 int expdif;
813 signed long long int q;
814
815 st0 = floatx80_to_double(env, ST0);
816 st1 = floatx80_to_double(env, ST1);
817
818 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
819 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
820 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
821 return;
822 }
823
824 fpsrcop = st0;
825 fptemp = st1;
826 fpsrcop1.d = ST0;
827 fptemp1.d = ST1;
828 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
829
830 if (expdif < 0) {
831 /* optimisation? taken from the AMD docs */
832 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
833 /* ST0 is unchanged */
834 return;
835 }
836
837 if (expdif < 53) {
838 dblq = fpsrcop / fptemp; /* ST0 / ST1 */
839 /* round dblq towards zero */
840 dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq);
841 st0 = fpsrcop - fptemp * dblq; /* fpsrcop is ST0 */
842
843 /* convert dblq to q by truncating towards zero */
844 if (dblq < 0.0) {
845 q = (signed long long int)(-dblq);
846 } else {
847 q = (signed long long int)dblq;
848 }
849
850 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
851 /* (C0,C3,C1) <-- (q2,q1,q0) */
852 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
853 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
854 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
855 } else {
856 int N = 32 + (expdif % 32); /* as per AMD docs */
857
858 env->fpus |= 0x400; /* C2 <-- 1 */
859 fptemp = pow(2.0, (double)(expdif - N));
860 fpsrcop = (st0 / st1) / fptemp;
861 /* fpsrcop = integer obtained by chopping */
862 fpsrcop = (fpsrcop < 0.0) ?
863 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
864 st0 -= (st1 * fpsrcop * fptemp);
865 }
866 ST0 = double_to_floatx80(env, st0);
867 }
868
869 void helper_fyl2xp1(CPUX86State *env)
870 {
871 double fptemp = floatx80_to_double(env, ST0);
872
873 if ((fptemp + 1.0) > 0.0) {
874 fptemp = log(fptemp + 1.0) / log(2.0); /* log2(ST + 1.0) */
875 fptemp *= floatx80_to_double(env, ST1);
876 ST1 = double_to_floatx80(env, fptemp);
877 fpop(env);
878 } else {
879 env->fpus &= ~0x4700;
880 env->fpus |= 0x400;
881 }
882 }
883
884 void helper_fsqrt(CPUX86State *env)
885 {
886 if (floatx80_is_neg(ST0)) {
887 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
888 env->fpus |= 0x400;
889 }
890 ST0 = floatx80_sqrt(ST0, &env->fp_status);
891 }
892
893 void helper_fsincos(CPUX86State *env)
894 {
895 double fptemp = floatx80_to_double(env, ST0);
896
897 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
898 env->fpus |= 0x400;
899 } else {
900 ST0 = double_to_floatx80(env, sin(fptemp));
901 fpush(env);
902 ST0 = double_to_floatx80(env, cos(fptemp));
903 env->fpus &= ~0x400; /* C2 <-- 0 */
904 /* the above code is for |arg| < 2**63 only */
905 }
906 }
907
908 void helper_frndint(CPUX86State *env)
909 {
910 ST0 = floatx80_round_to_int(ST0, &env->fp_status);
911 }
912
913 void helper_fscale(CPUX86State *env)
914 {
915 if (floatx80_is_any_nan(ST1)) {
916 ST0 = ST1;
917 } else {
918 int n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status);
919 ST0 = floatx80_scalbn(ST0, n, &env->fp_status);
920 }
921 }
922
923 void helper_fsin(CPUX86State *env)
924 {
925 double fptemp = floatx80_to_double(env, ST0);
926
927 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
928 env->fpus |= 0x400;
929 } else {
930 ST0 = double_to_floatx80(env, sin(fptemp));
931 env->fpus &= ~0x400; /* C2 <-- 0 */
932 /* the above code is for |arg| < 2**53 only */
933 }
934 }
935
936 void helper_fcos(CPUX86State *env)
937 {
938 double fptemp = floatx80_to_double(env, ST0);
939
940 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
941 env->fpus |= 0x400;
942 } else {
943 ST0 = double_to_floatx80(env, cos(fptemp));
944 env->fpus &= ~0x400; /* C2 <-- 0 */
945 /* the above code is for |arg| < 2**63 only */
946 }
947 }
948
949 void helper_fxam_ST0(CPUX86State *env)
950 {
951 CPU_LDoubleU temp;
952 int expdif;
953
954 temp.d = ST0;
955
956 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
957 if (SIGND(temp)) {
958 env->fpus |= 0x200; /* C1 <-- 1 */
959 }
960
961 /* XXX: test fptags too */
962 expdif = EXPD(temp);
963 if (expdif == MAXEXPD) {
964 if (MANTD(temp) == 0x8000000000000000ULL) {
965 env->fpus |= 0x500; /* Infinity */
966 } else {
967 env->fpus |= 0x100; /* NaN */
968 }
969 } else if (expdif == 0) {
970 if (MANTD(temp) == 0) {
971 env->fpus |= 0x4000; /* Zero */
972 } else {
973 env->fpus |= 0x4400; /* Denormal */
974 }
975 } else {
976 env->fpus |= 0x400;
977 }
978 }
979
980 void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
981 {
982 int fpus, fptag, exp, i;
983 uint64_t mant;
984 CPU_LDoubleU tmp;
985
986 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
987 fptag = 0;
988 for (i = 7; i >= 0; i--) {
989 fptag <<= 2;
990 if (env->fptags[i]) {
991 fptag |= 3;
992 } else {
993 tmp.d = env->fpregs[i].d;
994 exp = EXPD(tmp);
995 mant = MANTD(tmp);
996 if (exp == 0 && mant == 0) {
997 /* zero */
998 fptag |= 1;
999 } else if (exp == 0 || exp == MAXEXPD
1000 || (mant & (1LL << 63)) == 0) {
1001 /* NaNs, infinity, denormal */
1002 fptag |= 2;
1003 }
1004 }
1005 }
1006 if (data32) {
1007 /* 32 bit */
1008 cpu_stl_data(env, ptr, env->fpuc);
1009 cpu_stl_data(env, ptr + 4, fpus);
1010 cpu_stl_data(env, ptr + 8, fptag);
1011 cpu_stl_data(env, ptr + 12, 0); /* fpip */
1012 cpu_stl_data(env, ptr + 16, 0); /* fpcs */
1013 cpu_stl_data(env, ptr + 20, 0); /* fpoo */
1014 cpu_stl_data(env, ptr + 24, 0); /* fpos */
1015 } else {
1016 /* 16 bit */
1017 cpu_stw_data(env, ptr, env->fpuc);
1018 cpu_stw_data(env, ptr + 2, fpus);
1019 cpu_stw_data(env, ptr + 4, fptag);
1020 cpu_stw_data(env, ptr + 6, 0);
1021 cpu_stw_data(env, ptr + 8, 0);
1022 cpu_stw_data(env, ptr + 10, 0);
1023 cpu_stw_data(env, ptr + 12, 0);
1024 }
1025 }
1026
1027 void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
1028 {
1029 int i, fpus, fptag;
1030
1031 if (data32) {
1032 cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1033 fpus = cpu_lduw_data(env, ptr + 4);
1034 fptag = cpu_lduw_data(env, ptr + 8);
1035 } else {
1036 cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1037 fpus = cpu_lduw_data(env, ptr + 2);
1038 fptag = cpu_lduw_data(env, ptr + 4);
1039 }
1040 env->fpstt = (fpus >> 11) & 7;
1041 env->fpus = fpus & ~0x3800;
1042 for (i = 0; i < 8; i++) {
1043 env->fptags[i] = ((fptag & 3) == 3);
1044 fptag >>= 2;
1045 }
1046 }
1047
1048 void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
1049 {
1050 floatx80 tmp;
1051 int i;
1052
1053 helper_fstenv(env, ptr, data32);
1054
1055 ptr += (14 << data32);
1056 for (i = 0; i < 8; i++) {
1057 tmp = ST(i);
1058 helper_fstt(env, tmp, ptr);
1059 ptr += 10;
1060 }
1061
1062 /* fninit */
1063 env->fpus = 0;
1064 env->fpstt = 0;
1065 cpu_set_fpuc(env, 0x37f);
1066 env->fptags[0] = 1;
1067 env->fptags[1] = 1;
1068 env->fptags[2] = 1;
1069 env->fptags[3] = 1;
1070 env->fptags[4] = 1;
1071 env->fptags[5] = 1;
1072 env->fptags[6] = 1;
1073 env->fptags[7] = 1;
1074 }
1075
1076 void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)
1077 {
1078 floatx80 tmp;
1079 int i;
1080
1081 helper_fldenv(env, ptr, data32);
1082 ptr += (14 << data32);
1083
1084 for (i = 0; i < 8; i++) {
1085 tmp = helper_fldt(env, ptr);
1086 ST(i) = tmp;
1087 ptr += 10;
1088 }
1089 }
1090
1091 #if defined(CONFIG_USER_ONLY)
1092 void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
1093 {
1094 helper_fsave(env, ptr, data32);
1095 }
1096
1097 void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
1098 {
1099 helper_frstor(env, ptr, data32);
1100 }
1101 #endif
1102
1103 void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)
1104 {
1105 int fpus, fptag, i, nb_xmm_regs;
1106 floatx80 tmp;
1107 target_ulong addr;
1108
1109 /* The operand must be 16 byte aligned */
1110 if (ptr & 0xf) {
1111 raise_exception(env, EXCP0D_GPF);
1112 }
1113
1114 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1115 fptag = 0;
1116 for (i = 0; i < 8; i++) {
1117 fptag |= (env->fptags[i] << i);
1118 }
1119 cpu_stw_data(env, ptr, env->fpuc);
1120 cpu_stw_data(env, ptr + 2, fpus);
1121 cpu_stw_data(env, ptr + 4, fptag ^ 0xff);
1122 #ifdef TARGET_X86_64
1123 if (data64) {
1124 cpu_stq_data(env, ptr + 0x08, 0); /* rip */
1125 cpu_stq_data(env, ptr + 0x10, 0); /* rdp */
1126 } else
1127 #endif
1128 {
1129 cpu_stl_data(env, ptr + 0x08, 0); /* eip */
1130 cpu_stl_data(env, ptr + 0x0c, 0); /* sel */
1131 cpu_stl_data(env, ptr + 0x10, 0); /* dp */
1132 cpu_stl_data(env, ptr + 0x14, 0); /* sel */
1133 }
1134
1135 addr = ptr + 0x20;
1136 for (i = 0; i < 8; i++) {
1137 tmp = ST(i);
1138 helper_fstt(env, tmp, addr);
1139 addr += 16;
1140 }
1141
1142 if (env->cr[4] & CR4_OSFXSR_MASK) {
1143 /* XXX: finish it */
1144 cpu_stl_data(env, ptr + 0x18, env->mxcsr); /* mxcsr */
1145 cpu_stl_data(env, ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
1146 if (env->hflags & HF_CS64_MASK) {
1147 nb_xmm_regs = 16;
1148 } else {
1149 nb_xmm_regs = 8;
1150 }
1151 addr = ptr + 0xa0;
1152 /* Fast FXSAVE leaves out the XMM registers */
1153 if (!(env->efer & MSR_EFER_FFXSR)
1154 || (env->hflags & HF_CPL_MASK)
1155 || !(env->hflags & HF_LMA_MASK)) {
1156 for (i = 0; i < nb_xmm_regs; i++) {
1157 cpu_stq_data(env, addr, env->xmm_regs[i].XMM_Q(0));
1158 cpu_stq_data(env, addr + 8, env->xmm_regs[i].XMM_Q(1));
1159 addr += 16;
1160 }
1161 }
1162 }
1163 }
1164
1165 void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)
1166 {
1167 int i, fpus, fptag, nb_xmm_regs;
1168 floatx80 tmp;
1169 target_ulong addr;
1170
1171 /* The operand must be 16 byte aligned */
1172 if (ptr & 0xf) {
1173 raise_exception(env, EXCP0D_GPF);
1174 }
1175
1176 cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1177 fpus = cpu_lduw_data(env, ptr + 2);
1178 fptag = cpu_lduw_data(env, ptr + 4);
1179 env->fpstt = (fpus >> 11) & 7;
1180 env->fpus = fpus & ~0x3800;
1181 fptag ^= 0xff;
1182 for (i = 0; i < 8; i++) {
1183 env->fptags[i] = ((fptag >> i) & 1);
1184 }
1185
1186 addr = ptr + 0x20;
1187 for (i = 0; i < 8; i++) {
1188 tmp = helper_fldt(env, addr);
1189 ST(i) = tmp;
1190 addr += 16;
1191 }
1192
1193 if (env->cr[4] & CR4_OSFXSR_MASK) {
1194 /* XXX: finish it */
1195 cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18));
1196 /* cpu_ldl_data(env, ptr + 0x1c); */
1197 if (env->hflags & HF_CS64_MASK) {
1198 nb_xmm_regs = 16;
1199 } else {
1200 nb_xmm_regs = 8;
1201 }
1202 addr = ptr + 0xa0;
1203 /* Fast FXRESTORE leaves out the XMM registers */
1204 if (!(env->efer & MSR_EFER_FFXSR)
1205 || (env->hflags & HF_CPL_MASK)
1206 || !(env->hflags & HF_LMA_MASK)) {
1207 for (i = 0; i < nb_xmm_regs; i++) {
1208 env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);
1209 env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);
1210 addr += 16;
1211 }
1212 }
1213 }
1214 }
1215
1216 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
1217 {
1218 CPU_LDoubleU temp;
1219
1220 temp.d = f;
1221 *pmant = temp.l.lower;
1222 *pexp = temp.l.upper;
1223 }
1224
1225 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
1226 {
1227 CPU_LDoubleU temp;
1228
1229 temp.l.upper = upper;
1230 temp.l.lower = mant;
1231 return temp.d;
1232 }
1233
1234 /* MMX/SSE */
1235 /* XXX: optimize by storing fptt and fptags in the static cpu state */
1236
1237 #define SSE_DAZ 0x0040
1238 #define SSE_RC_MASK 0x6000
1239 #define SSE_RC_NEAR 0x0000
1240 #define SSE_RC_DOWN 0x2000
1241 #define SSE_RC_UP 0x4000
1242 #define SSE_RC_CHOP 0x6000
1243 #define SSE_FZ 0x8000
1244
1245 void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1246 {
1247 int rnd_type;
1248
1249 env->mxcsr = mxcsr;
1250
1251 /* set rounding mode */
1252 switch (mxcsr & SSE_RC_MASK) {
1253 default:
1254 case SSE_RC_NEAR:
1255 rnd_type = float_round_nearest_even;
1256 break;
1257 case SSE_RC_DOWN:
1258 rnd_type = float_round_down;
1259 break;
1260 case SSE_RC_UP:
1261 rnd_type = float_round_up;
1262 break;
1263 case SSE_RC_CHOP:
1264 rnd_type = float_round_to_zero;
1265 break;
1266 }
1267 set_float_rounding_mode(rnd_type, &env->sse_status);
1268
1269 /* set denormals are zero */
1270 set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status);
1271
1272 /* set flush to zero */
1273 set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
1274 }
1275
1276 void cpu_set_fpuc(CPUX86State *env, uint16_t val)
1277 {
1278 env->fpuc = val;
1279 update_fp_status(env);
1280 }
1281
1282 void helper_ldmxcsr(CPUX86State *env, uint32_t val)
1283 {
1284 cpu_set_mxcsr(env, val);
1285 }
1286
1287 void helper_enter_mmx(CPUX86State *env)
1288 {
1289 env->fpstt = 0;
1290 *(uint32_t *)(env->fptags) = 0;
1291 *(uint32_t *)(env->fptags + 4) = 0;
1292 }
1293
1294 void helper_emms(CPUX86State *env)
1295 {
1296 /* set to empty state */
1297 *(uint32_t *)(env->fptags) = 0x01010101;
1298 *(uint32_t *)(env->fptags + 4) = 0x01010101;
1299 }
1300
1301 /* XXX: suppress */
1302 void helper_movq(CPUX86State *env, void *d, void *s)
1303 {
1304 *(uint64_t *)d = *(uint64_t *)s;
1305 }
1306
1307 #define SHIFT 0
1308 #include "ops_sse.h"
1309
1310 #define SHIFT 1
1311 #include "ops_sse.h"