cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / target-i386 / misc_helper.c
1 /*
2 * x86 misc helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "exec/ioport.h"
22 #include "helper.h"
23
24 #if !defined(CONFIG_USER_ONLY)
25 #include "exec/softmmu_exec.h"
26 #endif /* !defined(CONFIG_USER_ONLY) */
27
28 /* check if Port I/O is allowed in TSS */
29 static inline void check_io(CPUX86State *env, int addr, int size)
30 {
31 int io_offset, val, mask;
32
33 /* TSS must be a valid 32 bit one */
34 if (!(env->tr.flags & DESC_P_MASK) ||
35 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
36 env->tr.limit < 103) {
37 goto fail;
38 }
39 io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
40 io_offset += (addr >> 3);
41 /* Note: the check needs two bytes */
42 if ((io_offset + 1) > env->tr.limit) {
43 goto fail;
44 }
45 val = cpu_lduw_kernel(env, env->tr.base + io_offset);
46 val >>= (addr & 7);
47 mask = (1 << size) - 1;
48 /* all bits must be zero to allow the I/O */
49 if ((val & mask) != 0) {
50 fail:
51 raise_exception_err(env, EXCP0D_GPF, 0);
52 }
53 }
54
55 void helper_check_iob(CPUX86State *env, uint32_t t0)
56 {
57 check_io(env, t0, 1);
58 }
59
60 void helper_check_iow(CPUX86State *env, uint32_t t0)
61 {
62 check_io(env, t0, 2);
63 }
64
65 void helper_check_iol(CPUX86State *env, uint32_t t0)
66 {
67 check_io(env, t0, 4);
68 }
69
70 void helper_outb(uint32_t port, uint32_t data)
71 {
72 cpu_outb(port, data & 0xff);
73 }
74
75 target_ulong helper_inb(uint32_t port)
76 {
77 return cpu_inb(port);
78 }
79
80 void helper_outw(uint32_t port, uint32_t data)
81 {
82 cpu_outw(port, data & 0xffff);
83 }
84
85 target_ulong helper_inw(uint32_t port)
86 {
87 return cpu_inw(port);
88 }
89
90 void helper_outl(uint32_t port, uint32_t data)
91 {
92 cpu_outl(port, data);
93 }
94
95 target_ulong helper_inl(uint32_t port)
96 {
97 return cpu_inl(port);
98 }
99
100 void helper_into(CPUX86State *env, int next_eip_addend)
101 {
102 int eflags;
103
104 eflags = cpu_cc_compute_all(env, CC_OP);
105 if (eflags & CC_O) {
106 raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
107 }
108 }
109
110 void helper_single_step(CPUX86State *env)
111 {
112 #ifndef CONFIG_USER_ONLY
113 check_hw_breakpoints(env, true);
114 env->dr[6] |= DR6_BS;
115 #endif
116 raise_exception(env, EXCP01_DB);
117 }
118
119 void helper_cpuid(CPUX86State *env)
120 {
121 uint32_t eax, ebx, ecx, edx;
122
123 cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
124
125 cpu_x86_cpuid(env, (uint32_t)EAX, (uint32_t)ECX, &eax, &ebx, &ecx, &edx);
126 EAX = eax;
127 EBX = ebx;
128 ECX = ecx;
129 EDX = edx;
130 }
131
132 #if defined(CONFIG_USER_ONLY)
133 target_ulong helper_read_crN(CPUX86State *env, int reg)
134 {
135 return 0;
136 }
137
138 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
139 {
140 }
141
142 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
143 {
144 }
145 #else
146 target_ulong helper_read_crN(CPUX86State *env, int reg)
147 {
148 target_ulong val;
149
150 cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
151 switch (reg) {
152 default:
153 val = env->cr[reg];
154 break;
155 case 8:
156 if (!(env->hflags2 & HF2_VINTR_MASK)) {
157 val = cpu_get_apic_tpr(env->apic_state);
158 } else {
159 val = env->v_tpr;
160 }
161 break;
162 }
163 return val;
164 }
165
166 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
167 {
168 cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
169 switch (reg) {
170 case 0:
171 cpu_x86_update_cr0(env, t0);
172 break;
173 case 3:
174 cpu_x86_update_cr3(env, t0);
175 break;
176 case 4:
177 cpu_x86_update_cr4(env, t0);
178 break;
179 case 8:
180 if (!(env->hflags2 & HF2_VINTR_MASK)) {
181 cpu_set_apic_tpr(env->apic_state, t0);
182 }
183 env->v_tpr = t0 & 0x0f;
184 break;
185 default:
186 env->cr[reg] = t0;
187 break;
188 }
189 }
190
191 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
192 {
193 int i;
194
195 if (reg < 4) {
196 hw_breakpoint_remove(env, reg);
197 env->dr[reg] = t0;
198 hw_breakpoint_insert(env, reg);
199 } else if (reg == 7) {
200 for (i = 0; i < DR7_MAX_BP; i++) {
201 hw_breakpoint_remove(env, i);
202 }
203 env->dr[7] = t0;
204 for (i = 0; i < DR7_MAX_BP; i++) {
205 hw_breakpoint_insert(env, i);
206 }
207 } else {
208 env->dr[reg] = t0;
209 }
210 }
211 #endif
212
213 void helper_lmsw(CPUX86State *env, target_ulong t0)
214 {
215 /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
216 if already set to one. */
217 t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
218 helper_write_crN(env, 0, t0);
219 }
220
221 void helper_invlpg(CPUX86State *env, target_ulong addr)
222 {
223 cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
224 tlb_flush_page(env, addr);
225 }
226
227 void helper_rdtsc(CPUX86State *env)
228 {
229 uint64_t val;
230
231 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
232 raise_exception(env, EXCP0D_GPF);
233 }
234 cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
235
236 val = cpu_get_tsc(env) + env->tsc_offset;
237 EAX = (uint32_t)(val);
238 EDX = (uint32_t)(val >> 32);
239 }
240
241 void helper_rdtscp(CPUX86State *env)
242 {
243 helper_rdtsc(env);
244 ECX = (uint32_t)(env->tsc_aux);
245 }
246
247 void helper_rdpmc(CPUX86State *env)
248 {
249 if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
250 raise_exception(env, EXCP0D_GPF);
251 }
252 cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
253
254 /* currently unimplemented */
255 qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
256 raise_exception_err(env, EXCP06_ILLOP, 0);
257 }
258
259 #if defined(CONFIG_USER_ONLY)
260 void helper_wrmsr(CPUX86State *env)
261 {
262 }
263
264 void helper_rdmsr(CPUX86State *env)
265 {
266 }
267 #else
268 void helper_wrmsr(CPUX86State *env)
269 {
270 uint64_t val;
271
272 cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
273
274 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
275
276 switch ((uint32_t)ECX) {
277 case MSR_IA32_SYSENTER_CS:
278 env->sysenter_cs = val & 0xffff;
279 break;
280 case MSR_IA32_SYSENTER_ESP:
281 env->sysenter_esp = val;
282 break;
283 case MSR_IA32_SYSENTER_EIP:
284 env->sysenter_eip = val;
285 break;
286 case MSR_IA32_APICBASE:
287 cpu_set_apic_base(env->apic_state, val);
288 break;
289 case MSR_EFER:
290 {
291 uint64_t update_mask;
292
293 update_mask = 0;
294 if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL) {
295 update_mask |= MSR_EFER_SCE;
296 }
297 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
298 update_mask |= MSR_EFER_LME;
299 }
300 if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
301 update_mask |= MSR_EFER_FFXSR;
302 }
303 if (env->cpuid_ext2_features & CPUID_EXT2_NX) {
304 update_mask |= MSR_EFER_NXE;
305 }
306 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
307 update_mask |= MSR_EFER_SVME;
308 }
309 if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
310 update_mask |= MSR_EFER_FFXSR;
311 }
312 cpu_load_efer(env, (env->efer & ~update_mask) |
313 (val & update_mask));
314 }
315 break;
316 case MSR_STAR:
317 env->star = val;
318 break;
319 case MSR_PAT:
320 env->pat = val;
321 break;
322 case MSR_VM_HSAVE_PA:
323 env->vm_hsave = val;
324 break;
325 #ifdef TARGET_X86_64
326 case MSR_LSTAR:
327 env->lstar = val;
328 break;
329 case MSR_CSTAR:
330 env->cstar = val;
331 break;
332 case MSR_FMASK:
333 env->fmask = val;
334 break;
335 case MSR_FSBASE:
336 env->segs[R_FS].base = val;
337 break;
338 case MSR_GSBASE:
339 env->segs[R_GS].base = val;
340 break;
341 case MSR_KERNELGSBASE:
342 env->kernelgsbase = val;
343 break;
344 #endif
345 case MSR_MTRRphysBase(0):
346 case MSR_MTRRphysBase(1):
347 case MSR_MTRRphysBase(2):
348 case MSR_MTRRphysBase(3):
349 case MSR_MTRRphysBase(4):
350 case MSR_MTRRphysBase(5):
351 case MSR_MTRRphysBase(6):
352 case MSR_MTRRphysBase(7):
353 env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base = val;
354 break;
355 case MSR_MTRRphysMask(0):
356 case MSR_MTRRphysMask(1):
357 case MSR_MTRRphysMask(2):
358 case MSR_MTRRphysMask(3):
359 case MSR_MTRRphysMask(4):
360 case MSR_MTRRphysMask(5):
361 case MSR_MTRRphysMask(6):
362 case MSR_MTRRphysMask(7):
363 env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask = val;
364 break;
365 case MSR_MTRRfix64K_00000:
366 env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix64K_00000] = val;
367 break;
368 case MSR_MTRRfix16K_80000:
369 case MSR_MTRRfix16K_A0000:
370 env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1] = val;
371 break;
372 case MSR_MTRRfix4K_C0000:
373 case MSR_MTRRfix4K_C8000:
374 case MSR_MTRRfix4K_D0000:
375 case MSR_MTRRfix4K_D8000:
376 case MSR_MTRRfix4K_E0000:
377 case MSR_MTRRfix4K_E8000:
378 case MSR_MTRRfix4K_F0000:
379 case MSR_MTRRfix4K_F8000:
380 env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3] = val;
381 break;
382 case MSR_MTRRdefType:
383 env->mtrr_deftype = val;
384 break;
385 case MSR_MCG_STATUS:
386 env->mcg_status = val;
387 break;
388 case MSR_MCG_CTL:
389 if ((env->mcg_cap & MCG_CTL_P)
390 && (val == 0 || val == ~(uint64_t)0)) {
391 env->mcg_ctl = val;
392 }
393 break;
394 case MSR_TSC_AUX:
395 env->tsc_aux = val;
396 break;
397 case MSR_IA32_MISC_ENABLE:
398 env->msr_ia32_misc_enable = val;
399 break;
400 default:
401 if ((uint32_t)ECX >= MSR_MC0_CTL
402 && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
403 uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
404 if ((offset & 0x3) != 0
405 || (val == 0 || val == ~(uint64_t)0)) {
406 env->mce_banks[offset] = val;
407 }
408 break;
409 }
410 /* XXX: exception? */
411 break;
412 }
413 }
414
415 void helper_rdmsr(CPUX86State *env)
416 {
417 uint64_t val;
418
419 cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
420
421 switch ((uint32_t)ECX) {
422 case MSR_IA32_SYSENTER_CS:
423 val = env->sysenter_cs;
424 break;
425 case MSR_IA32_SYSENTER_ESP:
426 val = env->sysenter_esp;
427 break;
428 case MSR_IA32_SYSENTER_EIP:
429 val = env->sysenter_eip;
430 break;
431 case MSR_IA32_APICBASE:
432 val = cpu_get_apic_base(env->apic_state);
433 break;
434 case MSR_EFER:
435 val = env->efer;
436 break;
437 case MSR_STAR:
438 val = env->star;
439 break;
440 case MSR_PAT:
441 val = env->pat;
442 break;
443 case MSR_VM_HSAVE_PA:
444 val = env->vm_hsave;
445 break;
446 case MSR_IA32_PERF_STATUS:
447 /* tsc_increment_by_tick */
448 val = 1000ULL;
449 /* CPU multiplier */
450 val |= (((uint64_t)4ULL) << 40);
451 break;
452 #ifdef TARGET_X86_64
453 case MSR_LSTAR:
454 val = env->lstar;
455 break;
456 case MSR_CSTAR:
457 val = env->cstar;
458 break;
459 case MSR_FMASK:
460 val = env->fmask;
461 break;
462 case MSR_FSBASE:
463 val = env->segs[R_FS].base;
464 break;
465 case MSR_GSBASE:
466 val = env->segs[R_GS].base;
467 break;
468 case MSR_KERNELGSBASE:
469 val = env->kernelgsbase;
470 break;
471 case MSR_TSC_AUX:
472 val = env->tsc_aux;
473 break;
474 #endif
475 case MSR_MTRRphysBase(0):
476 case MSR_MTRRphysBase(1):
477 case MSR_MTRRphysBase(2):
478 case MSR_MTRRphysBase(3):
479 case MSR_MTRRphysBase(4):
480 case MSR_MTRRphysBase(5):
481 case MSR_MTRRphysBase(6):
482 case MSR_MTRRphysBase(7):
483 val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base;
484 break;
485 case MSR_MTRRphysMask(0):
486 case MSR_MTRRphysMask(1):
487 case MSR_MTRRphysMask(2):
488 case MSR_MTRRphysMask(3):
489 case MSR_MTRRphysMask(4):
490 case MSR_MTRRphysMask(5):
491 case MSR_MTRRphysMask(6):
492 case MSR_MTRRphysMask(7):
493 val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask;
494 break;
495 case MSR_MTRRfix64K_00000:
496 val = env->mtrr_fixed[0];
497 break;
498 case MSR_MTRRfix16K_80000:
499 case MSR_MTRRfix16K_A0000:
500 val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1];
501 break;
502 case MSR_MTRRfix4K_C0000:
503 case MSR_MTRRfix4K_C8000:
504 case MSR_MTRRfix4K_D0000:
505 case MSR_MTRRfix4K_D8000:
506 case MSR_MTRRfix4K_E0000:
507 case MSR_MTRRfix4K_E8000:
508 case MSR_MTRRfix4K_F0000:
509 case MSR_MTRRfix4K_F8000:
510 val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3];
511 break;
512 case MSR_MTRRdefType:
513 val = env->mtrr_deftype;
514 break;
515 case MSR_MTRRcap:
516 if (env->cpuid_features & CPUID_MTRR) {
517 val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
518 MSR_MTRRcap_WC_SUPPORTED;
519 } else {
520 /* XXX: exception? */
521 val = 0;
522 }
523 break;
524 case MSR_MCG_CAP:
525 val = env->mcg_cap;
526 break;
527 case MSR_MCG_CTL:
528 if (env->mcg_cap & MCG_CTL_P) {
529 val = env->mcg_ctl;
530 } else {
531 val = 0;
532 }
533 break;
534 case MSR_MCG_STATUS:
535 val = env->mcg_status;
536 break;
537 case MSR_IA32_MISC_ENABLE:
538 val = env->msr_ia32_misc_enable;
539 break;
540 default:
541 if ((uint32_t)ECX >= MSR_MC0_CTL
542 && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
543 uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL;
544 val = env->mce_banks[offset];
545 break;
546 }
547 /* XXX: exception? */
548 val = 0;
549 break;
550 }
551 EAX = (uint32_t)(val);
552 EDX = (uint32_t)(val >> 32);
553 }
554 #endif
555
556 static void do_hlt(X86CPU *cpu)
557 {
558 CPUState *cs = CPU(cpu);
559 CPUX86State *env = &cpu->env;
560
561 env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
562 cs->halted = 1;
563 env->exception_index = EXCP_HLT;
564 cpu_loop_exit(env);
565 }
566
567 void helper_hlt(CPUX86State *env, int next_eip_addend)
568 {
569 X86CPU *cpu = x86_env_get_cpu(env);
570
571 cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
572 EIP += next_eip_addend;
573
574 do_hlt(cpu);
575 }
576
577 void helper_monitor(CPUX86State *env, target_ulong ptr)
578 {
579 if ((uint32_t)ECX != 0) {
580 raise_exception(env, EXCP0D_GPF);
581 }
582 /* XXX: store address? */
583 cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
584 }
585
586 void helper_mwait(CPUX86State *env, int next_eip_addend)
587 {
588 CPUState *cs;
589 X86CPU *cpu;
590
591 if ((uint32_t)ECX != 0) {
592 raise_exception(env, EXCP0D_GPF);
593 }
594 cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
595 EIP += next_eip_addend;
596
597 cpu = x86_env_get_cpu(env);
598 cs = CPU(cpu);
599 /* XXX: not complete but not completely erroneous */
600 if (cs->cpu_index != 0 || env->next_cpu != NULL) {
601 /* more than one CPU: do not sleep because another CPU may
602 wake this one */
603 } else {
604 do_hlt(cpu);
605 }
606 }
607
608 void helper_debug(CPUX86State *env)
609 {
610 env->exception_index = EXCP_DEBUG;
611 cpu_loop_exit(env);
612 }