qdev: integrate with QEMU Object Model (v2)
[qemu.git] / target-i386 / translate.c
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29
30 #include "helper.h"
31 #define GEN_HELPER 1
32 #include "helper.h"
33
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39
40 #ifdef TARGET_X86_64
41 #define X86_64_ONLY(x) x
42 #define X86_64_DEF(...) __VA_ARGS__
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
46 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
47 #if 1
48 #define BUGGY_64(x) NULL
49 #endif
50 #else
51 #define X86_64_ONLY(x) NULL
52 #define X86_64_DEF(...)
53 #define CODE64(s) 0
54 #define REX_X(s) 0
55 #define REX_B(s) 0
56 #endif
57
58 //#define MACRO_TEST 1
59
60 /* global register indexes */
61 static TCGv_ptr cpu_env;
62 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
63 static TCGv_i32 cpu_cc_op;
64 static TCGv cpu_regs[CPU_NB_REGS];
65 /* local temps */
66 static TCGv cpu_T[2], cpu_T3;
67 /* local register indexes (only used inside old micro ops) */
68 static TCGv cpu_tmp0, cpu_tmp4;
69 static TCGv_ptr cpu_ptr0, cpu_ptr1;
70 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
71 static TCGv_i64 cpu_tmp1_i64;
72 static TCGv cpu_tmp5;
73
74 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
75
76 #include "gen-icount.h"
77
78 #ifdef TARGET_X86_64
79 static int x86_64_hregs;
80 #endif
81
82 typedef struct DisasContext {
83 /* current insn context */
84 int override; /* -1 if no override */
85 int prefix;
86 int aflag, dflag;
87 target_ulong pc; /* pc = eip + cs_base */
88 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
89 static state change (stop translation) */
90 /* current block context */
91 target_ulong cs_base; /* base of CS segment */
92 int pe; /* protected mode */
93 int code32; /* 32 bit code segment */
94 #ifdef TARGET_X86_64
95 int lma; /* long mode active */
96 int code64; /* 64 bit code segment */
97 int rex_x, rex_b;
98 #endif
99 int ss32; /* 32 bit stack segment */
100 int cc_op; /* current CC operation */
101 int addseg; /* non zero if either DS/ES/SS have a non zero base */
102 int f_st; /* currently unused */
103 int vm86; /* vm86 mode */
104 int cpl;
105 int iopl;
106 int tf; /* TF cpu flag */
107 int singlestep_enabled; /* "hardware" single step enabled */
108 int jmp_opt; /* use direct block chaining for direct jumps */
109 int mem_index; /* select memory access functions */
110 uint64_t flags; /* all execution flags */
111 struct TranslationBlock *tb;
112 int popl_esp_hack; /* for correct popl with esp base handling */
113 int rip_offset; /* only used in x86_64, but left for simplicity */
114 int cpuid_features;
115 int cpuid_ext_features;
116 int cpuid_ext2_features;
117 int cpuid_ext3_features;
118 } DisasContext;
119
120 static void gen_eob(DisasContext *s);
121 static void gen_jmp(DisasContext *s, target_ulong eip);
122 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
123
124 /* i386 arith/logic operations */
125 enum {
126 OP_ADDL,
127 OP_ORL,
128 OP_ADCL,
129 OP_SBBL,
130 OP_ANDL,
131 OP_SUBL,
132 OP_XORL,
133 OP_CMPL,
134 };
135
136 /* i386 shift ops */
137 enum {
138 OP_ROL,
139 OP_ROR,
140 OP_RCL,
141 OP_RCR,
142 OP_SHL,
143 OP_SHR,
144 OP_SHL1, /* undocumented */
145 OP_SAR = 7,
146 };
147
148 enum {
149 JCC_O,
150 JCC_B,
151 JCC_Z,
152 JCC_BE,
153 JCC_S,
154 JCC_P,
155 JCC_L,
156 JCC_LE,
157 };
158
159 /* operand size */
160 enum {
161 OT_BYTE = 0,
162 OT_WORD,
163 OT_LONG,
164 OT_QUAD,
165 };
166
167 enum {
168 /* I386 int registers */
169 OR_EAX, /* MUST be even numbered */
170 OR_ECX,
171 OR_EDX,
172 OR_EBX,
173 OR_ESP,
174 OR_EBP,
175 OR_ESI,
176 OR_EDI,
177
178 OR_TMP0 = 16, /* temporary operand register */
179 OR_TMP1,
180 OR_A0, /* temporary register used when doing address evaluation */
181 };
182
183 static inline void gen_op_movl_T0_0(void)
184 {
185 tcg_gen_movi_tl(cpu_T[0], 0);
186 }
187
188 static inline void gen_op_movl_T0_im(int32_t val)
189 {
190 tcg_gen_movi_tl(cpu_T[0], val);
191 }
192
193 static inline void gen_op_movl_T0_imu(uint32_t val)
194 {
195 tcg_gen_movi_tl(cpu_T[0], val);
196 }
197
198 static inline void gen_op_movl_T1_im(int32_t val)
199 {
200 tcg_gen_movi_tl(cpu_T[1], val);
201 }
202
203 static inline void gen_op_movl_T1_imu(uint32_t val)
204 {
205 tcg_gen_movi_tl(cpu_T[1], val);
206 }
207
208 static inline void gen_op_movl_A0_im(uint32_t val)
209 {
210 tcg_gen_movi_tl(cpu_A0, val);
211 }
212
213 #ifdef TARGET_X86_64
214 static inline void gen_op_movq_A0_im(int64_t val)
215 {
216 tcg_gen_movi_tl(cpu_A0, val);
217 }
218 #endif
219
220 static inline void gen_movtl_T0_im(target_ulong val)
221 {
222 tcg_gen_movi_tl(cpu_T[0], val);
223 }
224
225 static inline void gen_movtl_T1_im(target_ulong val)
226 {
227 tcg_gen_movi_tl(cpu_T[1], val);
228 }
229
230 static inline void gen_op_andl_T0_ffff(void)
231 {
232 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
233 }
234
235 static inline void gen_op_andl_T0_im(uint32_t val)
236 {
237 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
238 }
239
240 static inline void gen_op_movl_T0_T1(void)
241 {
242 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
243 }
244
245 static inline void gen_op_andl_A0_ffff(void)
246 {
247 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
248 }
249
250 #ifdef TARGET_X86_64
251
252 #define NB_OP_SIZES 4
253
254 #else /* !TARGET_X86_64 */
255
256 #define NB_OP_SIZES 3
257
258 #endif /* !TARGET_X86_64 */
259
260 #if defined(HOST_WORDS_BIGENDIAN)
261 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
262 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
263 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
264 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
265 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
266 #else
267 #define REG_B_OFFSET 0
268 #define REG_H_OFFSET 1
269 #define REG_W_OFFSET 0
270 #define REG_L_OFFSET 0
271 #define REG_LH_OFFSET 4
272 #endif
273
274 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
275 {
276 switch(ot) {
277 case OT_BYTE:
278 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
279 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
280 } else {
281 tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
282 }
283 break;
284 case OT_WORD:
285 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
286 break;
287 default: /* XXX this shouldn't be reached; abort? */
288 case OT_LONG:
289 /* For x86_64, this sets the higher half of register to zero.
290 For i386, this is equivalent to a mov. */
291 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
292 break;
293 #ifdef TARGET_X86_64
294 case OT_QUAD:
295 tcg_gen_mov_tl(cpu_regs[reg], t0);
296 break;
297 #endif
298 }
299 }
300
301 static inline void gen_op_mov_reg_T0(int ot, int reg)
302 {
303 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
304 }
305
306 static inline void gen_op_mov_reg_T1(int ot, int reg)
307 {
308 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
309 }
310
311 static inline void gen_op_mov_reg_A0(int size, int reg)
312 {
313 switch(size) {
314 case 0:
315 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
316 break;
317 default: /* XXX this shouldn't be reached; abort? */
318 case 1:
319 /* For x86_64, this sets the higher half of register to zero.
320 For i386, this is equivalent to a mov. */
321 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
322 break;
323 #ifdef TARGET_X86_64
324 case 2:
325 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
326 break;
327 #endif
328 }
329 }
330
331 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
332 {
333 switch(ot) {
334 case OT_BYTE:
335 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
336 goto std_case;
337 } else {
338 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
339 tcg_gen_ext8u_tl(t0, t0);
340 }
341 break;
342 default:
343 std_case:
344 tcg_gen_mov_tl(t0, cpu_regs[reg]);
345 break;
346 }
347 }
348
349 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
350 {
351 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
352 }
353
354 static inline void gen_op_movl_A0_reg(int reg)
355 {
356 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
357 }
358
359 static inline void gen_op_addl_A0_im(int32_t val)
360 {
361 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
362 #ifdef TARGET_X86_64
363 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
364 #endif
365 }
366
367 #ifdef TARGET_X86_64
368 static inline void gen_op_addq_A0_im(int64_t val)
369 {
370 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
371 }
372 #endif
373
374 static void gen_add_A0_im(DisasContext *s, int val)
375 {
376 #ifdef TARGET_X86_64
377 if (CODE64(s))
378 gen_op_addq_A0_im(val);
379 else
380 #endif
381 gen_op_addl_A0_im(val);
382 }
383
384 static inline void gen_op_addl_T0_T1(void)
385 {
386 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
387 }
388
389 static inline void gen_op_jmp_T0(void)
390 {
391 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
392 }
393
394 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
395 {
396 switch(size) {
397 case 0:
398 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
399 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
400 break;
401 case 1:
402 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
403 /* For x86_64, this sets the higher half of register to zero.
404 For i386, this is equivalent to a nop. */
405 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
406 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
407 break;
408 #ifdef TARGET_X86_64
409 case 2:
410 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
411 break;
412 #endif
413 }
414 }
415
416 static inline void gen_op_add_reg_T0(int size, int reg)
417 {
418 switch(size) {
419 case 0:
420 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
421 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
422 break;
423 case 1:
424 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
425 /* For x86_64, this sets the higher half of register to zero.
426 For i386, this is equivalent to a nop. */
427 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
428 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
429 break;
430 #ifdef TARGET_X86_64
431 case 2:
432 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
433 break;
434 #endif
435 }
436 }
437
438 static inline void gen_op_set_cc_op(int32_t val)
439 {
440 tcg_gen_movi_i32(cpu_cc_op, val);
441 }
442
443 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
444 {
445 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
446 if (shift != 0)
447 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
448 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
449 /* For x86_64, this sets the higher half of register to zero.
450 For i386, this is equivalent to a nop. */
451 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
452 }
453
454 static inline void gen_op_movl_A0_seg(int reg)
455 {
456 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
457 }
458
459 static inline void gen_op_addl_A0_seg(int reg)
460 {
461 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
462 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
463 #ifdef TARGET_X86_64
464 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
465 #endif
466 }
467
468 #ifdef TARGET_X86_64
469 static inline void gen_op_movq_A0_seg(int reg)
470 {
471 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
472 }
473
474 static inline void gen_op_addq_A0_seg(int reg)
475 {
476 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
477 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
478 }
479
480 static inline void gen_op_movq_A0_reg(int reg)
481 {
482 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
483 }
484
485 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
486 {
487 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
488 if (shift != 0)
489 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
490 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
491 }
492 #endif
493
494 static inline void gen_op_lds_T0_A0(int idx)
495 {
496 int mem_index = (idx >> 2) - 1;
497 switch(idx & 3) {
498 case 0:
499 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
500 break;
501 case 1:
502 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
503 break;
504 default:
505 case 2:
506 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
507 break;
508 }
509 }
510
511 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
512 {
513 int mem_index = (idx >> 2) - 1;
514 switch(idx & 3) {
515 case 0:
516 tcg_gen_qemu_ld8u(t0, a0, mem_index);
517 break;
518 case 1:
519 tcg_gen_qemu_ld16u(t0, a0, mem_index);
520 break;
521 case 2:
522 tcg_gen_qemu_ld32u(t0, a0, mem_index);
523 break;
524 default:
525 case 3:
526 /* Should never happen on 32-bit targets. */
527 #ifdef TARGET_X86_64
528 tcg_gen_qemu_ld64(t0, a0, mem_index);
529 #endif
530 break;
531 }
532 }
533
534 /* XXX: always use ldu or lds */
535 static inline void gen_op_ld_T0_A0(int idx)
536 {
537 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
538 }
539
540 static inline void gen_op_ldu_T0_A0(int idx)
541 {
542 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
543 }
544
545 static inline void gen_op_ld_T1_A0(int idx)
546 {
547 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
548 }
549
550 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
551 {
552 int mem_index = (idx >> 2) - 1;
553 switch(idx & 3) {
554 case 0:
555 tcg_gen_qemu_st8(t0, a0, mem_index);
556 break;
557 case 1:
558 tcg_gen_qemu_st16(t0, a0, mem_index);
559 break;
560 case 2:
561 tcg_gen_qemu_st32(t0, a0, mem_index);
562 break;
563 default:
564 case 3:
565 /* Should never happen on 32-bit targets. */
566 #ifdef TARGET_X86_64
567 tcg_gen_qemu_st64(t0, a0, mem_index);
568 #endif
569 break;
570 }
571 }
572
573 static inline void gen_op_st_T0_A0(int idx)
574 {
575 gen_op_st_v(idx, cpu_T[0], cpu_A0);
576 }
577
578 static inline void gen_op_st_T1_A0(int idx)
579 {
580 gen_op_st_v(idx, cpu_T[1], cpu_A0);
581 }
582
583 static inline void gen_jmp_im(target_ulong pc)
584 {
585 tcg_gen_movi_tl(cpu_tmp0, pc);
586 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
587 }
588
589 static inline void gen_string_movl_A0_ESI(DisasContext *s)
590 {
591 int override;
592
593 override = s->override;
594 #ifdef TARGET_X86_64
595 if (s->aflag == 2) {
596 if (override >= 0) {
597 gen_op_movq_A0_seg(override);
598 gen_op_addq_A0_reg_sN(0, R_ESI);
599 } else {
600 gen_op_movq_A0_reg(R_ESI);
601 }
602 } else
603 #endif
604 if (s->aflag) {
605 /* 32 bit address */
606 if (s->addseg && override < 0)
607 override = R_DS;
608 if (override >= 0) {
609 gen_op_movl_A0_seg(override);
610 gen_op_addl_A0_reg_sN(0, R_ESI);
611 } else {
612 gen_op_movl_A0_reg(R_ESI);
613 }
614 } else {
615 /* 16 address, always override */
616 if (override < 0)
617 override = R_DS;
618 gen_op_movl_A0_reg(R_ESI);
619 gen_op_andl_A0_ffff();
620 gen_op_addl_A0_seg(override);
621 }
622 }
623
624 static inline void gen_string_movl_A0_EDI(DisasContext *s)
625 {
626 #ifdef TARGET_X86_64
627 if (s->aflag == 2) {
628 gen_op_movq_A0_reg(R_EDI);
629 } else
630 #endif
631 if (s->aflag) {
632 if (s->addseg) {
633 gen_op_movl_A0_seg(R_ES);
634 gen_op_addl_A0_reg_sN(0, R_EDI);
635 } else {
636 gen_op_movl_A0_reg(R_EDI);
637 }
638 } else {
639 gen_op_movl_A0_reg(R_EDI);
640 gen_op_andl_A0_ffff();
641 gen_op_addl_A0_seg(R_ES);
642 }
643 }
644
645 static inline void gen_op_movl_T0_Dshift(int ot)
646 {
647 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
648 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
649 };
650
651 static void gen_extu(int ot, TCGv reg)
652 {
653 switch(ot) {
654 case OT_BYTE:
655 tcg_gen_ext8u_tl(reg, reg);
656 break;
657 case OT_WORD:
658 tcg_gen_ext16u_tl(reg, reg);
659 break;
660 case OT_LONG:
661 tcg_gen_ext32u_tl(reg, reg);
662 break;
663 default:
664 break;
665 }
666 }
667
668 static void gen_exts(int ot, TCGv reg)
669 {
670 switch(ot) {
671 case OT_BYTE:
672 tcg_gen_ext8s_tl(reg, reg);
673 break;
674 case OT_WORD:
675 tcg_gen_ext16s_tl(reg, reg);
676 break;
677 case OT_LONG:
678 tcg_gen_ext32s_tl(reg, reg);
679 break;
680 default:
681 break;
682 }
683 }
684
685 static inline void gen_op_jnz_ecx(int size, int label1)
686 {
687 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
688 gen_extu(size + 1, cpu_tmp0);
689 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
690 }
691
692 static inline void gen_op_jz_ecx(int size, int label1)
693 {
694 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
695 gen_extu(size + 1, cpu_tmp0);
696 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
697 }
698
699 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
700 {
701 switch (ot) {
702 case 0: gen_helper_inb(v, n); break;
703 case 1: gen_helper_inw(v, n); break;
704 case 2: gen_helper_inl(v, n); break;
705 }
706
707 }
708
709 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
710 {
711 switch (ot) {
712 case 0: gen_helper_outb(v, n); break;
713 case 1: gen_helper_outw(v, n); break;
714 case 2: gen_helper_outl(v, n); break;
715 }
716
717 }
718
719 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
720 uint32_t svm_flags)
721 {
722 int state_saved;
723 target_ulong next_eip;
724
725 state_saved = 0;
726 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
727 if (s->cc_op != CC_OP_DYNAMIC)
728 gen_op_set_cc_op(s->cc_op);
729 gen_jmp_im(cur_eip);
730 state_saved = 1;
731 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
732 switch (ot) {
733 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
734 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
735 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
736 }
737 }
738 if(s->flags & HF_SVMI_MASK) {
739 if (!state_saved) {
740 if (s->cc_op != CC_OP_DYNAMIC)
741 gen_op_set_cc_op(s->cc_op);
742 gen_jmp_im(cur_eip);
743 }
744 svm_flags |= (1 << (4 + ot));
745 next_eip = s->pc - s->cs_base;
746 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
747 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
748 tcg_const_i32(next_eip - cur_eip));
749 }
750 }
751
752 static inline void gen_movs(DisasContext *s, int ot)
753 {
754 gen_string_movl_A0_ESI(s);
755 gen_op_ld_T0_A0(ot + s->mem_index);
756 gen_string_movl_A0_EDI(s);
757 gen_op_st_T0_A0(ot + s->mem_index);
758 gen_op_movl_T0_Dshift(ot);
759 gen_op_add_reg_T0(s->aflag, R_ESI);
760 gen_op_add_reg_T0(s->aflag, R_EDI);
761 }
762
763 static inline void gen_update_cc_op(DisasContext *s)
764 {
765 if (s->cc_op != CC_OP_DYNAMIC) {
766 gen_op_set_cc_op(s->cc_op);
767 s->cc_op = CC_OP_DYNAMIC;
768 }
769 }
770
771 static void gen_op_update1_cc(void)
772 {
773 tcg_gen_discard_tl(cpu_cc_src);
774 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
775 }
776
777 static void gen_op_update2_cc(void)
778 {
779 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
780 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
781 }
782
783 static inline void gen_op_cmpl_T0_T1_cc(void)
784 {
785 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
786 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
787 }
788
789 static inline void gen_op_testl_T0_T1_cc(void)
790 {
791 tcg_gen_discard_tl(cpu_cc_src);
792 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
793 }
794
795 static void gen_op_update_neg_cc(void)
796 {
797 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
798 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
799 }
800
801 /* compute eflags.C to reg */
802 static void gen_compute_eflags_c(TCGv reg)
803 {
804 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
805 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
806 }
807
808 /* compute all eflags to cc_src */
809 static void gen_compute_eflags(TCGv reg)
810 {
811 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
812 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
813 }
814
815 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
816 {
817 if (s->cc_op != CC_OP_DYNAMIC)
818 gen_op_set_cc_op(s->cc_op);
819 switch(jcc_op) {
820 case JCC_O:
821 gen_compute_eflags(cpu_T[0]);
822 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
823 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
824 break;
825 case JCC_B:
826 gen_compute_eflags_c(cpu_T[0]);
827 break;
828 case JCC_Z:
829 gen_compute_eflags(cpu_T[0]);
830 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
831 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
832 break;
833 case JCC_BE:
834 gen_compute_eflags(cpu_tmp0);
835 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
836 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
837 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
838 break;
839 case JCC_S:
840 gen_compute_eflags(cpu_T[0]);
841 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
842 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
843 break;
844 case JCC_P:
845 gen_compute_eflags(cpu_T[0]);
846 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
847 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
848 break;
849 case JCC_L:
850 gen_compute_eflags(cpu_tmp0);
851 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
852 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
853 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
854 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
855 break;
856 default:
857 case JCC_LE:
858 gen_compute_eflags(cpu_tmp0);
859 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
860 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
861 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
862 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
863 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
864 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865 break;
866 }
867 }
868
869 /* return true if setcc_slow is not needed (WARNING: must be kept in
870 sync with gen_jcc1) */
871 static int is_fast_jcc_case(DisasContext *s, int b)
872 {
873 int jcc_op;
874 jcc_op = (b >> 1) & 7;
875 switch(s->cc_op) {
876 /* we optimize the cmp/jcc case */
877 case CC_OP_SUBB:
878 case CC_OP_SUBW:
879 case CC_OP_SUBL:
880 case CC_OP_SUBQ:
881 if (jcc_op == JCC_O || jcc_op == JCC_P)
882 goto slow_jcc;
883 break;
884
885 /* some jumps are easy to compute */
886 case CC_OP_ADDB:
887 case CC_OP_ADDW:
888 case CC_OP_ADDL:
889 case CC_OP_ADDQ:
890
891 case CC_OP_LOGICB:
892 case CC_OP_LOGICW:
893 case CC_OP_LOGICL:
894 case CC_OP_LOGICQ:
895
896 case CC_OP_INCB:
897 case CC_OP_INCW:
898 case CC_OP_INCL:
899 case CC_OP_INCQ:
900
901 case CC_OP_DECB:
902 case CC_OP_DECW:
903 case CC_OP_DECL:
904 case CC_OP_DECQ:
905
906 case CC_OP_SHLB:
907 case CC_OP_SHLW:
908 case CC_OP_SHLL:
909 case CC_OP_SHLQ:
910 if (jcc_op != JCC_Z && jcc_op != JCC_S)
911 goto slow_jcc;
912 break;
913 default:
914 slow_jcc:
915 return 0;
916 }
917 return 1;
918 }
919
920 /* generate a conditional jump to label 'l1' according to jump opcode
921 value 'b'. In the fast case, T0 is guaranted not to be used. */
922 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
923 {
924 int inv, jcc_op, size, cond;
925 TCGv t0;
926
927 inv = b & 1;
928 jcc_op = (b >> 1) & 7;
929
930 switch(cc_op) {
931 /* we optimize the cmp/jcc case */
932 case CC_OP_SUBB:
933 case CC_OP_SUBW:
934 case CC_OP_SUBL:
935 case CC_OP_SUBQ:
936
937 size = cc_op - CC_OP_SUBB;
938 switch(jcc_op) {
939 case JCC_Z:
940 fast_jcc_z:
941 switch(size) {
942 case 0:
943 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
944 t0 = cpu_tmp0;
945 break;
946 case 1:
947 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
948 t0 = cpu_tmp0;
949 break;
950 #ifdef TARGET_X86_64
951 case 2:
952 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
953 t0 = cpu_tmp0;
954 break;
955 #endif
956 default:
957 t0 = cpu_cc_dst;
958 break;
959 }
960 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
961 break;
962 case JCC_S:
963 fast_jcc_s:
964 switch(size) {
965 case 0:
966 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
967 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
968 0, l1);
969 break;
970 case 1:
971 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
972 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
973 0, l1);
974 break;
975 #ifdef TARGET_X86_64
976 case 2:
977 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
978 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
979 0, l1);
980 break;
981 #endif
982 default:
983 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
984 0, l1);
985 break;
986 }
987 break;
988
989 case JCC_B:
990 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
991 goto fast_jcc_b;
992 case JCC_BE:
993 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
994 fast_jcc_b:
995 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
996 switch(size) {
997 case 0:
998 t0 = cpu_tmp0;
999 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1000 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1001 break;
1002 case 1:
1003 t0 = cpu_tmp0;
1004 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1005 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1006 break;
1007 #ifdef TARGET_X86_64
1008 case 2:
1009 t0 = cpu_tmp0;
1010 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1011 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1012 break;
1013 #endif
1014 default:
1015 t0 = cpu_cc_src;
1016 break;
1017 }
1018 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1019 break;
1020
1021 case JCC_L:
1022 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1023 goto fast_jcc_l;
1024 case JCC_LE:
1025 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1026 fast_jcc_l:
1027 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1028 switch(size) {
1029 case 0:
1030 t0 = cpu_tmp0;
1031 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1032 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1033 break;
1034 case 1:
1035 t0 = cpu_tmp0;
1036 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1037 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1038 break;
1039 #ifdef TARGET_X86_64
1040 case 2:
1041 t0 = cpu_tmp0;
1042 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1043 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1044 break;
1045 #endif
1046 default:
1047 t0 = cpu_cc_src;
1048 break;
1049 }
1050 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1051 break;
1052
1053 default:
1054 goto slow_jcc;
1055 }
1056 break;
1057
1058 /* some jumps are easy to compute */
1059 case CC_OP_ADDB:
1060 case CC_OP_ADDW:
1061 case CC_OP_ADDL:
1062 case CC_OP_ADDQ:
1063
1064 case CC_OP_ADCB:
1065 case CC_OP_ADCW:
1066 case CC_OP_ADCL:
1067 case CC_OP_ADCQ:
1068
1069 case CC_OP_SBBB:
1070 case CC_OP_SBBW:
1071 case CC_OP_SBBL:
1072 case CC_OP_SBBQ:
1073
1074 case CC_OP_LOGICB:
1075 case CC_OP_LOGICW:
1076 case CC_OP_LOGICL:
1077 case CC_OP_LOGICQ:
1078
1079 case CC_OP_INCB:
1080 case CC_OP_INCW:
1081 case CC_OP_INCL:
1082 case CC_OP_INCQ:
1083
1084 case CC_OP_DECB:
1085 case CC_OP_DECW:
1086 case CC_OP_DECL:
1087 case CC_OP_DECQ:
1088
1089 case CC_OP_SHLB:
1090 case CC_OP_SHLW:
1091 case CC_OP_SHLL:
1092 case CC_OP_SHLQ:
1093
1094 case CC_OP_SARB:
1095 case CC_OP_SARW:
1096 case CC_OP_SARL:
1097 case CC_OP_SARQ:
1098 switch(jcc_op) {
1099 case JCC_Z:
1100 size = (cc_op - CC_OP_ADDB) & 3;
1101 goto fast_jcc_z;
1102 case JCC_S:
1103 size = (cc_op - CC_OP_ADDB) & 3;
1104 goto fast_jcc_s;
1105 default:
1106 goto slow_jcc;
1107 }
1108 break;
1109 default:
1110 slow_jcc:
1111 gen_setcc_slow_T0(s, jcc_op);
1112 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1113 cpu_T[0], 0, l1);
1114 break;
1115 }
1116 }
1117
1118 /* XXX: does not work with gdbstub "ice" single step - not a
1119 serious problem */
1120 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1121 {
1122 int l1, l2;
1123
1124 l1 = gen_new_label();
1125 l2 = gen_new_label();
1126 gen_op_jnz_ecx(s->aflag, l1);
1127 gen_set_label(l2);
1128 gen_jmp_tb(s, next_eip, 1);
1129 gen_set_label(l1);
1130 return l2;
1131 }
1132
1133 static inline void gen_stos(DisasContext *s, int ot)
1134 {
1135 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1136 gen_string_movl_A0_EDI(s);
1137 gen_op_st_T0_A0(ot + s->mem_index);
1138 gen_op_movl_T0_Dshift(ot);
1139 gen_op_add_reg_T0(s->aflag, R_EDI);
1140 }
1141
1142 static inline void gen_lods(DisasContext *s, int ot)
1143 {
1144 gen_string_movl_A0_ESI(s);
1145 gen_op_ld_T0_A0(ot + s->mem_index);
1146 gen_op_mov_reg_T0(ot, R_EAX);
1147 gen_op_movl_T0_Dshift(ot);
1148 gen_op_add_reg_T0(s->aflag, R_ESI);
1149 }
1150
1151 static inline void gen_scas(DisasContext *s, int ot)
1152 {
1153 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1154 gen_string_movl_A0_EDI(s);
1155 gen_op_ld_T1_A0(ot + s->mem_index);
1156 gen_op_cmpl_T0_T1_cc();
1157 gen_op_movl_T0_Dshift(ot);
1158 gen_op_add_reg_T0(s->aflag, R_EDI);
1159 }
1160
1161 static inline void gen_cmps(DisasContext *s, int ot)
1162 {
1163 gen_string_movl_A0_ESI(s);
1164 gen_op_ld_T0_A0(ot + s->mem_index);
1165 gen_string_movl_A0_EDI(s);
1166 gen_op_ld_T1_A0(ot + s->mem_index);
1167 gen_op_cmpl_T0_T1_cc();
1168 gen_op_movl_T0_Dshift(ot);
1169 gen_op_add_reg_T0(s->aflag, R_ESI);
1170 gen_op_add_reg_T0(s->aflag, R_EDI);
1171 }
1172
1173 static inline void gen_ins(DisasContext *s, int ot)
1174 {
1175 if (use_icount)
1176 gen_io_start();
1177 gen_string_movl_A0_EDI(s);
1178 /* Note: we must do this dummy write first to be restartable in
1179 case of page fault. */
1180 gen_op_movl_T0_0();
1181 gen_op_st_T0_A0(ot + s->mem_index);
1182 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1183 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1184 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1185 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1186 gen_op_st_T0_A0(ot + s->mem_index);
1187 gen_op_movl_T0_Dshift(ot);
1188 gen_op_add_reg_T0(s->aflag, R_EDI);
1189 if (use_icount)
1190 gen_io_end();
1191 }
1192
1193 static inline void gen_outs(DisasContext *s, int ot)
1194 {
1195 if (use_icount)
1196 gen_io_start();
1197 gen_string_movl_A0_ESI(s);
1198 gen_op_ld_T0_A0(ot + s->mem_index);
1199
1200 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1201 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1202 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1203 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1204 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1205
1206 gen_op_movl_T0_Dshift(ot);
1207 gen_op_add_reg_T0(s->aflag, R_ESI);
1208 if (use_icount)
1209 gen_io_end();
1210 }
1211
1212 /* same method as Valgrind : we generate jumps to current or next
1213 instruction */
1214 #define GEN_REPZ(op) \
1215 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1216 target_ulong cur_eip, target_ulong next_eip) \
1217 { \
1218 int l2;\
1219 gen_update_cc_op(s); \
1220 l2 = gen_jz_ecx_string(s, next_eip); \
1221 gen_ ## op(s, ot); \
1222 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1223 /* a loop would cause two single step exceptions if ECX = 1 \
1224 before rep string_insn */ \
1225 if (!s->jmp_opt) \
1226 gen_op_jz_ecx(s->aflag, l2); \
1227 gen_jmp(s, cur_eip); \
1228 }
1229
1230 #define GEN_REPZ2(op) \
1231 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1232 target_ulong cur_eip, \
1233 target_ulong next_eip, \
1234 int nz) \
1235 { \
1236 int l2;\
1237 gen_update_cc_op(s); \
1238 l2 = gen_jz_ecx_string(s, next_eip); \
1239 gen_ ## op(s, ot); \
1240 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1241 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1242 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1243 if (!s->jmp_opt) \
1244 gen_op_jz_ecx(s->aflag, l2); \
1245 gen_jmp(s, cur_eip); \
1246 }
1247
1248 GEN_REPZ(movs)
1249 GEN_REPZ(stos)
1250 GEN_REPZ(lods)
1251 GEN_REPZ(ins)
1252 GEN_REPZ(outs)
1253 GEN_REPZ2(scas)
1254 GEN_REPZ2(cmps)
1255
1256 static void gen_helper_fp_arith_ST0_FT0(int op)
1257 {
1258 switch (op) {
1259 case 0: gen_helper_fadd_ST0_FT0(); break;
1260 case 1: gen_helper_fmul_ST0_FT0(); break;
1261 case 2: gen_helper_fcom_ST0_FT0(); break;
1262 case 3: gen_helper_fcom_ST0_FT0(); break;
1263 case 4: gen_helper_fsub_ST0_FT0(); break;
1264 case 5: gen_helper_fsubr_ST0_FT0(); break;
1265 case 6: gen_helper_fdiv_ST0_FT0(); break;
1266 case 7: gen_helper_fdivr_ST0_FT0(); break;
1267 }
1268 }
1269
1270 /* NOTE the exception in "r" op ordering */
1271 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1272 {
1273 TCGv_i32 tmp = tcg_const_i32(opreg);
1274 switch (op) {
1275 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1276 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1277 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1278 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1279 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1280 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1281 }
1282 }
1283
1284 /* if d == OR_TMP0, it means memory operand (address in A0) */
1285 static void gen_op(DisasContext *s1, int op, int ot, int d)
1286 {
1287 if (d != OR_TMP0) {
1288 gen_op_mov_TN_reg(ot, 0, d);
1289 } else {
1290 gen_op_ld_T0_A0(ot + s1->mem_index);
1291 }
1292 switch(op) {
1293 case OP_ADCL:
1294 if (s1->cc_op != CC_OP_DYNAMIC)
1295 gen_op_set_cc_op(s1->cc_op);
1296 gen_compute_eflags_c(cpu_tmp4);
1297 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1298 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1299 if (d != OR_TMP0)
1300 gen_op_mov_reg_T0(ot, d);
1301 else
1302 gen_op_st_T0_A0(ot + s1->mem_index);
1303 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1304 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1305 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1306 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1307 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1308 s1->cc_op = CC_OP_DYNAMIC;
1309 break;
1310 case OP_SBBL:
1311 if (s1->cc_op != CC_OP_DYNAMIC)
1312 gen_op_set_cc_op(s1->cc_op);
1313 gen_compute_eflags_c(cpu_tmp4);
1314 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1315 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1316 if (d != OR_TMP0)
1317 gen_op_mov_reg_T0(ot, d);
1318 else
1319 gen_op_st_T0_A0(ot + s1->mem_index);
1320 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1321 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1322 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1323 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1324 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1325 s1->cc_op = CC_OP_DYNAMIC;
1326 break;
1327 case OP_ADDL:
1328 gen_op_addl_T0_T1();
1329 if (d != OR_TMP0)
1330 gen_op_mov_reg_T0(ot, d);
1331 else
1332 gen_op_st_T0_A0(ot + s1->mem_index);
1333 gen_op_update2_cc();
1334 s1->cc_op = CC_OP_ADDB + ot;
1335 break;
1336 case OP_SUBL:
1337 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1338 if (d != OR_TMP0)
1339 gen_op_mov_reg_T0(ot, d);
1340 else
1341 gen_op_st_T0_A0(ot + s1->mem_index);
1342 gen_op_update2_cc();
1343 s1->cc_op = CC_OP_SUBB + ot;
1344 break;
1345 default:
1346 case OP_ANDL:
1347 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1348 if (d != OR_TMP0)
1349 gen_op_mov_reg_T0(ot, d);
1350 else
1351 gen_op_st_T0_A0(ot + s1->mem_index);
1352 gen_op_update1_cc();
1353 s1->cc_op = CC_OP_LOGICB + ot;
1354 break;
1355 case OP_ORL:
1356 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1357 if (d != OR_TMP0)
1358 gen_op_mov_reg_T0(ot, d);
1359 else
1360 gen_op_st_T0_A0(ot + s1->mem_index);
1361 gen_op_update1_cc();
1362 s1->cc_op = CC_OP_LOGICB + ot;
1363 break;
1364 case OP_XORL:
1365 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1366 if (d != OR_TMP0)
1367 gen_op_mov_reg_T0(ot, d);
1368 else
1369 gen_op_st_T0_A0(ot + s1->mem_index);
1370 gen_op_update1_cc();
1371 s1->cc_op = CC_OP_LOGICB + ot;
1372 break;
1373 case OP_CMPL:
1374 gen_op_cmpl_T0_T1_cc();
1375 s1->cc_op = CC_OP_SUBB + ot;
1376 break;
1377 }
1378 }
1379
1380 /* if d == OR_TMP0, it means memory operand (address in A0) */
1381 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1382 {
1383 if (d != OR_TMP0)
1384 gen_op_mov_TN_reg(ot, 0, d);
1385 else
1386 gen_op_ld_T0_A0(ot + s1->mem_index);
1387 if (s1->cc_op != CC_OP_DYNAMIC)
1388 gen_op_set_cc_op(s1->cc_op);
1389 if (c > 0) {
1390 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1391 s1->cc_op = CC_OP_INCB + ot;
1392 } else {
1393 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1394 s1->cc_op = CC_OP_DECB + ot;
1395 }
1396 if (d != OR_TMP0)
1397 gen_op_mov_reg_T0(ot, d);
1398 else
1399 gen_op_st_T0_A0(ot + s1->mem_index);
1400 gen_compute_eflags_c(cpu_cc_src);
1401 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1402 }
1403
1404 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1405 int is_right, int is_arith)
1406 {
1407 target_ulong mask;
1408 int shift_label;
1409 TCGv t0, t1, t2;
1410
1411 if (ot == OT_QUAD) {
1412 mask = 0x3f;
1413 } else {
1414 mask = 0x1f;
1415 }
1416
1417 /* load */
1418 if (op1 == OR_TMP0) {
1419 gen_op_ld_T0_A0(ot + s->mem_index);
1420 } else {
1421 gen_op_mov_TN_reg(ot, 0, op1);
1422 }
1423
1424 t0 = tcg_temp_local_new();
1425 t1 = tcg_temp_local_new();
1426 t2 = tcg_temp_local_new();
1427
1428 tcg_gen_andi_tl(t2, cpu_T[1], mask);
1429
1430 if (is_right) {
1431 if (is_arith) {
1432 gen_exts(ot, cpu_T[0]);
1433 tcg_gen_mov_tl(t0, cpu_T[0]);
1434 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2);
1435 } else {
1436 gen_extu(ot, cpu_T[0]);
1437 tcg_gen_mov_tl(t0, cpu_T[0]);
1438 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2);
1439 }
1440 } else {
1441 tcg_gen_mov_tl(t0, cpu_T[0]);
1442 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2);
1443 }
1444
1445 /* store */
1446 if (op1 == OR_TMP0) {
1447 gen_op_st_T0_A0(ot + s->mem_index);
1448 } else {
1449 gen_op_mov_reg_T0(ot, op1);
1450 }
1451
1452 /* update eflags if non zero shift */
1453 if (s->cc_op != CC_OP_DYNAMIC) {
1454 gen_op_set_cc_op(s->cc_op);
1455 }
1456
1457 tcg_gen_mov_tl(t1, cpu_T[0]);
1458
1459 shift_label = gen_new_label();
1460 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label);
1461
1462 tcg_gen_addi_tl(t2, t2, -1);
1463 tcg_gen_mov_tl(cpu_cc_dst, t1);
1464
1465 if (is_right) {
1466 if (is_arith) {
1467 tcg_gen_sar_tl(cpu_cc_src, t0, t2);
1468 } else {
1469 tcg_gen_shr_tl(cpu_cc_src, t0, t2);
1470 }
1471 } else {
1472 tcg_gen_shl_tl(cpu_cc_src, t0, t2);
1473 }
1474
1475 if (is_right) {
1476 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1477 } else {
1478 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1479 }
1480
1481 gen_set_label(shift_label);
1482 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1483
1484 tcg_temp_free(t0);
1485 tcg_temp_free(t1);
1486 tcg_temp_free(t2);
1487 }
1488
1489 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1490 int is_right, int is_arith)
1491 {
1492 int mask;
1493
1494 if (ot == OT_QUAD)
1495 mask = 0x3f;
1496 else
1497 mask = 0x1f;
1498
1499 /* load */
1500 if (op1 == OR_TMP0)
1501 gen_op_ld_T0_A0(ot + s->mem_index);
1502 else
1503 gen_op_mov_TN_reg(ot, 0, op1);
1504
1505 op2 &= mask;
1506 if (op2 != 0) {
1507 if (is_right) {
1508 if (is_arith) {
1509 gen_exts(ot, cpu_T[0]);
1510 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1511 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1512 } else {
1513 gen_extu(ot, cpu_T[0]);
1514 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1515 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1516 }
1517 } else {
1518 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1519 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1520 }
1521 }
1522
1523 /* store */
1524 if (op1 == OR_TMP0)
1525 gen_op_st_T0_A0(ot + s->mem_index);
1526 else
1527 gen_op_mov_reg_T0(ot, op1);
1528
1529 /* update eflags if non zero shift */
1530 if (op2 != 0) {
1531 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1532 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1533 if (is_right)
1534 s->cc_op = CC_OP_SARB + ot;
1535 else
1536 s->cc_op = CC_OP_SHLB + ot;
1537 }
1538 }
1539
1540 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1541 {
1542 if (arg2 >= 0)
1543 tcg_gen_shli_tl(ret, arg1, arg2);
1544 else
1545 tcg_gen_shri_tl(ret, arg1, -arg2);
1546 }
1547
1548 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1549 int is_right)
1550 {
1551 target_ulong mask;
1552 int label1, label2, data_bits;
1553 TCGv t0, t1, t2, a0;
1554
1555 /* XXX: inefficient, but we must use local temps */
1556 t0 = tcg_temp_local_new();
1557 t1 = tcg_temp_local_new();
1558 t2 = tcg_temp_local_new();
1559 a0 = tcg_temp_local_new();
1560
1561 if (ot == OT_QUAD)
1562 mask = 0x3f;
1563 else
1564 mask = 0x1f;
1565
1566 /* load */
1567 if (op1 == OR_TMP0) {
1568 tcg_gen_mov_tl(a0, cpu_A0);
1569 gen_op_ld_v(ot + s->mem_index, t0, a0);
1570 } else {
1571 gen_op_mov_v_reg(ot, t0, op1);
1572 }
1573
1574 tcg_gen_mov_tl(t1, cpu_T[1]);
1575
1576 tcg_gen_andi_tl(t1, t1, mask);
1577
1578 /* Must test zero case to avoid using undefined behaviour in TCG
1579 shifts. */
1580 label1 = gen_new_label();
1581 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1582
1583 if (ot <= OT_WORD)
1584 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1585 else
1586 tcg_gen_mov_tl(cpu_tmp0, t1);
1587
1588 gen_extu(ot, t0);
1589 tcg_gen_mov_tl(t2, t0);
1590
1591 data_bits = 8 << ot;
1592 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1593 fix TCG definition) */
1594 if (is_right) {
1595 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1596 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1597 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1598 } else {
1599 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1600 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1601 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1602 }
1603 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1604
1605 gen_set_label(label1);
1606 /* store */
1607 if (op1 == OR_TMP0) {
1608 gen_op_st_v(ot + s->mem_index, t0, a0);
1609 } else {
1610 gen_op_mov_reg_v(ot, op1, t0);
1611 }
1612
1613 /* update eflags */
1614 if (s->cc_op != CC_OP_DYNAMIC)
1615 gen_op_set_cc_op(s->cc_op);
1616
1617 label2 = gen_new_label();
1618 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1619
1620 gen_compute_eflags(cpu_cc_src);
1621 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1622 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1623 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1624 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1625 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1626 if (is_right) {
1627 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1628 }
1629 tcg_gen_andi_tl(t0, t0, CC_C);
1630 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1631
1632 tcg_gen_discard_tl(cpu_cc_dst);
1633 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1634
1635 gen_set_label(label2);
1636 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1637
1638 tcg_temp_free(t0);
1639 tcg_temp_free(t1);
1640 tcg_temp_free(t2);
1641 tcg_temp_free(a0);
1642 }
1643
1644 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1645 int is_right)
1646 {
1647 int mask;
1648 int data_bits;
1649 TCGv t0, t1, a0;
1650
1651 /* XXX: inefficient, but we must use local temps */
1652 t0 = tcg_temp_local_new();
1653 t1 = tcg_temp_local_new();
1654 a0 = tcg_temp_local_new();
1655
1656 if (ot == OT_QUAD)
1657 mask = 0x3f;
1658 else
1659 mask = 0x1f;
1660
1661 /* load */
1662 if (op1 == OR_TMP0) {
1663 tcg_gen_mov_tl(a0, cpu_A0);
1664 gen_op_ld_v(ot + s->mem_index, t0, a0);
1665 } else {
1666 gen_op_mov_v_reg(ot, t0, op1);
1667 }
1668
1669 gen_extu(ot, t0);
1670 tcg_gen_mov_tl(t1, t0);
1671
1672 op2 &= mask;
1673 data_bits = 8 << ot;
1674 if (op2 != 0) {
1675 int shift = op2 & ((1 << (3 + ot)) - 1);
1676 if (is_right) {
1677 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1678 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1679 }
1680 else {
1681 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1682 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1683 }
1684 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1685 }
1686
1687 /* store */
1688 if (op1 == OR_TMP0) {
1689 gen_op_st_v(ot + s->mem_index, t0, a0);
1690 } else {
1691 gen_op_mov_reg_v(ot, op1, t0);
1692 }
1693
1694 if (op2 != 0) {
1695 /* update eflags */
1696 if (s->cc_op != CC_OP_DYNAMIC)
1697 gen_op_set_cc_op(s->cc_op);
1698
1699 gen_compute_eflags(cpu_cc_src);
1700 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1701 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1702 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1703 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1704 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1705 if (is_right) {
1706 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1707 }
1708 tcg_gen_andi_tl(t0, t0, CC_C);
1709 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1710
1711 tcg_gen_discard_tl(cpu_cc_dst);
1712 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1713 s->cc_op = CC_OP_EFLAGS;
1714 }
1715
1716 tcg_temp_free(t0);
1717 tcg_temp_free(t1);
1718 tcg_temp_free(a0);
1719 }
1720
1721 /* XXX: add faster immediate = 1 case */
1722 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1723 int is_right)
1724 {
1725 int label1;
1726
1727 if (s->cc_op != CC_OP_DYNAMIC)
1728 gen_op_set_cc_op(s->cc_op);
1729
1730 /* load */
1731 if (op1 == OR_TMP0)
1732 gen_op_ld_T0_A0(ot + s->mem_index);
1733 else
1734 gen_op_mov_TN_reg(ot, 0, op1);
1735
1736 if (is_right) {
1737 switch (ot) {
1738 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1739 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1740 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1741 #ifdef TARGET_X86_64
1742 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1743 #endif
1744 }
1745 } else {
1746 switch (ot) {
1747 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1748 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1749 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1750 #ifdef TARGET_X86_64
1751 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1752 #endif
1753 }
1754 }
1755 /* store */
1756 if (op1 == OR_TMP0)
1757 gen_op_st_T0_A0(ot + s->mem_index);
1758 else
1759 gen_op_mov_reg_T0(ot, op1);
1760
1761 /* update eflags */
1762 label1 = gen_new_label();
1763 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1764
1765 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1766 tcg_gen_discard_tl(cpu_cc_dst);
1767 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1768
1769 gen_set_label(label1);
1770 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1771 }
1772
1773 /* XXX: add faster immediate case */
1774 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1775 int is_right)
1776 {
1777 int label1, label2, data_bits;
1778 target_ulong mask;
1779 TCGv t0, t1, t2, a0;
1780
1781 t0 = tcg_temp_local_new();
1782 t1 = tcg_temp_local_new();
1783 t2 = tcg_temp_local_new();
1784 a0 = tcg_temp_local_new();
1785
1786 if (ot == OT_QUAD)
1787 mask = 0x3f;
1788 else
1789 mask = 0x1f;
1790
1791 /* load */
1792 if (op1 == OR_TMP0) {
1793 tcg_gen_mov_tl(a0, cpu_A0);
1794 gen_op_ld_v(ot + s->mem_index, t0, a0);
1795 } else {
1796 gen_op_mov_v_reg(ot, t0, op1);
1797 }
1798
1799 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1800
1801 tcg_gen_mov_tl(t1, cpu_T[1]);
1802 tcg_gen_mov_tl(t2, cpu_T3);
1803
1804 /* Must test zero case to avoid using undefined behaviour in TCG
1805 shifts. */
1806 label1 = gen_new_label();
1807 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1808
1809 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1810 if (ot == OT_WORD) {
1811 /* Note: we implement the Intel behaviour for shift count > 16 */
1812 if (is_right) {
1813 tcg_gen_andi_tl(t0, t0, 0xffff);
1814 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1815 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1816 tcg_gen_ext32u_tl(t0, t0);
1817
1818 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1819
1820 /* only needed if count > 16, but a test would complicate */
1821 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1822 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1823
1824 tcg_gen_shr_tl(t0, t0, t2);
1825
1826 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1827 } else {
1828 /* XXX: not optimal */
1829 tcg_gen_andi_tl(t0, t0, 0xffff);
1830 tcg_gen_shli_tl(t1, t1, 16);
1831 tcg_gen_or_tl(t1, t1, t0);
1832 tcg_gen_ext32u_tl(t1, t1);
1833
1834 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1835 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1836 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1837 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1838
1839 tcg_gen_shl_tl(t0, t0, t2);
1840 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1841 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1842 tcg_gen_or_tl(t0, t0, t1);
1843 }
1844 } else {
1845 data_bits = 8 << ot;
1846 if (is_right) {
1847 if (ot == OT_LONG)
1848 tcg_gen_ext32u_tl(t0, t0);
1849
1850 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1851
1852 tcg_gen_shr_tl(t0, t0, t2);
1853 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1854 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1855 tcg_gen_or_tl(t0, t0, t1);
1856
1857 } else {
1858 if (ot == OT_LONG)
1859 tcg_gen_ext32u_tl(t1, t1);
1860
1861 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1862
1863 tcg_gen_shl_tl(t0, t0, t2);
1864 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1865 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1866 tcg_gen_or_tl(t0, t0, t1);
1867 }
1868 }
1869 tcg_gen_mov_tl(t1, cpu_tmp4);
1870
1871 gen_set_label(label1);
1872 /* store */
1873 if (op1 == OR_TMP0) {
1874 gen_op_st_v(ot + s->mem_index, t0, a0);
1875 } else {
1876 gen_op_mov_reg_v(ot, op1, t0);
1877 }
1878
1879 /* update eflags */
1880 if (s->cc_op != CC_OP_DYNAMIC)
1881 gen_op_set_cc_op(s->cc_op);
1882
1883 label2 = gen_new_label();
1884 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1885
1886 tcg_gen_mov_tl(cpu_cc_src, t1);
1887 tcg_gen_mov_tl(cpu_cc_dst, t0);
1888 if (is_right) {
1889 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1890 } else {
1891 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1892 }
1893 gen_set_label(label2);
1894 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1895
1896 tcg_temp_free(t0);
1897 tcg_temp_free(t1);
1898 tcg_temp_free(t2);
1899 tcg_temp_free(a0);
1900 }
1901
1902 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1903 {
1904 if (s != OR_TMP1)
1905 gen_op_mov_TN_reg(ot, 1, s);
1906 switch(op) {
1907 case OP_ROL:
1908 gen_rot_rm_T1(s1, ot, d, 0);
1909 break;
1910 case OP_ROR:
1911 gen_rot_rm_T1(s1, ot, d, 1);
1912 break;
1913 case OP_SHL:
1914 case OP_SHL1:
1915 gen_shift_rm_T1(s1, ot, d, 0, 0);
1916 break;
1917 case OP_SHR:
1918 gen_shift_rm_T1(s1, ot, d, 1, 0);
1919 break;
1920 case OP_SAR:
1921 gen_shift_rm_T1(s1, ot, d, 1, 1);
1922 break;
1923 case OP_RCL:
1924 gen_rotc_rm_T1(s1, ot, d, 0);
1925 break;
1926 case OP_RCR:
1927 gen_rotc_rm_T1(s1, ot, d, 1);
1928 break;
1929 }
1930 }
1931
1932 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1933 {
1934 switch(op) {
1935 case OP_ROL:
1936 gen_rot_rm_im(s1, ot, d, c, 0);
1937 break;
1938 case OP_ROR:
1939 gen_rot_rm_im(s1, ot, d, c, 1);
1940 break;
1941 case OP_SHL:
1942 case OP_SHL1:
1943 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1944 break;
1945 case OP_SHR:
1946 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1947 break;
1948 case OP_SAR:
1949 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1950 break;
1951 default:
1952 /* currently not optimized */
1953 gen_op_movl_T1_im(c);
1954 gen_shift(s1, op, ot, d, OR_TMP1);
1955 break;
1956 }
1957 }
1958
1959 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1960 {
1961 target_long disp;
1962 int havesib;
1963 int base;
1964 int index;
1965 int scale;
1966 int opreg;
1967 int mod, rm, code, override, must_add_seg;
1968
1969 override = s->override;
1970 must_add_seg = s->addseg;
1971 if (override >= 0)
1972 must_add_seg = 1;
1973 mod = (modrm >> 6) & 3;
1974 rm = modrm & 7;
1975
1976 if (s->aflag) {
1977
1978 havesib = 0;
1979 base = rm;
1980 index = 0;
1981 scale = 0;
1982
1983 if (base == 4) {
1984 havesib = 1;
1985 code = ldub_code(s->pc++);
1986 scale = (code >> 6) & 3;
1987 index = ((code >> 3) & 7) | REX_X(s);
1988 base = (code & 7);
1989 }
1990 base |= REX_B(s);
1991
1992 switch (mod) {
1993 case 0:
1994 if ((base & 7) == 5) {
1995 base = -1;
1996 disp = (int32_t)ldl_code(s->pc);
1997 s->pc += 4;
1998 if (CODE64(s) && !havesib) {
1999 disp += s->pc + s->rip_offset;
2000 }
2001 } else {
2002 disp = 0;
2003 }
2004 break;
2005 case 1:
2006 disp = (int8_t)ldub_code(s->pc++);
2007 break;
2008 default:
2009 case 2:
2010 disp = (int32_t)ldl_code(s->pc);
2011 s->pc += 4;
2012 break;
2013 }
2014
2015 if (base >= 0) {
2016 /* for correct popl handling with esp */
2017 if (base == 4 && s->popl_esp_hack)
2018 disp += s->popl_esp_hack;
2019 #ifdef TARGET_X86_64
2020 if (s->aflag == 2) {
2021 gen_op_movq_A0_reg(base);
2022 if (disp != 0) {
2023 gen_op_addq_A0_im(disp);
2024 }
2025 } else
2026 #endif
2027 {
2028 gen_op_movl_A0_reg(base);
2029 if (disp != 0)
2030 gen_op_addl_A0_im(disp);
2031 }
2032 } else {
2033 #ifdef TARGET_X86_64
2034 if (s->aflag == 2) {
2035 gen_op_movq_A0_im(disp);
2036 } else
2037 #endif
2038 {
2039 gen_op_movl_A0_im(disp);
2040 }
2041 }
2042 /* index == 4 means no index */
2043 if (havesib && (index != 4)) {
2044 #ifdef TARGET_X86_64
2045 if (s->aflag == 2) {
2046 gen_op_addq_A0_reg_sN(scale, index);
2047 } else
2048 #endif
2049 {
2050 gen_op_addl_A0_reg_sN(scale, index);
2051 }
2052 }
2053 if (must_add_seg) {
2054 if (override < 0) {
2055 if (base == R_EBP || base == R_ESP)
2056 override = R_SS;
2057 else
2058 override = R_DS;
2059 }
2060 #ifdef TARGET_X86_64
2061 if (s->aflag == 2) {
2062 gen_op_addq_A0_seg(override);
2063 } else
2064 #endif
2065 {
2066 gen_op_addl_A0_seg(override);
2067 }
2068 }
2069 } else {
2070 switch (mod) {
2071 case 0:
2072 if (rm == 6) {
2073 disp = lduw_code(s->pc);
2074 s->pc += 2;
2075 gen_op_movl_A0_im(disp);
2076 rm = 0; /* avoid SS override */
2077 goto no_rm;
2078 } else {
2079 disp = 0;
2080 }
2081 break;
2082 case 1:
2083 disp = (int8_t)ldub_code(s->pc++);
2084 break;
2085 default:
2086 case 2:
2087 disp = lduw_code(s->pc);
2088 s->pc += 2;
2089 break;
2090 }
2091 switch(rm) {
2092 case 0:
2093 gen_op_movl_A0_reg(R_EBX);
2094 gen_op_addl_A0_reg_sN(0, R_ESI);
2095 break;
2096 case 1:
2097 gen_op_movl_A0_reg(R_EBX);
2098 gen_op_addl_A0_reg_sN(0, R_EDI);
2099 break;
2100 case 2:
2101 gen_op_movl_A0_reg(R_EBP);
2102 gen_op_addl_A0_reg_sN(0, R_ESI);
2103 break;
2104 case 3:
2105 gen_op_movl_A0_reg(R_EBP);
2106 gen_op_addl_A0_reg_sN(0, R_EDI);
2107 break;
2108 case 4:
2109 gen_op_movl_A0_reg(R_ESI);
2110 break;
2111 case 5:
2112 gen_op_movl_A0_reg(R_EDI);
2113 break;
2114 case 6:
2115 gen_op_movl_A0_reg(R_EBP);
2116 break;
2117 default:
2118 case 7:
2119 gen_op_movl_A0_reg(R_EBX);
2120 break;
2121 }
2122 if (disp != 0)
2123 gen_op_addl_A0_im(disp);
2124 gen_op_andl_A0_ffff();
2125 no_rm:
2126 if (must_add_seg) {
2127 if (override < 0) {
2128 if (rm == 2 || rm == 3 || rm == 6)
2129 override = R_SS;
2130 else
2131 override = R_DS;
2132 }
2133 gen_op_addl_A0_seg(override);
2134 }
2135 }
2136
2137 opreg = OR_A0;
2138 disp = 0;
2139 *reg_ptr = opreg;
2140 *offset_ptr = disp;
2141 }
2142
2143 static void gen_nop_modrm(DisasContext *s, int modrm)
2144 {
2145 int mod, rm, base, code;
2146
2147 mod = (modrm >> 6) & 3;
2148 if (mod == 3)
2149 return;
2150 rm = modrm & 7;
2151
2152 if (s->aflag) {
2153
2154 base = rm;
2155
2156 if (base == 4) {
2157 code = ldub_code(s->pc++);
2158 base = (code & 7);
2159 }
2160
2161 switch (mod) {
2162 case 0:
2163 if (base == 5) {
2164 s->pc += 4;
2165 }
2166 break;
2167 case 1:
2168 s->pc++;
2169 break;
2170 default:
2171 case 2:
2172 s->pc += 4;
2173 break;
2174 }
2175 } else {
2176 switch (mod) {
2177 case 0:
2178 if (rm == 6) {
2179 s->pc += 2;
2180 }
2181 break;
2182 case 1:
2183 s->pc++;
2184 break;
2185 default:
2186 case 2:
2187 s->pc += 2;
2188 break;
2189 }
2190 }
2191 }
2192
2193 /* used for LEA and MOV AX, mem */
2194 static void gen_add_A0_ds_seg(DisasContext *s)
2195 {
2196 int override, must_add_seg;
2197 must_add_seg = s->addseg;
2198 override = R_DS;
2199 if (s->override >= 0) {
2200 override = s->override;
2201 must_add_seg = 1;
2202 }
2203 if (must_add_seg) {
2204 #ifdef TARGET_X86_64
2205 if (CODE64(s)) {
2206 gen_op_addq_A0_seg(override);
2207 } else
2208 #endif
2209 {
2210 gen_op_addl_A0_seg(override);
2211 }
2212 }
2213 }
2214
2215 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2216 OR_TMP0 */
2217 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2218 {
2219 int mod, rm, opreg, disp;
2220
2221 mod = (modrm >> 6) & 3;
2222 rm = (modrm & 7) | REX_B(s);
2223 if (mod == 3) {
2224 if (is_store) {
2225 if (reg != OR_TMP0)
2226 gen_op_mov_TN_reg(ot, 0, reg);
2227 gen_op_mov_reg_T0(ot, rm);
2228 } else {
2229 gen_op_mov_TN_reg(ot, 0, rm);
2230 if (reg != OR_TMP0)
2231 gen_op_mov_reg_T0(ot, reg);
2232 }
2233 } else {
2234 gen_lea_modrm(s, modrm, &opreg, &disp);
2235 if (is_store) {
2236 if (reg != OR_TMP0)
2237 gen_op_mov_TN_reg(ot, 0, reg);
2238 gen_op_st_T0_A0(ot + s->mem_index);
2239 } else {
2240 gen_op_ld_T0_A0(ot + s->mem_index);
2241 if (reg != OR_TMP0)
2242 gen_op_mov_reg_T0(ot, reg);
2243 }
2244 }
2245 }
2246
2247 static inline uint32_t insn_get(DisasContext *s, int ot)
2248 {
2249 uint32_t ret;
2250
2251 switch(ot) {
2252 case OT_BYTE:
2253 ret = ldub_code(s->pc);
2254 s->pc++;
2255 break;
2256 case OT_WORD:
2257 ret = lduw_code(s->pc);
2258 s->pc += 2;
2259 break;
2260 default:
2261 case OT_LONG:
2262 ret = ldl_code(s->pc);
2263 s->pc += 4;
2264 break;
2265 }
2266 return ret;
2267 }
2268
2269 static inline int insn_const_size(unsigned int ot)
2270 {
2271 if (ot <= OT_LONG)
2272 return 1 << ot;
2273 else
2274 return 4;
2275 }
2276
2277 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2278 {
2279 TranslationBlock *tb;
2280 target_ulong pc;
2281
2282 pc = s->cs_base + eip;
2283 tb = s->tb;
2284 /* NOTE: we handle the case where the TB spans two pages here */
2285 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2286 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2287 /* jump to same page: we can use a direct jump */
2288 tcg_gen_goto_tb(tb_num);
2289 gen_jmp_im(eip);
2290 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
2291 } else {
2292 /* jump to another page: currently not optimized */
2293 gen_jmp_im(eip);
2294 gen_eob(s);
2295 }
2296 }
2297
2298 static inline void gen_jcc(DisasContext *s, int b,
2299 target_ulong val, target_ulong next_eip)
2300 {
2301 int l1, l2, cc_op;
2302
2303 cc_op = s->cc_op;
2304 gen_update_cc_op(s);
2305 if (s->jmp_opt) {
2306 l1 = gen_new_label();
2307 gen_jcc1(s, cc_op, b, l1);
2308
2309 gen_goto_tb(s, 0, next_eip);
2310
2311 gen_set_label(l1);
2312 gen_goto_tb(s, 1, val);
2313 s->is_jmp = DISAS_TB_JUMP;
2314 } else {
2315
2316 l1 = gen_new_label();
2317 l2 = gen_new_label();
2318 gen_jcc1(s, cc_op, b, l1);
2319
2320 gen_jmp_im(next_eip);
2321 tcg_gen_br(l2);
2322
2323 gen_set_label(l1);
2324 gen_jmp_im(val);
2325 gen_set_label(l2);
2326 gen_eob(s);
2327 }
2328 }
2329
2330 static void gen_setcc(DisasContext *s, int b)
2331 {
2332 int inv, jcc_op, l1;
2333 TCGv t0;
2334
2335 if (is_fast_jcc_case(s, b)) {
2336 /* nominal case: we use a jump */
2337 /* XXX: make it faster by adding new instructions in TCG */
2338 t0 = tcg_temp_local_new();
2339 tcg_gen_movi_tl(t0, 0);
2340 l1 = gen_new_label();
2341 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2342 tcg_gen_movi_tl(t0, 1);
2343 gen_set_label(l1);
2344 tcg_gen_mov_tl(cpu_T[0], t0);
2345 tcg_temp_free(t0);
2346 } else {
2347 /* slow case: it is more efficient not to generate a jump,
2348 although it is questionnable whether this optimization is
2349 worth to */
2350 inv = b & 1;
2351 jcc_op = (b >> 1) & 7;
2352 gen_setcc_slow_T0(s, jcc_op);
2353 if (inv) {
2354 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2355 }
2356 }
2357 }
2358
2359 static inline void gen_op_movl_T0_seg(int seg_reg)
2360 {
2361 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2362 offsetof(CPUX86State,segs[seg_reg].selector));
2363 }
2364
2365 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2366 {
2367 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2368 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2369 offsetof(CPUX86State,segs[seg_reg].selector));
2370 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2371 tcg_gen_st_tl(cpu_T[0], cpu_env,
2372 offsetof(CPUX86State,segs[seg_reg].base));
2373 }
2374
2375 /* move T0 to seg_reg and compute if the CPU state may change. Never
2376 call this function with seg_reg == R_CS */
2377 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2378 {
2379 if (s->pe && !s->vm86) {
2380 /* XXX: optimize by finding processor state dynamically */
2381 if (s->cc_op != CC_OP_DYNAMIC)
2382 gen_op_set_cc_op(s->cc_op);
2383 gen_jmp_im(cur_eip);
2384 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2385 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2386 /* abort translation because the addseg value may change or
2387 because ss32 may change. For R_SS, translation must always
2388 stop as a special handling must be done to disable hardware
2389 interrupts for the next instruction */
2390 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2391 s->is_jmp = DISAS_TB_JUMP;
2392 } else {
2393 gen_op_movl_seg_T0_vm(seg_reg);
2394 if (seg_reg == R_SS)
2395 s->is_jmp = DISAS_TB_JUMP;
2396 }
2397 }
2398
2399 static inline int svm_is_rep(int prefixes)
2400 {
2401 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2402 }
2403
2404 static inline void
2405 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2406 uint32_t type, uint64_t param)
2407 {
2408 /* no SVM activated; fast case */
2409 if (likely(!(s->flags & HF_SVMI_MASK)))
2410 return;
2411 if (s->cc_op != CC_OP_DYNAMIC)
2412 gen_op_set_cc_op(s->cc_op);
2413 gen_jmp_im(pc_start - s->cs_base);
2414 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2415 tcg_const_i64(param));
2416 }
2417
2418 static inline void
2419 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2420 {
2421 gen_svm_check_intercept_param(s, pc_start, type, 0);
2422 }
2423
2424 static inline void gen_stack_update(DisasContext *s, int addend)
2425 {
2426 #ifdef TARGET_X86_64
2427 if (CODE64(s)) {
2428 gen_op_add_reg_im(2, R_ESP, addend);
2429 } else
2430 #endif
2431 if (s->ss32) {
2432 gen_op_add_reg_im(1, R_ESP, addend);
2433 } else {
2434 gen_op_add_reg_im(0, R_ESP, addend);
2435 }
2436 }
2437
2438 /* generate a push. It depends on ss32, addseg and dflag */
2439 static void gen_push_T0(DisasContext *s)
2440 {
2441 #ifdef TARGET_X86_64
2442 if (CODE64(s)) {
2443 gen_op_movq_A0_reg(R_ESP);
2444 if (s->dflag) {
2445 gen_op_addq_A0_im(-8);
2446 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2447 } else {
2448 gen_op_addq_A0_im(-2);
2449 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2450 }
2451 gen_op_mov_reg_A0(2, R_ESP);
2452 } else
2453 #endif
2454 {
2455 gen_op_movl_A0_reg(R_ESP);
2456 if (!s->dflag)
2457 gen_op_addl_A0_im(-2);
2458 else
2459 gen_op_addl_A0_im(-4);
2460 if (s->ss32) {
2461 if (s->addseg) {
2462 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2463 gen_op_addl_A0_seg(R_SS);
2464 }
2465 } else {
2466 gen_op_andl_A0_ffff();
2467 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2468 gen_op_addl_A0_seg(R_SS);
2469 }
2470 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2471 if (s->ss32 && !s->addseg)
2472 gen_op_mov_reg_A0(1, R_ESP);
2473 else
2474 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2475 }
2476 }
2477
2478 /* generate a push. It depends on ss32, addseg and dflag */
2479 /* slower version for T1, only used for call Ev */
2480 static void gen_push_T1(DisasContext *s)
2481 {
2482 #ifdef TARGET_X86_64
2483 if (CODE64(s)) {
2484 gen_op_movq_A0_reg(R_ESP);
2485 if (s->dflag) {
2486 gen_op_addq_A0_im(-8);
2487 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2488 } else {
2489 gen_op_addq_A0_im(-2);
2490 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2491 }
2492 gen_op_mov_reg_A0(2, R_ESP);
2493 } else
2494 #endif
2495 {
2496 gen_op_movl_A0_reg(R_ESP);
2497 if (!s->dflag)
2498 gen_op_addl_A0_im(-2);
2499 else
2500 gen_op_addl_A0_im(-4);
2501 if (s->ss32) {
2502 if (s->addseg) {
2503 gen_op_addl_A0_seg(R_SS);
2504 }
2505 } else {
2506 gen_op_andl_A0_ffff();
2507 gen_op_addl_A0_seg(R_SS);
2508 }
2509 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2510
2511 if (s->ss32 && !s->addseg)
2512 gen_op_mov_reg_A0(1, R_ESP);
2513 else
2514 gen_stack_update(s, (-2) << s->dflag);
2515 }
2516 }
2517
2518 /* two step pop is necessary for precise exceptions */
2519 static void gen_pop_T0(DisasContext *s)
2520 {
2521 #ifdef TARGET_X86_64
2522 if (CODE64(s)) {
2523 gen_op_movq_A0_reg(R_ESP);
2524 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2525 } else
2526 #endif
2527 {
2528 gen_op_movl_A0_reg(R_ESP);
2529 if (s->ss32) {
2530 if (s->addseg)
2531 gen_op_addl_A0_seg(R_SS);
2532 } else {
2533 gen_op_andl_A0_ffff();
2534 gen_op_addl_A0_seg(R_SS);
2535 }
2536 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2537 }
2538 }
2539
2540 static void gen_pop_update(DisasContext *s)
2541 {
2542 #ifdef TARGET_X86_64
2543 if (CODE64(s) && s->dflag) {
2544 gen_stack_update(s, 8);
2545 } else
2546 #endif
2547 {
2548 gen_stack_update(s, 2 << s->dflag);
2549 }
2550 }
2551
2552 static void gen_stack_A0(DisasContext *s)
2553 {
2554 gen_op_movl_A0_reg(R_ESP);
2555 if (!s->ss32)
2556 gen_op_andl_A0_ffff();
2557 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2558 if (s->addseg)
2559 gen_op_addl_A0_seg(R_SS);
2560 }
2561
2562 /* NOTE: wrap around in 16 bit not fully handled */
2563 static void gen_pusha(DisasContext *s)
2564 {
2565 int i;
2566 gen_op_movl_A0_reg(R_ESP);
2567 gen_op_addl_A0_im(-16 << s->dflag);
2568 if (!s->ss32)
2569 gen_op_andl_A0_ffff();
2570 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2571 if (s->addseg)
2572 gen_op_addl_A0_seg(R_SS);
2573 for(i = 0;i < 8; i++) {
2574 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2575 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2576 gen_op_addl_A0_im(2 << s->dflag);
2577 }
2578 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2579 }
2580
2581 /* NOTE: wrap around in 16 bit not fully handled */
2582 static void gen_popa(DisasContext *s)
2583 {
2584 int i;
2585 gen_op_movl_A0_reg(R_ESP);
2586 if (!s->ss32)
2587 gen_op_andl_A0_ffff();
2588 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2589 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2590 if (s->addseg)
2591 gen_op_addl_A0_seg(R_SS);
2592 for(i = 0;i < 8; i++) {
2593 /* ESP is not reloaded */
2594 if (i != 3) {
2595 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2596 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2597 }
2598 gen_op_addl_A0_im(2 << s->dflag);
2599 }
2600 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2601 }
2602
2603 static void gen_enter(DisasContext *s, int esp_addend, int level)
2604 {
2605 int ot, opsize;
2606
2607 level &= 0x1f;
2608 #ifdef TARGET_X86_64
2609 if (CODE64(s)) {
2610 ot = s->dflag ? OT_QUAD : OT_WORD;
2611 opsize = 1 << ot;
2612
2613 gen_op_movl_A0_reg(R_ESP);
2614 gen_op_addq_A0_im(-opsize);
2615 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2616
2617 /* push bp */
2618 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2619 gen_op_st_T0_A0(ot + s->mem_index);
2620 if (level) {
2621 /* XXX: must save state */
2622 gen_helper_enter64_level(tcg_const_i32(level),
2623 tcg_const_i32((ot == OT_QUAD)),
2624 cpu_T[1]);
2625 }
2626 gen_op_mov_reg_T1(ot, R_EBP);
2627 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2628 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2629 } else
2630 #endif
2631 {
2632 ot = s->dflag + OT_WORD;
2633 opsize = 2 << s->dflag;
2634
2635 gen_op_movl_A0_reg(R_ESP);
2636 gen_op_addl_A0_im(-opsize);
2637 if (!s->ss32)
2638 gen_op_andl_A0_ffff();
2639 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2640 if (s->addseg)
2641 gen_op_addl_A0_seg(R_SS);
2642 /* push bp */
2643 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2644 gen_op_st_T0_A0(ot + s->mem_index);
2645 if (level) {
2646 /* XXX: must save state */
2647 gen_helper_enter_level(tcg_const_i32(level),
2648 tcg_const_i32(s->dflag),
2649 cpu_T[1]);
2650 }
2651 gen_op_mov_reg_T1(ot, R_EBP);
2652 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2653 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2654 }
2655 }
2656
2657 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2658 {
2659 if (s->cc_op != CC_OP_DYNAMIC)
2660 gen_op_set_cc_op(s->cc_op);
2661 gen_jmp_im(cur_eip);
2662 gen_helper_raise_exception(tcg_const_i32(trapno));
2663 s->is_jmp = DISAS_TB_JUMP;
2664 }
2665
2666 /* an interrupt is different from an exception because of the
2667 privilege checks */
2668 static void gen_interrupt(DisasContext *s, int intno,
2669 target_ulong cur_eip, target_ulong next_eip)
2670 {
2671 if (s->cc_op != CC_OP_DYNAMIC)
2672 gen_op_set_cc_op(s->cc_op);
2673 gen_jmp_im(cur_eip);
2674 gen_helper_raise_interrupt(tcg_const_i32(intno),
2675 tcg_const_i32(next_eip - cur_eip));
2676 s->is_jmp = DISAS_TB_JUMP;
2677 }
2678
2679 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2680 {
2681 if (s->cc_op != CC_OP_DYNAMIC)
2682 gen_op_set_cc_op(s->cc_op);
2683 gen_jmp_im(cur_eip);
2684 gen_helper_debug();
2685 s->is_jmp = DISAS_TB_JUMP;
2686 }
2687
2688 /* generate a generic end of block. Trace exception is also generated
2689 if needed */
2690 static void gen_eob(DisasContext *s)
2691 {
2692 if (s->cc_op != CC_OP_DYNAMIC)
2693 gen_op_set_cc_op(s->cc_op);
2694 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2695 gen_helper_reset_inhibit_irq();
2696 }
2697 if (s->tb->flags & HF_RF_MASK) {
2698 gen_helper_reset_rf();
2699 }
2700 if (s->singlestep_enabled) {
2701 gen_helper_debug();
2702 } else if (s->tf) {
2703 gen_helper_single_step();
2704 } else {
2705 tcg_gen_exit_tb(0);
2706 }
2707 s->is_jmp = DISAS_TB_JUMP;
2708 }
2709
2710 /* generate a jump to eip. No segment change must happen before as a
2711 direct call to the next block may occur */
2712 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2713 {
2714 if (s->jmp_opt) {
2715 gen_update_cc_op(s);
2716 gen_goto_tb(s, tb_num, eip);
2717 s->is_jmp = DISAS_TB_JUMP;
2718 } else {
2719 gen_jmp_im(eip);
2720 gen_eob(s);
2721 }
2722 }
2723
2724 static void gen_jmp(DisasContext *s, target_ulong eip)
2725 {
2726 gen_jmp_tb(s, eip, 0);
2727 }
2728
2729 static inline void gen_ldq_env_A0(int idx, int offset)
2730 {
2731 int mem_index = (idx >> 2) - 1;
2732 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2733 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2734 }
2735
2736 static inline void gen_stq_env_A0(int idx, int offset)
2737 {
2738 int mem_index = (idx >> 2) - 1;
2739 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2740 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2741 }
2742
2743 static inline void gen_ldo_env_A0(int idx, int offset)
2744 {
2745 int mem_index = (idx >> 2) - 1;
2746 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2747 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2748 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2749 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2750 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2751 }
2752
2753 static inline void gen_sto_env_A0(int idx, int offset)
2754 {
2755 int mem_index = (idx >> 2) - 1;
2756 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2757 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2758 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2759 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2760 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2761 }
2762
2763 static inline void gen_op_movo(int d_offset, int s_offset)
2764 {
2765 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2766 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2767 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2768 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2769 }
2770
2771 static inline void gen_op_movq(int d_offset, int s_offset)
2772 {
2773 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2774 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2775 }
2776
2777 static inline void gen_op_movl(int d_offset, int s_offset)
2778 {
2779 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2780 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2781 }
2782
2783 static inline void gen_op_movq_env_0(int d_offset)
2784 {
2785 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2786 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2787 }
2788
2789 #define SSE_SPECIAL ((void *)1)
2790 #define SSE_DUMMY ((void *)2)
2791
2792 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2793 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2794 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2795
2796 static void *sse_op_table1[256][4] = {
2797 /* 3DNow! extensions */
2798 [0x0e] = { SSE_DUMMY }, /* femms */
2799 [0x0f] = { SSE_DUMMY }, /* pf... */
2800 /* pure SSE operations */
2801 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2802 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2803 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2804 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2805 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2806 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2807 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2808 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2809
2810 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2811 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2812 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2813 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2814 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2815 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2816 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2817 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2818 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2819 [0x51] = SSE_FOP(sqrt),
2820 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2821 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2822 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2823 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2824 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2825 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2826 [0x58] = SSE_FOP(add),
2827 [0x59] = SSE_FOP(mul),
2828 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2829 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2830 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2831 [0x5c] = SSE_FOP(sub),
2832 [0x5d] = SSE_FOP(min),
2833 [0x5e] = SSE_FOP(div),
2834 [0x5f] = SSE_FOP(max),
2835
2836 [0xc2] = SSE_FOP(cmpeq),
2837 [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
2838
2839 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2840 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2841
2842 /* MMX ops and their SSE extensions */
2843 [0x60] = MMX_OP2(punpcklbw),
2844 [0x61] = MMX_OP2(punpcklwd),
2845 [0x62] = MMX_OP2(punpckldq),
2846 [0x63] = MMX_OP2(packsswb),
2847 [0x64] = MMX_OP2(pcmpgtb),
2848 [0x65] = MMX_OP2(pcmpgtw),
2849 [0x66] = MMX_OP2(pcmpgtl),
2850 [0x67] = MMX_OP2(packuswb),
2851 [0x68] = MMX_OP2(punpckhbw),
2852 [0x69] = MMX_OP2(punpckhwd),
2853 [0x6a] = MMX_OP2(punpckhdq),
2854 [0x6b] = MMX_OP2(packssdw),
2855 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2856 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2857 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2858 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2859 [0x70] = { gen_helper_pshufw_mmx,
2860 gen_helper_pshufd_xmm,
2861 gen_helper_pshufhw_xmm,
2862 gen_helper_pshuflw_xmm },
2863 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2864 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2865 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2866 [0x74] = MMX_OP2(pcmpeqb),
2867 [0x75] = MMX_OP2(pcmpeqw),
2868 [0x76] = MMX_OP2(pcmpeql),
2869 [0x77] = { SSE_DUMMY }, /* emms */
2870 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2871 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2872 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2873 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2874 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2875 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2876 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2877 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2878 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2879 [0xd1] = MMX_OP2(psrlw),
2880 [0xd2] = MMX_OP2(psrld),
2881 [0xd3] = MMX_OP2(psrlq),
2882 [0xd4] = MMX_OP2(paddq),
2883 [0xd5] = MMX_OP2(pmullw),
2884 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2885 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2886 [0xd8] = MMX_OP2(psubusb),
2887 [0xd9] = MMX_OP2(psubusw),
2888 [0xda] = MMX_OP2(pminub),
2889 [0xdb] = MMX_OP2(pand),
2890 [0xdc] = MMX_OP2(paddusb),
2891 [0xdd] = MMX_OP2(paddusw),
2892 [0xde] = MMX_OP2(pmaxub),
2893 [0xdf] = MMX_OP2(pandn),
2894 [0xe0] = MMX_OP2(pavgb),
2895 [0xe1] = MMX_OP2(psraw),
2896 [0xe2] = MMX_OP2(psrad),
2897 [0xe3] = MMX_OP2(pavgw),
2898 [0xe4] = MMX_OP2(pmulhuw),
2899 [0xe5] = MMX_OP2(pmulhw),
2900 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2901 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2902 [0xe8] = MMX_OP2(psubsb),
2903 [0xe9] = MMX_OP2(psubsw),
2904 [0xea] = MMX_OP2(pminsw),
2905 [0xeb] = MMX_OP2(por),
2906 [0xec] = MMX_OP2(paddsb),
2907 [0xed] = MMX_OP2(paddsw),
2908 [0xee] = MMX_OP2(pmaxsw),
2909 [0xef] = MMX_OP2(pxor),
2910 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2911 [0xf1] = MMX_OP2(psllw),
2912 [0xf2] = MMX_OP2(pslld),
2913 [0xf3] = MMX_OP2(psllq),
2914 [0xf4] = MMX_OP2(pmuludq),
2915 [0xf5] = MMX_OP2(pmaddwd),
2916 [0xf6] = MMX_OP2(psadbw),
2917 [0xf7] = MMX_OP2(maskmov),
2918 [0xf8] = MMX_OP2(psubb),
2919 [0xf9] = MMX_OP2(psubw),
2920 [0xfa] = MMX_OP2(psubl),
2921 [0xfb] = MMX_OP2(psubq),
2922 [0xfc] = MMX_OP2(paddb),
2923 [0xfd] = MMX_OP2(paddw),
2924 [0xfe] = MMX_OP2(paddl),
2925 };
2926
2927 static void *sse_op_table2[3 * 8][2] = {
2928 [0 + 2] = MMX_OP2(psrlw),
2929 [0 + 4] = MMX_OP2(psraw),
2930 [0 + 6] = MMX_OP2(psllw),
2931 [8 + 2] = MMX_OP2(psrld),
2932 [8 + 4] = MMX_OP2(psrad),
2933 [8 + 6] = MMX_OP2(pslld),
2934 [16 + 2] = MMX_OP2(psrlq),
2935 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2936 [16 + 6] = MMX_OP2(psllq),
2937 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2938 };
2939
2940 static void *sse_op_table3[4 * 3] = {
2941 gen_helper_cvtsi2ss,
2942 gen_helper_cvtsi2sd,
2943 X86_64_ONLY(gen_helper_cvtsq2ss),
2944 X86_64_ONLY(gen_helper_cvtsq2sd),
2945
2946 gen_helper_cvttss2si,
2947 gen_helper_cvttsd2si,
2948 X86_64_ONLY(gen_helper_cvttss2sq),
2949 X86_64_ONLY(gen_helper_cvttsd2sq),
2950
2951 gen_helper_cvtss2si,
2952 gen_helper_cvtsd2si,
2953 X86_64_ONLY(gen_helper_cvtss2sq),
2954 X86_64_ONLY(gen_helper_cvtsd2sq),
2955 };
2956
2957 static void *sse_op_table4[8][4] = {
2958 SSE_FOP(cmpeq),
2959 SSE_FOP(cmplt),
2960 SSE_FOP(cmple),
2961 SSE_FOP(cmpunord),
2962 SSE_FOP(cmpneq),
2963 SSE_FOP(cmpnlt),
2964 SSE_FOP(cmpnle),
2965 SSE_FOP(cmpord),
2966 };
2967
2968 static void *sse_op_table5[256] = {
2969 [0x0c] = gen_helper_pi2fw,
2970 [0x0d] = gen_helper_pi2fd,
2971 [0x1c] = gen_helper_pf2iw,
2972 [0x1d] = gen_helper_pf2id,
2973 [0x8a] = gen_helper_pfnacc,
2974 [0x8e] = gen_helper_pfpnacc,
2975 [0x90] = gen_helper_pfcmpge,
2976 [0x94] = gen_helper_pfmin,
2977 [0x96] = gen_helper_pfrcp,
2978 [0x97] = gen_helper_pfrsqrt,
2979 [0x9a] = gen_helper_pfsub,
2980 [0x9e] = gen_helper_pfadd,
2981 [0xa0] = gen_helper_pfcmpgt,
2982 [0xa4] = gen_helper_pfmax,
2983 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
2984 [0xa7] = gen_helper_movq, /* pfrsqit1 */
2985 [0xaa] = gen_helper_pfsubr,
2986 [0xae] = gen_helper_pfacc,
2987 [0xb0] = gen_helper_pfcmpeq,
2988 [0xb4] = gen_helper_pfmul,
2989 [0xb6] = gen_helper_movq, /* pfrcpit2 */
2990 [0xb7] = gen_helper_pmulhrw_mmx,
2991 [0xbb] = gen_helper_pswapd,
2992 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
2993 };
2994
2995 struct sse_op_helper_s {
2996 void *op[2]; uint32_t ext_mask;
2997 };
2998 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2999 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3000 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3001 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3002 static struct sse_op_helper_s sse_op_table6[256] = {
3003 [0x00] = SSSE3_OP(pshufb),
3004 [0x01] = SSSE3_OP(phaddw),
3005 [0x02] = SSSE3_OP(phaddd),
3006 [0x03] = SSSE3_OP(phaddsw),
3007 [0x04] = SSSE3_OP(pmaddubsw),
3008 [0x05] = SSSE3_OP(phsubw),
3009 [0x06] = SSSE3_OP(phsubd),
3010 [0x07] = SSSE3_OP(phsubsw),
3011 [0x08] = SSSE3_OP(psignb),
3012 [0x09] = SSSE3_OP(psignw),
3013 [0x0a] = SSSE3_OP(psignd),
3014 [0x0b] = SSSE3_OP(pmulhrsw),
3015 [0x10] = SSE41_OP(pblendvb),
3016 [0x14] = SSE41_OP(blendvps),
3017 [0x15] = SSE41_OP(blendvpd),
3018 [0x17] = SSE41_OP(ptest),
3019 [0x1c] = SSSE3_OP(pabsb),
3020 [0x1d] = SSSE3_OP(pabsw),
3021 [0x1e] = SSSE3_OP(pabsd),
3022 [0x20] = SSE41_OP(pmovsxbw),
3023 [0x21] = SSE41_OP(pmovsxbd),
3024 [0x22] = SSE41_OP(pmovsxbq),
3025 [0x23] = SSE41_OP(pmovsxwd),
3026 [0x24] = SSE41_OP(pmovsxwq),
3027 [0x25] = SSE41_OP(pmovsxdq),
3028 [0x28] = SSE41_OP(pmuldq),
3029 [0x29] = SSE41_OP(pcmpeqq),
3030 [0x2a] = SSE41_SPECIAL, /* movntqda */
3031 [0x2b] = SSE41_OP(packusdw),
3032 [0x30] = SSE41_OP(pmovzxbw),
3033 [0x31] = SSE41_OP(pmovzxbd),
3034 [0x32] = SSE41_OP(pmovzxbq),
3035 [0x33] = SSE41_OP(pmovzxwd),
3036 [0x34] = SSE41_OP(pmovzxwq),
3037 [0x35] = SSE41_OP(pmovzxdq),
3038 [0x37] = SSE42_OP(pcmpgtq),
3039 [0x38] = SSE41_OP(pminsb),
3040 [0x39] = SSE41_OP(pminsd),
3041 [0x3a] = SSE41_OP(pminuw),
3042 [0x3b] = SSE41_OP(pminud),
3043 [0x3c] = SSE41_OP(pmaxsb),
3044 [0x3d] = SSE41_OP(pmaxsd),
3045 [0x3e] = SSE41_OP(pmaxuw),
3046 [0x3f] = SSE41_OP(pmaxud),
3047 [0x40] = SSE41_OP(pmulld),
3048 [0x41] = SSE41_OP(phminposuw),
3049 };
3050
3051 static struct sse_op_helper_s sse_op_table7[256] = {
3052 [0x08] = SSE41_OP(roundps),
3053 [0x09] = SSE41_OP(roundpd),
3054 [0x0a] = SSE41_OP(roundss),
3055 [0x0b] = SSE41_OP(roundsd),
3056 [0x0c] = SSE41_OP(blendps),
3057 [0x0d] = SSE41_OP(blendpd),
3058 [0x0e] = SSE41_OP(pblendw),
3059 [0x0f] = SSSE3_OP(palignr),
3060 [0x14] = SSE41_SPECIAL, /* pextrb */
3061 [0x15] = SSE41_SPECIAL, /* pextrw */
3062 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3063 [0x17] = SSE41_SPECIAL, /* extractps */
3064 [0x20] = SSE41_SPECIAL, /* pinsrb */
3065 [0x21] = SSE41_SPECIAL, /* insertps */
3066 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3067 [0x40] = SSE41_OP(dpps),
3068 [0x41] = SSE41_OP(dppd),
3069 [0x42] = SSE41_OP(mpsadbw),
3070 [0x60] = SSE42_OP(pcmpestrm),
3071 [0x61] = SSE42_OP(pcmpestri),
3072 [0x62] = SSE42_OP(pcmpistrm),
3073 [0x63] = SSE42_OP(pcmpistri),
3074 };
3075
3076 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3077 {
3078 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3079 int modrm, mod, rm, reg, reg_addr, offset_addr;
3080 void *sse_op2;
3081
3082 b &= 0xff;
3083 if (s->prefix & PREFIX_DATA)
3084 b1 = 1;
3085 else if (s->prefix & PREFIX_REPZ)
3086 b1 = 2;
3087 else if (s->prefix & PREFIX_REPNZ)
3088 b1 = 3;
3089 else
3090 b1 = 0;
3091 sse_op2 = sse_op_table1[b][b1];
3092 if (!sse_op2)
3093 goto illegal_op;
3094 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3095 is_xmm = 1;
3096 } else {
3097 if (b1 == 0) {
3098 /* MMX case */
3099 is_xmm = 0;
3100 } else {
3101 is_xmm = 1;
3102 }
3103 }
3104 /* simple MMX/SSE operation */
3105 if (s->flags & HF_TS_MASK) {
3106 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3107 return;
3108 }
3109 if (s->flags & HF_EM_MASK) {
3110 illegal_op:
3111 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3112 return;
3113 }
3114 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3115 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3116 goto illegal_op;
3117 if (b == 0x0e) {
3118 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3119 goto illegal_op;
3120 /* femms */
3121 gen_helper_emms();
3122 return;
3123 }
3124 if (b == 0x77) {
3125 /* emms */
3126 gen_helper_emms();
3127 return;
3128 }
3129 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3130 the static cpu state) */
3131 if (!is_xmm) {
3132 gen_helper_enter_mmx();
3133 }
3134
3135 modrm = ldub_code(s->pc++);
3136 reg = ((modrm >> 3) & 7);
3137 if (is_xmm)
3138 reg |= rex_r;
3139 mod = (modrm >> 6) & 3;
3140 if (sse_op2 == SSE_SPECIAL) {
3141 b |= (b1 << 8);
3142 switch(b) {
3143 case 0x0e7: /* movntq */
3144 if (mod == 3)
3145 goto illegal_op;
3146 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3147 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3148 break;
3149 case 0x1e7: /* movntdq */
3150 case 0x02b: /* movntps */
3151 case 0x12b: /* movntps */
3152 if (mod == 3)
3153 goto illegal_op;
3154 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3155 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3156 break;
3157 case 0x3f0: /* lddqu */
3158 if (mod == 3)
3159 goto illegal_op;
3160 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3161 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3162 break;
3163 case 0x22b: /* movntss */
3164 case 0x32b: /* movntsd */
3165 if (mod == 3)
3166 goto illegal_op;
3167 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3168 if (b1 & 1) {
3169 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3170 xmm_regs[reg]));
3171 } else {
3172 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3173 xmm_regs[reg].XMM_L(0)));
3174 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3175 }
3176 break;
3177 case 0x6e: /* movd mm, ea */
3178 #ifdef TARGET_X86_64
3179 if (s->dflag == 2) {
3180 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3181 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3182 } else
3183 #endif
3184 {
3185 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3186 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3187 offsetof(CPUX86State,fpregs[reg].mmx));
3188 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3189 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3190 }
3191 break;
3192 case 0x16e: /* movd xmm, ea */
3193 #ifdef TARGET_X86_64
3194 if (s->dflag == 2) {
3195 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3196 tcg_gen_addi_ptr(cpu_ptr0, cpu_env