exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argument
[qemu.git] / target-lm32 / helper.c
1 /*
2 * LatticeMico32 helper routines.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22
23 int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
24 int mmu_idx)
25 {
26 LM32CPU *cpu = LM32_CPU(cs);
27 CPULM32State *env = &cpu->env;
28 int prot;
29
30 address &= TARGET_PAGE_MASK;
31 prot = PAGE_BITS;
32 if (env->flags & LM32_FLAG_IGNORE_MSB) {
33 tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
34 TARGET_PAGE_SIZE);
35 } else {
36 tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
37 }
38
39 return 0;
40 }
41
42 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
43 {
44 LM32CPU *cpu = LM32_CPU(cs);
45
46 addr &= TARGET_PAGE_MASK;
47 if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
48 return addr & 0x7fffffff;
49 } else {
50 return addr;
51 }
52 }
53
54 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
55 {
56 LM32CPU *cpu = lm32_env_get_cpu(env);
57
58 cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
59 &env->cpu_breakpoint[idx]);
60 }
61
62 void lm32_breakpoint_remove(CPULM32State *env, int idx)
63 {
64 LM32CPU *cpu = lm32_env_get_cpu(env);
65
66 if (!env->cpu_breakpoint[idx]) {
67 return;
68 }
69
70 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
71 env->cpu_breakpoint[idx] = NULL;
72 }
73
74 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
75 lm32_wp_t wp_type)
76 {
77 LM32CPU *cpu = lm32_env_get_cpu(env);
78 int flags = 0;
79
80 switch (wp_type) {
81 case LM32_WP_DISABLED:
82 /* nothing to to */
83 break;
84 case LM32_WP_READ:
85 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
86 break;
87 case LM32_WP_WRITE:
88 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
89 break;
90 case LM32_WP_READ_WRITE:
91 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
92 break;
93 }
94
95 if (flags != 0) {
96 cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
97 &env->cpu_watchpoint[idx]);
98 }
99 }
100
101 void lm32_watchpoint_remove(CPULM32State *env, int idx)
102 {
103 LM32CPU *cpu = lm32_env_get_cpu(env);
104
105 if (!env->cpu_watchpoint[idx]) {
106 return;
107 }
108
109 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
110 env->cpu_watchpoint[idx] = NULL;
111 }
112
113 static bool check_watchpoints(CPULM32State *env)
114 {
115 LM32CPU *cpu = lm32_env_get_cpu(env);
116 int i;
117
118 for (i = 0; i < cpu->num_watchpoints; i++) {
119 if (env->cpu_watchpoint[i] &&
120 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
121 return true;
122 }
123 }
124 return false;
125 }
126
127 void lm32_debug_excp_handler(CPULM32State *env)
128 {
129 CPUState *cs = CPU(lm32_env_get_cpu(env));
130 CPUBreakpoint *bp;
131
132 if (cs->watchpoint_hit) {
133 if (cs->watchpoint_hit->flags & BP_CPU) {
134 cs->watchpoint_hit = NULL;
135 if (check_watchpoints(env)) {
136 raise_exception(env, EXCP_WATCHPOINT);
137 } else {
138 cpu_resume_from_signal(env, NULL);
139 }
140 }
141 } else {
142 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
143 if (bp->pc == env->pc) {
144 if (bp->flags & BP_CPU) {
145 raise_exception(env, EXCP_BREAKPOINT);
146 }
147 break;
148 }
149 }
150 }
151 }
152
153 void lm32_cpu_do_interrupt(CPUState *cs)
154 {
155 LM32CPU *cpu = LM32_CPU(cs);
156 CPULM32State *env = &cpu->env;
157
158 qemu_log_mask(CPU_LOG_INT,
159 "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
160
161 switch (cs->exception_index) {
162 case EXCP_INSN_BUS_ERROR:
163 case EXCP_DATA_BUS_ERROR:
164 case EXCP_DIVIDE_BY_ZERO:
165 case EXCP_IRQ:
166 case EXCP_SYSTEMCALL:
167 /* non-debug exceptions */
168 env->regs[R_EA] = env->pc;
169 env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
170 env->ie &= ~IE_IE;
171 if (env->dc & DC_RE) {
172 env->pc = env->deba + (cs->exception_index * 32);
173 } else {
174 env->pc = env->eba + (cs->exception_index * 32);
175 }
176 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
177 break;
178 case EXCP_BREAKPOINT:
179 case EXCP_WATCHPOINT:
180 /* debug exceptions */
181 env->regs[R_BA] = env->pc;
182 env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
183 env->ie &= ~IE_IE;
184 env->pc = env->deba + (cs->exception_index * 32);
185 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
186 break;
187 default:
188 cpu_abort(env, "unhandled exception type=%d\n",
189 cs->exception_index);
190 break;
191 }
192 }
193
194 LM32CPU *cpu_lm32_init(const char *cpu_model)
195 {
196 return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
197 }
198
199 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
200 * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
201 * 0x80000000-0xffffffff is not cached and used to access IO devices. */
202 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
203 {
204 if (value) {
205 env->flags |= LM32_FLAG_IGNORE_MSB;
206 } else {
207 env->flags &= ~LM32_FLAG_IGNORE_MSB;
208 }
209 }