migration: convert unix socket protocol to use QIOChannel
[qemu.git] / target-lm32 / helper.c
1 /*
2 * LatticeMico32 helper routines.
3 *
4 * Copyright (c) 2010-2014 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "qemu/host-utils.h"
24 #include "sysemu/sysemu.h"
25 #include "exec/semihost.h"
26 #include "exec/log.h"
27
28 int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
29 int mmu_idx)
30 {
31 LM32CPU *cpu = LM32_CPU(cs);
32 CPULM32State *env = &cpu->env;
33 int prot;
34
35 address &= TARGET_PAGE_MASK;
36 prot = PAGE_BITS;
37 if (env->flags & LM32_FLAG_IGNORE_MSB) {
38 tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
39 TARGET_PAGE_SIZE);
40 } else {
41 tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
42 }
43
44 return 0;
45 }
46
47 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
48 {
49 LM32CPU *cpu = LM32_CPU(cs);
50
51 addr &= TARGET_PAGE_MASK;
52 if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
53 return addr & 0x7fffffff;
54 } else {
55 return addr;
56 }
57 }
58
59 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
60 {
61 LM32CPU *cpu = lm32_env_get_cpu(env);
62
63 cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
64 &env->cpu_breakpoint[idx]);
65 }
66
67 void lm32_breakpoint_remove(CPULM32State *env, int idx)
68 {
69 LM32CPU *cpu = lm32_env_get_cpu(env);
70
71 if (!env->cpu_breakpoint[idx]) {
72 return;
73 }
74
75 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
76 env->cpu_breakpoint[idx] = NULL;
77 }
78
79 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
80 lm32_wp_t wp_type)
81 {
82 LM32CPU *cpu = lm32_env_get_cpu(env);
83 int flags = 0;
84
85 switch (wp_type) {
86 case LM32_WP_DISABLED:
87 /* nothing to do */
88 break;
89 case LM32_WP_READ:
90 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
91 break;
92 case LM32_WP_WRITE:
93 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
94 break;
95 case LM32_WP_READ_WRITE:
96 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
97 break;
98 }
99
100 if (flags != 0) {
101 cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
102 &env->cpu_watchpoint[idx]);
103 }
104 }
105
106 void lm32_watchpoint_remove(CPULM32State *env, int idx)
107 {
108 LM32CPU *cpu = lm32_env_get_cpu(env);
109
110 if (!env->cpu_watchpoint[idx]) {
111 return;
112 }
113
114 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
115 env->cpu_watchpoint[idx] = NULL;
116 }
117
118 static bool check_watchpoints(CPULM32State *env)
119 {
120 LM32CPU *cpu = lm32_env_get_cpu(env);
121 int i;
122
123 for (i = 0; i < cpu->num_watchpoints; i++) {
124 if (env->cpu_watchpoint[i] &&
125 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
126 return true;
127 }
128 }
129 return false;
130 }
131
132 void lm32_debug_excp_handler(CPUState *cs)
133 {
134 LM32CPU *cpu = LM32_CPU(cs);
135 CPULM32State *env = &cpu->env;
136 CPUBreakpoint *bp;
137
138 if (cs->watchpoint_hit) {
139 if (cs->watchpoint_hit->flags & BP_CPU) {
140 cs->watchpoint_hit = NULL;
141 if (check_watchpoints(env)) {
142 raise_exception(env, EXCP_WATCHPOINT);
143 } else {
144 cpu_resume_from_signal(cs, NULL);
145 }
146 }
147 } else {
148 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
149 if (bp->pc == env->pc) {
150 if (bp->flags & BP_CPU) {
151 raise_exception(env, EXCP_BREAKPOINT);
152 }
153 break;
154 }
155 }
156 }
157 }
158
159 void lm32_cpu_do_interrupt(CPUState *cs)
160 {
161 LM32CPU *cpu = LM32_CPU(cs);
162 CPULM32State *env = &cpu->env;
163
164 qemu_log_mask(CPU_LOG_INT,
165 "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
166
167 switch (cs->exception_index) {
168 case EXCP_SYSTEMCALL:
169 if (unlikely(semihosting_enabled())) {
170 /* do_semicall() returns true if call was handled. Otherwise
171 * do the normal exception handling. */
172 if (lm32_cpu_do_semihosting(cs)) {
173 env->pc += 4;
174 break;
175 }
176 }
177 /* fall through */
178 case EXCP_INSN_BUS_ERROR:
179 case EXCP_DATA_BUS_ERROR:
180 case EXCP_DIVIDE_BY_ZERO:
181 case EXCP_IRQ:
182 /* non-debug exceptions */
183 env->regs[R_EA] = env->pc;
184 env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
185 env->ie &= ~IE_IE;
186 if (env->dc & DC_RE) {
187 env->pc = env->deba + (cs->exception_index * 32);
188 } else {
189 env->pc = env->eba + (cs->exception_index * 32);
190 }
191 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
192 break;
193 case EXCP_BREAKPOINT:
194 case EXCP_WATCHPOINT:
195 /* debug exceptions */
196 env->regs[R_BA] = env->pc;
197 env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
198 env->ie &= ~IE_IE;
199 env->pc = env->deba + (cs->exception_index * 32);
200 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
201 break;
202 default:
203 cpu_abort(cs, "unhandled exception type=%d\n",
204 cs->exception_index);
205 break;
206 }
207 }
208
209 bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
210 {
211 LM32CPU *cpu = LM32_CPU(cs);
212 CPULM32State *env = &cpu->env;
213
214 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) {
215 cs->exception_index = EXCP_IRQ;
216 lm32_cpu_do_interrupt(cs);
217 return true;
218 }
219 return false;
220 }
221
222 LM32CPU *cpu_lm32_init(const char *cpu_model)
223 {
224 return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
225 }
226
227 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
228 * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
229 * 0x80000000-0xffffffff is not cached and used to access IO devices. */
230 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
231 {
232 if (value) {
233 env->flags |= LM32_FLAG_IGNORE_MSB;
234 } else {
235 env->flags &= ~LM32_FLAG_IGNORE_MSB;
236 }
237 }