KVM: Update headers (except HIOR mess)
[qemu.git] / target-m68k / cpu.h
1 /*
2 * m68k virtual CPU header
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #ifndef CPU_M68K_H
21 #define CPU_M68K_H
22
23 #define TARGET_LONG_BITS 32
24
25 #define CPUState struct CPUM68KState
26
27 #include "qemu-common.h"
28 #include "cpu-defs.h"
29
30 #include "softfloat.h"
31
32 #define MAX_QREGS 32
33
34 #define TARGET_HAS_ICE 1
35
36 #define ELF_MACHINE EM_68K
37
38 #define EXCP_ACCESS 2 /* Access (MMU) error. */
39 #define EXCP_ADDRESS 3 /* Address error. */
40 #define EXCP_ILLEGAL 4 /* Illegal instruction. */
41 #define EXCP_DIV0 5 /* Divide by zero */
42 #define EXCP_PRIVILEGE 8 /* Privilege violation. */
43 #define EXCP_TRACE 9
44 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
45 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
46 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
47 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
48 #define EXCP_FORMAT 14 /* RTE format error. */
49 #define EXCP_UNINITIALIZED 15
50 #define EXCP_TRAP0 32 /* User trap #0. */
51 #define EXCP_TRAP15 47 /* User trap #15. */
52 #define EXCP_UNSUPPORTED 61
53 #define EXCP_ICE 13
54
55 #define EXCP_RTE 0x100
56 #define EXCP_HALT_INSN 0x101
57
58 #define NB_MMU_MODES 2
59
60 typedef struct CPUM68KState {
61 uint32_t dregs[8];
62 uint32_t aregs[8];
63 uint32_t pc;
64 uint32_t sr;
65
66 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
67 int current_sp;
68 uint32_t sp[2];
69
70 /* Condition flags. */
71 uint32_t cc_op;
72 uint32_t cc_dest;
73 uint32_t cc_src;
74 uint32_t cc_x;
75
76 float64 fregs[8];
77 float64 fp_result;
78 uint32_t fpcr;
79 uint32_t fpsr;
80 float_status fp_status;
81
82 uint64_t mactmp;
83 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
84 two 8-bit parts. We store a single 64-bit value and
85 rearrange/extend this when changing modes. */
86 uint64_t macc[4];
87 uint32_t macsr;
88 uint32_t mac_mask;
89
90 /* Temporary storage for DIV helpers. */
91 uint32_t div1;
92 uint32_t div2;
93
94 /* MMU status. */
95 struct {
96 uint32_t ar;
97 } mmu;
98
99 /* Control registers. */
100 uint32_t vbr;
101 uint32_t mbar;
102 uint32_t rambar0;
103 uint32_t cacr;
104
105 /* ??? remove this. */
106 uint32_t t1;
107
108 int pending_vector;
109 int pending_level;
110
111 uint32_t qregs[MAX_QREGS];
112
113 CPU_COMMON
114
115 uint32_t features;
116 } CPUM68KState;
117
118 void m68k_tcg_init(void);
119 CPUM68KState *cpu_m68k_init(const char *cpu_model);
120 int cpu_m68k_exec(CPUM68KState *s);
121 void cpu_m68k_close(CPUM68KState *s);
122 void do_interrupt(CPUState *env1);
123 void do_interrupt_m68k_hardirq(CPUState *env1);
124 /* you can call this signal handler from your SIGBUS and SIGSEGV
125 signal handlers to inform the virtual CPU of exceptions. non zero
126 is returned if the signal was handled by the virtual CPU. */
127 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
128 void *puc);
129 void cpu_m68k_flush_flags(CPUM68KState *, int);
130
131 enum {
132 CC_OP_DYNAMIC, /* Use env->cc_op */
133 CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
134 CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
135 CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
136 CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
137 CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
138 CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
139 CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
140 CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
141 CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
142 };
143
144 #define CCF_C 0x01
145 #define CCF_V 0x02
146 #define CCF_Z 0x04
147 #define CCF_N 0x08
148 #define CCF_X 0x10
149
150 #define SR_I_SHIFT 8
151 #define SR_I 0x0700
152 #define SR_M 0x1000
153 #define SR_S 0x2000
154 #define SR_T 0x8000
155
156 #define M68K_SSP 0
157 #define M68K_USP 1
158
159 /* CACR fields are implementation defined, but some bits are common. */
160 #define M68K_CACR_EUSP 0x10
161
162 #define MACSR_PAV0 0x100
163 #define MACSR_OMC 0x080
164 #define MACSR_SU 0x040
165 #define MACSR_FI 0x020
166 #define MACSR_RT 0x010
167 #define MACSR_N 0x008
168 #define MACSR_Z 0x004
169 #define MACSR_V 0x002
170 #define MACSR_EV 0x001
171
172 void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector);
173 void m68k_set_macsr(CPUM68KState *env, uint32_t val);
174 void m68k_switch_sp(CPUM68KState *env);
175
176 #define M68K_FPCR_PREC (1 << 6)
177
178 void do_m68k_semihosting(CPUM68KState *env, int nr);
179
180 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
181 Each feature covers the subset of instructions common to the
182 ISA revisions mentioned. */
183
184 enum m68k_features {
185 M68K_FEATURE_CF_ISA_A,
186 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
187 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
188 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
189 M68K_FEATURE_CF_FPU,
190 M68K_FEATURE_CF_MAC,
191 M68K_FEATURE_CF_EMAC,
192 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
193 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
194 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
195 M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
196 };
197
198 static inline int m68k_feature(CPUM68KState *env, int feature)
199 {
200 return (env->features & (1u << feature)) != 0;
201 }
202
203 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
204
205 void register_m68k_insns (CPUM68KState *env);
206
207 #ifdef CONFIG_USER_ONLY
208 /* Linux uses 8k pages. */
209 #define TARGET_PAGE_BITS 13
210 #else
211 /* Smallest TLB entry size is 1k. */
212 #define TARGET_PAGE_BITS 10
213 #endif
214
215 #define TARGET_PHYS_ADDR_SPACE_BITS 32
216 #define TARGET_VIRT_ADDR_SPACE_BITS 32
217
218 #define cpu_init cpu_m68k_init
219 #define cpu_exec cpu_m68k_exec
220 #define cpu_gen_code cpu_m68k_gen_code
221 #define cpu_signal_handler cpu_m68k_signal_handler
222 #define cpu_list m68k_cpu_list
223
224 /* MMU modes definitions */
225 #define MMU_MODE0_SUFFIX _kernel
226 #define MMU_MODE1_SUFFIX _user
227 #define MMU_USER_IDX 1
228 static inline int cpu_mmu_index (CPUState *env)
229 {
230 return (env->sr & SR_S) == 0 ? 1 : 0;
231 }
232
233 int cpu_m68k_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
234 int mmu_idx);
235 #define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
236
237 #if defined(CONFIG_USER_ONLY)
238 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
239 {
240 if (newsp)
241 env->aregs[7] = newsp;
242 env->dregs[0] = 0;
243 }
244 #endif
245
246 #include "cpu-all.h"
247
248 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
249 target_ulong *cs_base, int *flags)
250 {
251 *pc = env->pc;
252 *cs_base = 0;
253 *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
254 | (env->sr & SR_S) /* Bit 13 */
255 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
256 }
257
258 static inline bool cpu_has_work(CPUState *env)
259 {
260 return env->interrupt_request & CPU_INTERRUPT_HARD;
261 }
262
263 #include "exec-all.h"
264
265 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
266 {
267 env->pc = tb->pc;
268 }
269
270 #endif