target-m68k: Remove custom qemu_assert() function
[qemu.git] / target-m68k / translate.c
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/log.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 //#define DEBUG_DISPATCH 1
31
32 /* Fake floating point. */
33 #define tcg_gen_mov_f64 tcg_gen_mov_i64
34 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
35 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
36
37 #define DEFO32(name, offset) static TCGv QREG_##name;
38 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
39 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
40 #include "qregs.def"
41 #undef DEFO32
42 #undef DEFO64
43 #undef DEFF64
44
45 static TCGv_i32 cpu_halted;
46
47 static TCGv_ptr cpu_env;
48
49 static char cpu_reg_names[3*8*3 + 5*4];
50 static TCGv cpu_dregs[8];
51 static TCGv cpu_aregs[8];
52 static TCGv_i64 cpu_fregs[8];
53 static TCGv_i64 cpu_macc[4];
54
55 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
56 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
57 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
58 #define MACREG(acc) cpu_macc[acc]
59 #define QREG_SP cpu_aregs[7]
60
61 static TCGv NULL_QREG;
62 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
63 /* Used to distinguish stores from bad addressing modes. */
64 static TCGv store_dummy;
65
66 #include "exec/gen-icount.h"
67
68 void m68k_tcg_init(void)
69 {
70 char *p;
71 int i;
72
73 #define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
74 #define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
75 #define DEFF64(name, offset) DEFO64(name, offset)
76 #include "qregs.def"
77 #undef DEFO32
78 #undef DEFO64
79 #undef DEFF64
80
81 cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
82 -offsetof(M68kCPU, env) +
83 offsetof(CPUState, halted), "HALTED");
84
85 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
86
87 p = cpu_reg_names;
88 for (i = 0; i < 8; i++) {
89 sprintf(p, "D%d", i);
90 cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0,
91 offsetof(CPUM68KState, dregs[i]), p);
92 p += 3;
93 sprintf(p, "A%d", i);
94 cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0,
95 offsetof(CPUM68KState, aregs[i]), p);
96 p += 3;
97 sprintf(p, "F%d", i);
98 cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0,
99 offsetof(CPUM68KState, fregs[i]), p);
100 p += 3;
101 }
102 for (i = 0; i < 4; i++) {
103 sprintf(p, "ACC%d", i);
104 cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0,
105 offsetof(CPUM68KState, macc[i]), p);
106 p += 5;
107 }
108
109 NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");
110 store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");
111 }
112
113 /* internal defines */
114 typedef struct DisasContext {
115 CPUM68KState *env;
116 target_ulong insn_pc; /* Start of the current instruction. */
117 target_ulong pc;
118 int is_jmp;
119 int cc_op;
120 int user;
121 uint32_t fpcr;
122 struct TranslationBlock *tb;
123 int singlestep_enabled;
124 int is_mem;
125 TCGv_i64 mactmp;
126 int done_mac;
127 } DisasContext;
128
129 #define DISAS_JUMP_NEXT 4
130
131 #if defined(CONFIG_USER_ONLY)
132 #define IS_USER(s) 1
133 #else
134 #define IS_USER(s) s->user
135 #endif
136
137 /* XXX: move that elsewhere */
138 /* ??? Fix exceptions. */
139 static void *gen_throws_exception;
140 #define gen_last_qop NULL
141
142 #define OS_BYTE 0
143 #define OS_WORD 1
144 #define OS_LONG 2
145 #define OS_SINGLE 4
146 #define OS_DOUBLE 5
147
148 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
149
150 #ifdef DEBUG_DISPATCH
151 #define DISAS_INSN(name) \
152 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
153 uint16_t insn); \
154 static void disas_##name(CPUM68KState *env, DisasContext *s, \
155 uint16_t insn) \
156 { \
157 qemu_log("Dispatch " #name "\n"); \
158 real_disas_##name(s, env, insn); \
159 } \
160 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
161 uint16_t insn)
162 #else
163 #define DISAS_INSN(name) \
164 static void disas_##name(CPUM68KState *env, DisasContext *s, \
165 uint16_t insn)
166 #endif
167
168 /* Generate a load from the specified address. Narrow values are
169 sign extended to full register width. */
170 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
171 {
172 TCGv tmp;
173 int index = IS_USER(s);
174 s->is_mem = 1;
175 tmp = tcg_temp_new_i32();
176 switch(opsize) {
177 case OS_BYTE:
178 if (sign)
179 tcg_gen_qemu_ld8s(tmp, addr, index);
180 else
181 tcg_gen_qemu_ld8u(tmp, addr, index);
182 break;
183 case OS_WORD:
184 if (sign)
185 tcg_gen_qemu_ld16s(tmp, addr, index);
186 else
187 tcg_gen_qemu_ld16u(tmp, addr, index);
188 break;
189 case OS_LONG:
190 case OS_SINGLE:
191 tcg_gen_qemu_ld32u(tmp, addr, index);
192 break;
193 default:
194 g_assert_not_reached();
195 }
196 gen_throws_exception = gen_last_qop;
197 return tmp;
198 }
199
200 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
201 {
202 TCGv_i64 tmp;
203 int index = IS_USER(s);
204 s->is_mem = 1;
205 tmp = tcg_temp_new_i64();
206 tcg_gen_qemu_ldf64(tmp, addr, index);
207 gen_throws_exception = gen_last_qop;
208 return tmp;
209 }
210
211 /* Generate a store. */
212 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
213 {
214 int index = IS_USER(s);
215 s->is_mem = 1;
216 switch(opsize) {
217 case OS_BYTE:
218 tcg_gen_qemu_st8(val, addr, index);
219 break;
220 case OS_WORD:
221 tcg_gen_qemu_st16(val, addr, index);
222 break;
223 case OS_LONG:
224 case OS_SINGLE:
225 tcg_gen_qemu_st32(val, addr, index);
226 break;
227 default:
228 g_assert_not_reached();
229 }
230 gen_throws_exception = gen_last_qop;
231 }
232
233 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
234 {
235 int index = IS_USER(s);
236 s->is_mem = 1;
237 tcg_gen_qemu_stf64(val, addr, index);
238 gen_throws_exception = gen_last_qop;
239 }
240
241 typedef enum {
242 EA_STORE,
243 EA_LOADU,
244 EA_LOADS
245 } ea_what;
246
247 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
248 otherwise generate a store. */
249 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
250 ea_what what)
251 {
252 if (what == EA_STORE) {
253 gen_store(s, opsize, addr, val);
254 return store_dummy;
255 } else {
256 return gen_load(s, opsize, addr, what == EA_LOADS);
257 }
258 }
259
260 /* Read a 32-bit immediate constant. */
261 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
262 {
263 uint32_t im;
264 im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
265 s->pc += 2;
266 im |= cpu_lduw_code(env, s->pc);
267 s->pc += 2;
268 return im;
269 }
270
271 /* Calculate and address index. */
272 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
273 {
274 TCGv add;
275 int scale;
276
277 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
278 if ((ext & 0x800) == 0) {
279 tcg_gen_ext16s_i32(tmp, add);
280 add = tmp;
281 }
282 scale = (ext >> 9) & 3;
283 if (scale != 0) {
284 tcg_gen_shli_i32(tmp, add, scale);
285 add = tmp;
286 }
287 return add;
288 }
289
290 /* Handle a base + index + displacement effective addresss.
291 A NULL_QREG base means pc-relative. */
292 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize,
293 TCGv base)
294 {
295 uint32_t offset;
296 uint16_t ext;
297 TCGv add;
298 TCGv tmp;
299 uint32_t bd, od;
300
301 offset = s->pc;
302 ext = cpu_lduw_code(env, s->pc);
303 s->pc += 2;
304
305 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
306 return NULL_QREG;
307
308 if (ext & 0x100) {
309 /* full extension word format */
310 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
311 return NULL_QREG;
312
313 if ((ext & 0x30) > 0x10) {
314 /* base displacement */
315 if ((ext & 0x30) == 0x20) {
316 bd = (int16_t)cpu_lduw_code(env, s->pc);
317 s->pc += 2;
318 } else {
319 bd = read_im32(env, s);
320 }
321 } else {
322 bd = 0;
323 }
324 tmp = tcg_temp_new();
325 if ((ext & 0x44) == 0) {
326 /* pre-index */
327 add = gen_addr_index(ext, tmp);
328 } else {
329 add = NULL_QREG;
330 }
331 if ((ext & 0x80) == 0) {
332 /* base not suppressed */
333 if (IS_NULL_QREG(base)) {
334 base = tcg_const_i32(offset + bd);
335 bd = 0;
336 }
337 if (!IS_NULL_QREG(add)) {
338 tcg_gen_add_i32(tmp, add, base);
339 add = tmp;
340 } else {
341 add = base;
342 }
343 }
344 if (!IS_NULL_QREG(add)) {
345 if (bd != 0) {
346 tcg_gen_addi_i32(tmp, add, bd);
347 add = tmp;
348 }
349 } else {
350 add = tcg_const_i32(bd);
351 }
352 if ((ext & 3) != 0) {
353 /* memory indirect */
354 base = gen_load(s, OS_LONG, add, 0);
355 if ((ext & 0x44) == 4) {
356 add = gen_addr_index(ext, tmp);
357 tcg_gen_add_i32(tmp, add, base);
358 add = tmp;
359 } else {
360 add = base;
361 }
362 if ((ext & 3) > 1) {
363 /* outer displacement */
364 if ((ext & 3) == 2) {
365 od = (int16_t)cpu_lduw_code(env, s->pc);
366 s->pc += 2;
367 } else {
368 od = read_im32(env, s);
369 }
370 } else {
371 od = 0;
372 }
373 if (od != 0) {
374 tcg_gen_addi_i32(tmp, add, od);
375 add = tmp;
376 }
377 }
378 } else {
379 /* brief extension word format */
380 tmp = tcg_temp_new();
381 add = gen_addr_index(ext, tmp);
382 if (!IS_NULL_QREG(base)) {
383 tcg_gen_add_i32(tmp, add, base);
384 if ((int8_t)ext)
385 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
386 } else {
387 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
388 }
389 add = tmp;
390 }
391 return add;
392 }
393
394 /* Update the CPU env CC_OP state. */
395 static inline void gen_flush_cc_op(DisasContext *s)
396 {
397 if (s->cc_op != CC_OP_DYNAMIC)
398 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
399 }
400
401 /* Evaluate all the CC flags. */
402 static inline void gen_flush_flags(DisasContext *s)
403 {
404 if (s->cc_op == CC_OP_FLAGS)
405 return;
406 gen_flush_cc_op(s);
407 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
408 s->cc_op = CC_OP_FLAGS;
409 }
410
411 static void gen_logic_cc(DisasContext *s, TCGv val)
412 {
413 tcg_gen_mov_i32(QREG_CC_DEST, val);
414 s->cc_op = CC_OP_LOGIC;
415 }
416
417 static void gen_update_cc_add(TCGv dest, TCGv src)
418 {
419 tcg_gen_mov_i32(QREG_CC_DEST, dest);
420 tcg_gen_mov_i32(QREG_CC_SRC, src);
421 }
422
423 static inline int opsize_bytes(int opsize)
424 {
425 switch (opsize) {
426 case OS_BYTE: return 1;
427 case OS_WORD: return 2;
428 case OS_LONG: return 4;
429 case OS_SINGLE: return 4;
430 case OS_DOUBLE: return 8;
431 default:
432 g_assert_not_reached();
433 }
434 }
435
436 /* Assign value to a register. If the width is less than the register width
437 only the low part of the register is set. */
438 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
439 {
440 TCGv tmp;
441 switch (opsize) {
442 case OS_BYTE:
443 tcg_gen_andi_i32(reg, reg, 0xffffff00);
444 tmp = tcg_temp_new();
445 tcg_gen_ext8u_i32(tmp, val);
446 tcg_gen_or_i32(reg, reg, tmp);
447 break;
448 case OS_WORD:
449 tcg_gen_andi_i32(reg, reg, 0xffff0000);
450 tmp = tcg_temp_new();
451 tcg_gen_ext16u_i32(tmp, val);
452 tcg_gen_or_i32(reg, reg, tmp);
453 break;
454 case OS_LONG:
455 case OS_SINGLE:
456 tcg_gen_mov_i32(reg, val);
457 break;
458 default:
459 g_assert_not_reached();
460 }
461 }
462
463 /* Sign or zero extend a value. */
464 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
465 {
466 TCGv tmp;
467
468 switch (opsize) {
469 case OS_BYTE:
470 tmp = tcg_temp_new();
471 if (sign)
472 tcg_gen_ext8s_i32(tmp, val);
473 else
474 tcg_gen_ext8u_i32(tmp, val);
475 break;
476 case OS_WORD:
477 tmp = tcg_temp_new();
478 if (sign)
479 tcg_gen_ext16s_i32(tmp, val);
480 else
481 tcg_gen_ext16u_i32(tmp, val);
482 break;
483 case OS_LONG:
484 case OS_SINGLE:
485 tmp = val;
486 break;
487 default:
488 g_assert_not_reached();
489 }
490 return tmp;
491 }
492
493 /* Generate code for an "effective address". Does not adjust the base
494 register for autoincrement addressing modes. */
495 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
496 int opsize)
497 {
498 TCGv reg;
499 TCGv tmp;
500 uint16_t ext;
501 uint32_t offset;
502
503 switch ((insn >> 3) & 7) {
504 case 0: /* Data register direct. */
505 case 1: /* Address register direct. */
506 return NULL_QREG;
507 case 2: /* Indirect register */
508 case 3: /* Indirect postincrement. */
509 return AREG(insn, 0);
510 case 4: /* Indirect predecrememnt. */
511 reg = AREG(insn, 0);
512 tmp = tcg_temp_new();
513 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
514 return tmp;
515 case 5: /* Indirect displacement. */
516 reg = AREG(insn, 0);
517 tmp = tcg_temp_new();
518 ext = cpu_lduw_code(env, s->pc);
519 s->pc += 2;
520 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
521 return tmp;
522 case 6: /* Indirect index + displacement. */
523 reg = AREG(insn, 0);
524 return gen_lea_indexed(env, s, opsize, reg);
525 case 7: /* Other */
526 switch (insn & 7) {
527 case 0: /* Absolute short. */
528 offset = cpu_ldsw_code(env, s->pc);
529 s->pc += 2;
530 return tcg_const_i32(offset);
531 case 1: /* Absolute long. */
532 offset = read_im32(env, s);
533 return tcg_const_i32(offset);
534 case 2: /* pc displacement */
535 offset = s->pc;
536 offset += cpu_ldsw_code(env, s->pc);
537 s->pc += 2;
538 return tcg_const_i32(offset);
539 case 3: /* pc index+displacement. */
540 return gen_lea_indexed(env, s, opsize, NULL_QREG);
541 case 4: /* Immediate. */
542 default:
543 return NULL_QREG;
544 }
545 }
546 /* Should never happen. */
547 return NULL_QREG;
548 }
549
550 /* Helper function for gen_ea. Reuse the computed address between the
551 for read/write operands. */
552 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
553 uint16_t insn, int opsize, TCGv val,
554 TCGv *addrp, ea_what what)
555 {
556 TCGv tmp;
557
558 if (addrp && what == EA_STORE) {
559 tmp = *addrp;
560 } else {
561 tmp = gen_lea(env, s, insn, opsize);
562 if (IS_NULL_QREG(tmp))
563 return tmp;
564 if (addrp)
565 *addrp = tmp;
566 }
567 return gen_ldst(s, opsize, tmp, val, what);
568 }
569
570 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
571 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
572 ADDRP is non-null for readwrite operands. */
573 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
574 int opsize, TCGv val, TCGv *addrp, ea_what what)
575 {
576 TCGv reg;
577 TCGv result;
578 uint32_t offset;
579
580 switch ((insn >> 3) & 7) {
581 case 0: /* Data register direct. */
582 reg = DREG(insn, 0);
583 if (what == EA_STORE) {
584 gen_partset_reg(opsize, reg, val);
585 return store_dummy;
586 } else {
587 return gen_extend(reg, opsize, what == EA_LOADS);
588 }
589 case 1: /* Address register direct. */
590 reg = AREG(insn, 0);
591 if (what == EA_STORE) {
592 tcg_gen_mov_i32(reg, val);
593 return store_dummy;
594 } else {
595 return gen_extend(reg, opsize, what == EA_LOADS);
596 }
597 case 2: /* Indirect register */
598 reg = AREG(insn, 0);
599 return gen_ldst(s, opsize, reg, val, what);
600 case 3: /* Indirect postincrement. */
601 reg = AREG(insn, 0);
602 result = gen_ldst(s, opsize, reg, val, what);
603 /* ??? This is not exception safe. The instruction may still
604 fault after this point. */
605 if (what == EA_STORE || !addrp)
606 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
607 return result;
608 case 4: /* Indirect predecrememnt. */
609 {
610 TCGv tmp;
611 if (addrp && what == EA_STORE) {
612 tmp = *addrp;
613 } else {
614 tmp = gen_lea(env, s, insn, opsize);
615 if (IS_NULL_QREG(tmp))
616 return tmp;
617 if (addrp)
618 *addrp = tmp;
619 }
620 result = gen_ldst(s, opsize, tmp, val, what);
621 /* ??? This is not exception safe. The instruction may still
622 fault after this point. */
623 if (what == EA_STORE || !addrp) {
624 reg = AREG(insn, 0);
625 tcg_gen_mov_i32(reg, tmp);
626 }
627 }
628 return result;
629 case 5: /* Indirect displacement. */
630 case 6: /* Indirect index + displacement. */
631 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
632 case 7: /* Other */
633 switch (insn & 7) {
634 case 0: /* Absolute short. */
635 case 1: /* Absolute long. */
636 case 2: /* pc displacement */
637 case 3: /* pc index+displacement. */
638 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
639 case 4: /* Immediate. */
640 /* Sign extend values for consistency. */
641 switch (opsize) {
642 case OS_BYTE:
643 if (what == EA_LOADS) {
644 offset = cpu_ldsb_code(env, s->pc + 1);
645 } else {
646 offset = cpu_ldub_code(env, s->pc + 1);
647 }
648 s->pc += 2;
649 break;
650 case OS_WORD:
651 if (what == EA_LOADS) {
652 offset = cpu_ldsw_code(env, s->pc);
653 } else {
654 offset = cpu_lduw_code(env, s->pc);
655 }
656 s->pc += 2;
657 break;
658 case OS_LONG:
659 offset = read_im32(env, s);
660 break;
661 default:
662 g_assert_not_reached();
663 }
664 return tcg_const_i32(offset);
665 default:
666 return NULL_QREG;
667 }
668 }
669 /* Should never happen. */
670 return NULL_QREG;
671 }
672
673 /* This generates a conditional branch, clobbering all temporaries. */
674 static void gen_jmpcc(DisasContext *s, int cond, int l1)
675 {
676 TCGv tmp;
677
678 /* TODO: Optimize compare/branch pairs rather than always flushing
679 flag state to CC_OP_FLAGS. */
680 gen_flush_flags(s);
681 switch (cond) {
682 case 0: /* T */
683 tcg_gen_br(l1);
684 break;
685 case 1: /* F */
686 break;
687 case 2: /* HI (!C && !Z) */
688 tmp = tcg_temp_new();
689 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
690 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
691 break;
692 case 3: /* LS (C || Z) */
693 tmp = tcg_temp_new();
694 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
695 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
696 break;
697 case 4: /* CC (!C) */
698 tmp = tcg_temp_new();
699 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
700 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
701 break;
702 case 5: /* CS (C) */
703 tmp = tcg_temp_new();
704 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
705 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
706 break;
707 case 6: /* NE (!Z) */
708 tmp = tcg_temp_new();
709 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
710 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
711 break;
712 case 7: /* EQ (Z) */
713 tmp = tcg_temp_new();
714 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
715 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
716 break;
717 case 8: /* VC (!V) */
718 tmp = tcg_temp_new();
719 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
720 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
721 break;
722 case 9: /* VS (V) */
723 tmp = tcg_temp_new();
724 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
725 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
726 break;
727 case 10: /* PL (!N) */
728 tmp = tcg_temp_new();
729 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
731 break;
732 case 11: /* MI (N) */
733 tmp = tcg_temp_new();
734 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
735 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
736 break;
737 case 12: /* GE (!(N ^ V)) */
738 tmp = tcg_temp_new();
739 assert(CCF_V == (CCF_N >> 2));
740 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
741 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
742 tcg_gen_andi_i32(tmp, tmp, CCF_V);
743 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
744 break;
745 case 13: /* LT (N ^ V) */
746 tmp = tcg_temp_new();
747 assert(CCF_V == (CCF_N >> 2));
748 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
749 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
750 tcg_gen_andi_i32(tmp, tmp, CCF_V);
751 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
752 break;
753 case 14: /* GT (!(Z || (N ^ V))) */
754 tmp = tcg_temp_new();
755 assert(CCF_V == (CCF_N >> 2));
756 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
757 tcg_gen_shri_i32(tmp, tmp, 2);
758 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
759 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
760 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
761 break;
762 case 15: /* LE (Z || (N ^ V)) */
763 tmp = tcg_temp_new();
764 assert(CCF_V == (CCF_N >> 2));
765 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
766 tcg_gen_shri_i32(tmp, tmp, 2);
767 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
768 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
769 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
770 break;
771 default:
772 /* Should ever happen. */
773 abort();
774 }
775 }
776
777 DISAS_INSN(scc)
778 {
779 int l1;
780 int cond;
781 TCGv reg;
782
783 l1 = gen_new_label();
784 cond = (insn >> 8) & 0xf;
785 reg = DREG(insn, 0);
786 tcg_gen_andi_i32(reg, reg, 0xffffff00);
787 /* This is safe because we modify the reg directly, with no other values
788 live. */
789 gen_jmpcc(s, cond ^ 1, l1);
790 tcg_gen_ori_i32(reg, reg, 0xff);
791 gen_set_label(l1);
792 }
793
794 /* Force a TB lookup after an instruction that changes the CPU state. */
795 static void gen_lookup_tb(DisasContext *s)
796 {
797 gen_flush_cc_op(s);
798 tcg_gen_movi_i32(QREG_PC, s->pc);
799 s->is_jmp = DISAS_UPDATE;
800 }
801
802 /* Generate a jump to an immediate address. */
803 static void gen_jmp_im(DisasContext *s, uint32_t dest)
804 {
805 gen_flush_cc_op(s);
806 tcg_gen_movi_i32(QREG_PC, dest);
807 s->is_jmp = DISAS_JUMP;
808 }
809
810 /* Generate a jump to the address in qreg DEST. */
811 static void gen_jmp(DisasContext *s, TCGv dest)
812 {
813 gen_flush_cc_op(s);
814 tcg_gen_mov_i32(QREG_PC, dest);
815 s->is_jmp = DISAS_JUMP;
816 }
817
818 static void gen_exception(DisasContext *s, uint32_t where, int nr)
819 {
820 gen_flush_cc_op(s);
821 gen_jmp_im(s, where);
822 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
823 }
824
825 static inline void gen_addr_fault(DisasContext *s)
826 {
827 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
828 }
829
830 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
831 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
832 op_sign ? EA_LOADS : EA_LOADU); \
833 if (IS_NULL_QREG(result)) { \
834 gen_addr_fault(s); \
835 return; \
836 } \
837 } while (0)
838
839 #define DEST_EA(env, insn, opsize, val, addrp) do { \
840 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
841 if (IS_NULL_QREG(ea_result)) { \
842 gen_addr_fault(s); \
843 return; \
844 } \
845 } while (0)
846
847 /* Generate a jump to an immediate address. */
848 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
849 {
850 TranslationBlock *tb;
851
852 tb = s->tb;
853 if (unlikely(s->singlestep_enabled)) {
854 gen_exception(s, dest, EXCP_DEBUG);
855 } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
856 (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
857 tcg_gen_goto_tb(n);
858 tcg_gen_movi_i32(QREG_PC, dest);
859 tcg_gen_exit_tb((uintptr_t)tb + n);
860 } else {
861 gen_jmp_im(s, dest);
862 tcg_gen_exit_tb(0);
863 }
864 s->is_jmp = DISAS_TB_JUMP;
865 }
866
867 DISAS_INSN(undef_mac)
868 {
869 gen_exception(s, s->pc - 2, EXCP_LINEA);
870 }
871
872 DISAS_INSN(undef_fpu)
873 {
874 gen_exception(s, s->pc - 2, EXCP_LINEF);
875 }
876
877 DISAS_INSN(undef)
878 {
879 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
880 cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
881 }
882
883 DISAS_INSN(mulw)
884 {
885 TCGv reg;
886 TCGv tmp;
887 TCGv src;
888 int sign;
889
890 sign = (insn & 0x100) != 0;
891 reg = DREG(insn, 9);
892 tmp = tcg_temp_new();
893 if (sign)
894 tcg_gen_ext16s_i32(tmp, reg);
895 else
896 tcg_gen_ext16u_i32(tmp, reg);
897 SRC_EA(env, src, OS_WORD, sign, NULL);
898 tcg_gen_mul_i32(tmp, tmp, src);
899 tcg_gen_mov_i32(reg, tmp);
900 /* Unlike m68k, coldfire always clears the overflow bit. */
901 gen_logic_cc(s, tmp);
902 }
903
904 DISAS_INSN(divw)
905 {
906 TCGv reg;
907 TCGv tmp;
908 TCGv src;
909 int sign;
910
911 sign = (insn & 0x100) != 0;
912 reg = DREG(insn, 9);
913 if (sign) {
914 tcg_gen_ext16s_i32(QREG_DIV1, reg);
915 } else {
916 tcg_gen_ext16u_i32(QREG_DIV1, reg);
917 }
918 SRC_EA(env, src, OS_WORD, sign, NULL);
919 tcg_gen_mov_i32(QREG_DIV2, src);
920 if (sign) {
921 gen_helper_divs(cpu_env, tcg_const_i32(1));
922 } else {
923 gen_helper_divu(cpu_env, tcg_const_i32(1));
924 }
925
926 tmp = tcg_temp_new();
927 src = tcg_temp_new();
928 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
929 tcg_gen_shli_i32(src, QREG_DIV2, 16);
930 tcg_gen_or_i32(reg, tmp, src);
931 s->cc_op = CC_OP_FLAGS;
932 }
933
934 DISAS_INSN(divl)
935 {
936 TCGv num;
937 TCGv den;
938 TCGv reg;
939 uint16_t ext;
940
941 ext = cpu_lduw_code(env, s->pc);
942 s->pc += 2;
943 if (ext & 0x87f8) {
944 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
945 return;
946 }
947 num = DREG(ext, 12);
948 reg = DREG(ext, 0);
949 tcg_gen_mov_i32(QREG_DIV1, num);
950 SRC_EA(env, den, OS_LONG, 0, NULL);
951 tcg_gen_mov_i32(QREG_DIV2, den);
952 if (ext & 0x0800) {
953 gen_helper_divs(cpu_env, tcg_const_i32(0));
954 } else {
955 gen_helper_divu(cpu_env, tcg_const_i32(0));
956 }
957 if ((ext & 7) == ((ext >> 12) & 7)) {
958 /* div */
959 tcg_gen_mov_i32 (reg, QREG_DIV1);
960 } else {
961 /* rem */
962 tcg_gen_mov_i32 (reg, QREG_DIV2);
963 }
964 s->cc_op = CC_OP_FLAGS;
965 }
966
967 DISAS_INSN(addsub)
968 {
969 TCGv reg;
970 TCGv dest;
971 TCGv src;
972 TCGv tmp;
973 TCGv addr;
974 int add;
975
976 add = (insn & 0x4000) != 0;
977 reg = DREG(insn, 9);
978 dest = tcg_temp_new();
979 if (insn & 0x100) {
980 SRC_EA(env, tmp, OS_LONG, 0, &addr);
981 src = reg;
982 } else {
983 tmp = reg;
984 SRC_EA(env, src, OS_LONG, 0, NULL);
985 }
986 if (add) {
987 tcg_gen_add_i32(dest, tmp, src);
988 gen_helper_xflag_lt(QREG_CC_X, dest, src);
989 s->cc_op = CC_OP_ADD;
990 } else {
991 gen_helper_xflag_lt(QREG_CC_X, tmp, src);
992 tcg_gen_sub_i32(dest, tmp, src);
993 s->cc_op = CC_OP_SUB;
994 }
995 gen_update_cc_add(dest, src);
996 if (insn & 0x100) {
997 DEST_EA(env, insn, OS_LONG, dest, &addr);
998 } else {
999 tcg_gen_mov_i32(reg, dest);
1000 }
1001 }
1002
1003
1004 /* Reverse the order of the bits in REG. */
1005 DISAS_INSN(bitrev)
1006 {
1007 TCGv reg;
1008 reg = DREG(insn, 0);
1009 gen_helper_bitrev(reg, reg);
1010 }
1011
1012 DISAS_INSN(bitop_reg)
1013 {
1014 int opsize;
1015 int op;
1016 TCGv src1;
1017 TCGv src2;
1018 TCGv tmp;
1019 TCGv addr;
1020 TCGv dest;
1021
1022 if ((insn & 0x38) != 0)
1023 opsize = OS_BYTE;
1024 else
1025 opsize = OS_LONG;
1026 op = (insn >> 6) & 3;
1027 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1028 src2 = DREG(insn, 9);
1029 dest = tcg_temp_new();
1030
1031 gen_flush_flags(s);
1032 tmp = tcg_temp_new();
1033 if (opsize == OS_BYTE)
1034 tcg_gen_andi_i32(tmp, src2, 7);
1035 else
1036 tcg_gen_andi_i32(tmp, src2, 31);
1037 src2 = tmp;
1038 tmp = tcg_temp_new();
1039 tcg_gen_shr_i32(tmp, src1, src2);
1040 tcg_gen_andi_i32(tmp, tmp, 1);
1041 tcg_gen_shli_i32(tmp, tmp, 2);
1042 /* Clear CCF_Z if bit set. */
1043 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1044 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1045
1046 tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);
1047 switch (op) {
1048 case 1: /* bchg */
1049 tcg_gen_xor_i32(dest, src1, tmp);
1050 break;
1051 case 2: /* bclr */
1052 tcg_gen_not_i32(tmp, tmp);
1053 tcg_gen_and_i32(dest, src1, tmp);
1054 break;
1055 case 3: /* bset */
1056 tcg_gen_or_i32(dest, src1, tmp);
1057 break;
1058 default: /* btst */
1059 break;
1060 }
1061 if (op)
1062 DEST_EA(env, insn, opsize, dest, &addr);
1063 }
1064
1065 DISAS_INSN(sats)
1066 {
1067 TCGv reg;
1068 reg = DREG(insn, 0);
1069 gen_flush_flags(s);
1070 gen_helper_sats(reg, reg, QREG_CC_DEST);
1071 gen_logic_cc(s, reg);
1072 }
1073
1074 static void gen_push(DisasContext *s, TCGv val)
1075 {
1076 TCGv tmp;
1077
1078 tmp = tcg_temp_new();
1079 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1080 gen_store(s, OS_LONG, tmp, val);
1081 tcg_gen_mov_i32(QREG_SP, tmp);
1082 }
1083
1084 DISAS_INSN(movem)
1085 {
1086 TCGv addr;
1087 int i;
1088 uint16_t mask;
1089 TCGv reg;
1090 TCGv tmp;
1091 int is_load;
1092
1093 mask = cpu_lduw_code(env, s->pc);
1094 s->pc += 2;
1095 tmp = gen_lea(env, s, insn, OS_LONG);
1096 if (IS_NULL_QREG(tmp)) {
1097 gen_addr_fault(s);
1098 return;
1099 }
1100 addr = tcg_temp_new();
1101 tcg_gen_mov_i32(addr, tmp);
1102 is_load = ((insn & 0x0400) != 0);
1103 for (i = 0; i < 16; i++, mask >>= 1) {
1104 if (mask & 1) {
1105 if (i < 8)
1106 reg = DREG(i, 0);
1107 else
1108 reg = AREG(i, 0);
1109 if (is_load) {
1110 tmp = gen_load(s, OS_LONG, addr, 0);
1111 tcg_gen_mov_i32(reg, tmp);
1112 } else {
1113 gen_store(s, OS_LONG, addr, reg);
1114 }
1115 if (mask != 1)
1116 tcg_gen_addi_i32(addr, addr, 4);
1117 }
1118 }
1119 }
1120
1121 DISAS_INSN(bitop_im)
1122 {
1123 int opsize;
1124 int op;
1125 TCGv src1;
1126 uint32_t mask;
1127 int bitnum;
1128 TCGv tmp;
1129 TCGv addr;
1130
1131 if ((insn & 0x38) != 0)
1132 opsize = OS_BYTE;
1133 else
1134 opsize = OS_LONG;
1135 op = (insn >> 6) & 3;
1136
1137 bitnum = cpu_lduw_code(env, s->pc);
1138 s->pc += 2;
1139 if (bitnum & 0xff00) {
1140 disas_undef(env, s, insn);
1141 return;
1142 }
1143
1144 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1145
1146 gen_flush_flags(s);
1147 if (opsize == OS_BYTE)
1148 bitnum &= 7;
1149 else
1150 bitnum &= 31;
1151 mask = 1 << bitnum;
1152
1153 tmp = tcg_temp_new();
1154 assert (CCF_Z == (1 << 2));
1155 if (bitnum > 2)
1156 tcg_gen_shri_i32(tmp, src1, bitnum - 2);
1157 else if (bitnum < 2)
1158 tcg_gen_shli_i32(tmp, src1, 2 - bitnum);
1159 else
1160 tcg_gen_mov_i32(tmp, src1);
1161 tcg_gen_andi_i32(tmp, tmp, CCF_Z);
1162 /* Clear CCF_Z if bit set. */
1163 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1164 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1165 if (op) {
1166 switch (op) {
1167 case 1: /* bchg */
1168 tcg_gen_xori_i32(tmp, src1, mask);
1169 break;
1170 case 2: /* bclr */
1171 tcg_gen_andi_i32(tmp, src1, ~mask);
1172 break;
1173 case 3: /* bset */
1174 tcg_gen_ori_i32(tmp, src1, mask);
1175 break;
1176 default: /* btst */
1177 break;
1178 }
1179 DEST_EA(env, insn, opsize, tmp, &addr);
1180 }
1181 }
1182
1183 DISAS_INSN(arith_im)
1184 {
1185 int op;
1186 uint32_t im;
1187 TCGv src1;
1188 TCGv dest;
1189 TCGv addr;
1190
1191 op = (insn >> 9) & 7;
1192 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1193 im = read_im32(env, s);
1194 dest = tcg_temp_new();
1195 switch (op) {
1196 case 0: /* ori */
1197 tcg_gen_ori_i32(dest, src1, im);
1198 gen_logic_cc(s, dest);
1199 break;
1200 case 1: /* andi */
1201 tcg_gen_andi_i32(dest, src1, im);
1202 gen_logic_cc(s, dest);
1203 break;
1204 case 2: /* subi */
1205 tcg_gen_mov_i32(dest, src1);
1206 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1207 tcg_gen_subi_i32(dest, dest, im);
1208 gen_update_cc_add(dest, tcg_const_i32(im));
1209 s->cc_op = CC_OP_SUB;
1210 break;
1211 case 3: /* addi */
1212 tcg_gen_mov_i32(dest, src1);
1213 tcg_gen_addi_i32(dest, dest, im);
1214 gen_update_cc_add(dest, tcg_const_i32(im));
1215 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1216 s->cc_op = CC_OP_ADD;
1217 break;
1218 case 5: /* eori */
1219 tcg_gen_xori_i32(dest, src1, im);
1220 gen_logic_cc(s, dest);
1221 break;
1222 case 6: /* cmpi */
1223 tcg_gen_mov_i32(dest, src1);
1224 tcg_gen_subi_i32(dest, dest, im);
1225 gen_update_cc_add(dest, tcg_const_i32(im));
1226 s->cc_op = CC_OP_SUB;
1227 break;
1228 default:
1229 abort();
1230 }
1231 if (op != 6) {
1232 DEST_EA(env, insn, OS_LONG, dest, &addr);
1233 }
1234 }
1235
1236 DISAS_INSN(byterev)
1237 {
1238 TCGv reg;
1239
1240 reg = DREG(insn, 0);
1241 tcg_gen_bswap32_i32(reg, reg);
1242 }
1243
1244 DISAS_INSN(move)
1245 {
1246 TCGv src;
1247 TCGv dest;
1248 int op;
1249 int opsize;
1250
1251 switch (insn >> 12) {
1252 case 1: /* move.b */
1253 opsize = OS_BYTE;
1254 break;
1255 case 2: /* move.l */
1256 opsize = OS_LONG;
1257 break;
1258 case 3: /* move.w */
1259 opsize = OS_WORD;
1260 break;
1261 default:
1262 abort();
1263 }
1264 SRC_EA(env, src, opsize, 1, NULL);
1265 op = (insn >> 6) & 7;
1266 if (op == 1) {
1267 /* movea */
1268 /* The value will already have been sign extended. */
1269 dest = AREG(insn, 9);
1270 tcg_gen_mov_i32(dest, src);
1271 } else {
1272 /* normal move */
1273 uint16_t dest_ea;
1274 dest_ea = ((insn >> 9) & 7) | (op << 3);
1275 DEST_EA(env, dest_ea, opsize, src, NULL);
1276 /* This will be correct because loads sign extend. */
1277 gen_logic_cc(s, src);
1278 }
1279 }
1280
1281 DISAS_INSN(negx)
1282 {
1283 TCGv reg;
1284
1285 gen_flush_flags(s);
1286 reg = DREG(insn, 0);
1287 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1288 }
1289
1290 DISAS_INSN(lea)
1291 {
1292 TCGv reg;
1293 TCGv tmp;
1294
1295 reg = AREG(insn, 9);
1296 tmp = gen_lea(env, s, insn, OS_LONG);
1297 if (IS_NULL_QREG(tmp)) {
1298 gen_addr_fault(s);
1299 return;
1300 }
1301 tcg_gen_mov_i32(reg, tmp);
1302 }
1303
1304 DISAS_INSN(clr)
1305 {
1306 int opsize;
1307
1308 switch ((insn >> 6) & 3) {
1309 case 0: /* clr.b */
1310 opsize = OS_BYTE;
1311 break;
1312 case 1: /* clr.w */
1313 opsize = OS_WORD;
1314 break;
1315 case 2: /* clr.l */
1316 opsize = OS_LONG;
1317 break;
1318 default:
1319 abort();
1320 }
1321 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1322 gen_logic_cc(s, tcg_const_i32(0));
1323 }
1324
1325 static TCGv gen_get_ccr(DisasContext *s)
1326 {
1327 TCGv dest;
1328
1329 gen_flush_flags(s);
1330 dest = tcg_temp_new();
1331 tcg_gen_shli_i32(dest, QREG_CC_X, 4);
1332 tcg_gen_or_i32(dest, dest, QREG_CC_DEST);
1333 return dest;
1334 }
1335
1336 DISAS_INSN(move_from_ccr)
1337 {
1338 TCGv reg;
1339 TCGv ccr;
1340
1341 ccr = gen_get_ccr(s);
1342 reg = DREG(insn, 0);
1343 gen_partset_reg(OS_WORD, reg, ccr);
1344 }
1345
1346 DISAS_INSN(neg)
1347 {
1348 TCGv reg;
1349 TCGv src1;
1350
1351 reg = DREG(insn, 0);
1352 src1 = tcg_temp_new();
1353 tcg_gen_mov_i32(src1, reg);
1354 tcg_gen_neg_i32(reg, src1);
1355 s->cc_op = CC_OP_SUB;
1356 gen_update_cc_add(reg, src1);
1357 gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
1358 s->cc_op = CC_OP_SUB;
1359 }
1360
1361 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1362 {
1363 tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf);
1364 tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4);
1365 if (!ccr_only) {
1366 gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
1367 }
1368 }
1369
1370 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1371 int ccr_only)
1372 {
1373 TCGv tmp;
1374 TCGv reg;
1375
1376 s->cc_op = CC_OP_FLAGS;
1377 if ((insn & 0x38) == 0)
1378 {
1379 tmp = tcg_temp_new();
1380 reg = DREG(insn, 0);
1381 tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
1382 tcg_gen_shri_i32(tmp, reg, 4);
1383 tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
1384 if (!ccr_only) {
1385 gen_helper_set_sr(cpu_env, reg);
1386 }
1387 }
1388 else if ((insn & 0x3f) == 0x3c)
1389 {
1390 uint16_t val;
1391 val = cpu_lduw_code(env, s->pc);
1392 s->pc += 2;
1393 gen_set_sr_im(s, val, ccr_only);
1394 }
1395 else
1396 disas_undef(env, s, insn);
1397 }
1398
1399 DISAS_INSN(move_to_ccr)
1400 {
1401 gen_set_sr(env, s, insn, 1);
1402 }
1403
1404 DISAS_INSN(not)
1405 {
1406 TCGv reg;
1407
1408 reg = DREG(insn, 0);
1409 tcg_gen_not_i32(reg, reg);
1410 gen_logic_cc(s, reg);
1411 }
1412
1413 DISAS_INSN(swap)
1414 {
1415 TCGv src1;
1416 TCGv src2;
1417 TCGv reg;
1418
1419 src1 = tcg_temp_new();
1420 src2 = tcg_temp_new();
1421 reg = DREG(insn, 0);
1422 tcg_gen_shli_i32(src1, reg, 16);
1423 tcg_gen_shri_i32(src2, reg, 16);
1424 tcg_gen_or_i32(reg, src1, src2);
1425 gen_logic_cc(s, reg);
1426 }
1427
1428 DISAS_INSN(pea)
1429 {
1430 TCGv tmp;
1431
1432 tmp = gen_lea(env, s, insn, OS_LONG);
1433 if (IS_NULL_QREG(tmp)) {
1434 gen_addr_fault(s);
1435 return;
1436 }
1437 gen_push(s, tmp);
1438 }
1439
1440 DISAS_INSN(ext)
1441 {
1442 int op;
1443 TCGv reg;
1444 TCGv tmp;
1445
1446 reg = DREG(insn, 0);
1447 op = (insn >> 6) & 7;
1448 tmp = tcg_temp_new();
1449 if (op == 3)
1450 tcg_gen_ext16s_i32(tmp, reg);
1451 else
1452 tcg_gen_ext8s_i32(tmp, reg);
1453 if (op == 2)
1454 gen_partset_reg(OS_WORD, reg, tmp);
1455 else
1456 tcg_gen_mov_i32(reg, tmp);
1457 gen_logic_cc(s, tmp);
1458 }
1459
1460 DISAS_INSN(tst)
1461 {
1462 int opsize;
1463 TCGv tmp;
1464
1465 switch ((insn >> 6) & 3) {
1466 case 0: /* tst.b */
1467 opsize = OS_BYTE;
1468 break;
1469 case 1: /* tst.w */
1470 opsize = OS_WORD;
1471 break;
1472 case 2: /* tst.l */
1473 opsize = OS_LONG;
1474 break;
1475 default:
1476 abort();
1477 }
1478 SRC_EA(env, tmp, opsize, 1, NULL);
1479 gen_logic_cc(s, tmp);
1480 }
1481
1482 DISAS_INSN(pulse)
1483 {
1484 /* Implemented as a NOP. */
1485 }
1486
1487 DISAS_INSN(illegal)
1488 {
1489 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1490 }
1491
1492 /* ??? This should be atomic. */
1493 DISAS_INSN(tas)
1494 {
1495 TCGv dest;
1496 TCGv src1;
1497 TCGv addr;
1498
1499 dest = tcg_temp_new();
1500 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1501 gen_logic_cc(s, src1);
1502 tcg_gen_ori_i32(dest, src1, 0x80);
1503 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1504 }
1505
1506 DISAS_INSN(mull)
1507 {
1508 uint16_t ext;
1509 TCGv reg;
1510 TCGv src1;
1511 TCGv dest;
1512
1513 /* The upper 32 bits of the product are discarded, so
1514 muls.l and mulu.l are functionally equivalent. */
1515 ext = cpu_lduw_code(env, s->pc);
1516 s->pc += 2;
1517 if (ext & 0x87ff) {
1518 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1519 return;
1520 }
1521 reg = DREG(ext, 12);
1522 SRC_EA(env, src1, OS_LONG, 0, NULL);
1523 dest = tcg_temp_new();
1524 tcg_gen_mul_i32(dest, src1, reg);
1525 tcg_gen_mov_i32(reg, dest);
1526 /* Unlike m68k, coldfire always clears the overflow bit. */
1527 gen_logic_cc(s, dest);
1528 }
1529
1530 DISAS_INSN(link)
1531 {
1532 int16_t offset;
1533 TCGv reg;
1534 TCGv tmp;
1535
1536 offset = cpu_ldsw_code(env, s->pc);
1537 s->pc += 2;
1538 reg = AREG(insn, 0);
1539 tmp = tcg_temp_new();
1540 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1541 gen_store(s, OS_LONG, tmp, reg);
1542 if ((insn & 7) != 7)
1543 tcg_gen_mov_i32(reg, tmp);
1544 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1545 }
1546
1547 DISAS_INSN(unlk)
1548 {
1549 TCGv src;
1550 TCGv reg;
1551 TCGv tmp;
1552
1553 src = tcg_temp_new();
1554 reg = AREG(insn, 0);
1555 tcg_gen_mov_i32(src, reg);
1556 tmp = gen_load(s, OS_LONG, src, 0);
1557 tcg_gen_mov_i32(reg, tmp);
1558 tcg_gen_addi_i32(QREG_SP, src, 4);
1559 }
1560
1561 DISAS_INSN(nop)
1562 {
1563 }
1564
1565 DISAS_INSN(rts)
1566 {
1567 TCGv tmp;
1568
1569 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1570 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1571 gen_jmp(s, tmp);
1572 }
1573
1574 DISAS_INSN(jump)
1575 {
1576 TCGv tmp;
1577
1578 /* Load the target address first to ensure correct exception
1579 behavior. */
1580 tmp = gen_lea(env, s, insn, OS_LONG);
1581 if (IS_NULL_QREG(tmp)) {
1582 gen_addr_fault(s);
1583 return;
1584 }
1585 if ((insn & 0x40) == 0) {
1586 /* jsr */
1587 gen_push(s, tcg_const_i32(s->pc));
1588 }
1589 gen_jmp(s, tmp);
1590 }
1591
1592 DISAS_INSN(addsubq)
1593 {
1594 TCGv src1;
1595 TCGv src2;
1596 TCGv dest;
1597 int val;
1598 TCGv addr;
1599
1600 SRC_EA(env, src1, OS_LONG, 0, &addr);
1601 val = (insn >> 9) & 7;
1602 if (val == 0)
1603 val = 8;
1604 dest = tcg_temp_new();
1605 tcg_gen_mov_i32(dest, src1);
1606 if ((insn & 0x38) == 0x08) {
1607 /* Don't update condition codes if the destination is an
1608 address register. */
1609 if (insn & 0x0100) {
1610 tcg_gen_subi_i32(dest, dest, val);
1611 } else {
1612 tcg_gen_addi_i32(dest, dest, val);
1613 }
1614 } else {
1615 src2 = tcg_const_i32(val);
1616 if (insn & 0x0100) {
1617 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1618 tcg_gen_subi_i32(dest, dest, val);
1619 s->cc_op = CC_OP_SUB;
1620 } else {
1621 tcg_gen_addi_i32(dest, dest, val);
1622 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1623 s->cc_op = CC_OP_ADD;
1624 }
1625 gen_update_cc_add(dest, src2);
1626 }
1627 DEST_EA(env, insn, OS_LONG, dest, &addr);
1628 }
1629
1630 DISAS_INSN(tpf)
1631 {
1632 switch (insn & 7) {
1633 case 2: /* One extension word. */
1634 s->pc += 2;
1635 break;
1636 case 3: /* Two extension words. */
1637 s->pc += 4;
1638 break;
1639 case 4: /* No extension words. */
1640 break;
1641 default:
1642 disas_undef(env, s, insn);
1643 }
1644 }
1645
1646 DISAS_INSN(branch)
1647 {
1648 int32_t offset;
1649 uint32_t base;
1650 int op;
1651 int l1;
1652
1653 base = s->pc;
1654 op = (insn >> 8) & 0xf;
1655 offset = (int8_t)insn;
1656 if (offset == 0) {
1657 offset = cpu_ldsw_code(env, s->pc);
1658 s->pc += 2;
1659 } else if (offset == -1) {
1660 offset = read_im32(env, s);
1661 }
1662 if (op == 1) {
1663 /* bsr */
1664 gen_push(s, tcg_const_i32(s->pc));
1665 }
1666 gen_flush_cc_op(s);
1667 if (op > 1) {
1668 /* Bcc */
1669 l1 = gen_new_label();
1670 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1671 gen_jmp_tb(s, 1, base + offset);
1672 gen_set_label(l1);
1673 gen_jmp_tb(s, 0, s->pc);
1674 } else {
1675 /* Unconditional branch. */
1676 gen_jmp_tb(s, 0, base + offset);
1677 }
1678 }
1679
1680 DISAS_INSN(moveq)
1681 {
1682 uint32_t val;
1683
1684 val = (int8_t)insn;
1685 tcg_gen_movi_i32(DREG(insn, 9), val);
1686 gen_logic_cc(s, tcg_const_i32(val));
1687 }
1688
1689 DISAS_INSN(mvzs)
1690 {
1691 int opsize;
1692 TCGv src;
1693 TCGv reg;
1694
1695 if (insn & 0x40)
1696 opsize = OS_WORD;
1697 else
1698 opsize = OS_BYTE;
1699 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1700 reg = DREG(insn, 9);
1701 tcg_gen_mov_i32(reg, src);
1702 gen_logic_cc(s, src);
1703 }
1704
1705 DISAS_INSN(or)
1706 {
1707 TCGv reg;
1708 TCGv dest;
1709 TCGv src;
1710 TCGv addr;
1711
1712 reg = DREG(insn, 9);
1713 dest = tcg_temp_new();
1714 if (insn & 0x100) {
1715 SRC_EA(env, src, OS_LONG, 0, &addr);
1716 tcg_gen_or_i32(dest, src, reg);
1717 DEST_EA(env, insn, OS_LONG, dest, &addr);
1718 } else {
1719 SRC_EA(env, src, OS_LONG, 0, NULL);
1720 tcg_gen_or_i32(dest, src, reg);
1721 tcg_gen_mov_i32(reg, dest);
1722 }
1723 gen_logic_cc(s, dest);
1724 }
1725
1726 DISAS_INSN(suba)
1727 {
1728 TCGv src;
1729 TCGv reg;
1730
1731 SRC_EA(env, src, OS_LONG, 0, NULL);
1732 reg = AREG(insn, 9);
1733 tcg_gen_sub_i32(reg, reg, src);
1734 }
1735
1736 DISAS_INSN(subx)
1737 {
1738 TCGv reg;
1739 TCGv src;
1740
1741 gen_flush_flags(s);
1742 reg = DREG(insn, 9);
1743 src = DREG(insn, 0);
1744 gen_helper_subx_cc(reg, cpu_env, reg, src);
1745 }
1746
1747 DISAS_INSN(mov3q)
1748 {
1749 TCGv src;
1750 int val;
1751
1752 val = (insn >> 9) & 7;
1753 if (val == 0)
1754 val = -1;
1755 src = tcg_const_i32(val);
1756 gen_logic_cc(s, src);
1757 DEST_EA(env, insn, OS_LONG, src, NULL);
1758 }
1759
1760 DISAS_INSN(cmp)
1761 {
1762 int op;
1763 TCGv src;
1764 TCGv reg;
1765 TCGv dest;
1766 int opsize;
1767
1768 op = (insn >> 6) & 3;
1769 switch (op) {
1770 case 0: /* cmp.b */
1771 opsize = OS_BYTE;
1772 s->cc_op = CC_OP_CMPB;
1773 break;
1774 case 1: /* cmp.w */
1775 opsize = OS_WORD;
1776 s->cc_op = CC_OP_CMPW;
1777 break;
1778 case 2: /* cmp.l */
1779 opsize = OS_LONG;
1780 s->cc_op = CC_OP_SUB;
1781 break;
1782 default:
1783 abort();
1784 }
1785 SRC_EA(env, src, opsize, 1, NULL);
1786 reg = DREG(insn, 9);
1787 dest = tcg_temp_new();
1788 tcg_gen_sub_i32(dest, reg, src);
1789 gen_update_cc_add(dest, src);
1790 }
1791
1792 DISAS_INSN(cmpa)
1793 {
1794 int opsize;
1795 TCGv src;
1796 TCGv reg;
1797 TCGv dest;
1798
1799 if (insn & 0x100) {
1800 opsize = OS_LONG;
1801 } else {
1802 opsize = OS_WORD;
1803 }
1804 SRC_EA(env, src, opsize, 1, NULL);
1805 reg = AREG(insn, 9);
1806 dest = tcg_temp_new();
1807 tcg_gen_sub_i32(dest, reg, src);
1808 gen_update_cc_add(dest, src);
1809 s->cc_op = CC_OP_SUB;
1810 }
1811
1812 DISAS_INSN(eor)
1813 {
1814 TCGv src;
1815 TCGv reg;
1816 TCGv dest;
1817 TCGv addr;
1818
1819 SRC_EA(env, src, OS_LONG, 0, &addr);
1820 reg = DREG(insn, 9);
1821 dest = tcg_temp_new();
1822 tcg_gen_xor_i32(dest, src, reg);
1823 gen_logic_cc(s, dest);
1824 DEST_EA(env, insn, OS_LONG, dest, &addr);
1825 }
1826
1827 DISAS_INSN(and)
1828 {
1829 TCGv src;
1830 TCGv reg;
1831 TCGv dest;
1832 TCGv addr;
1833
1834 reg = DREG(insn, 9);
1835 dest = tcg_temp_new();
1836 if (insn & 0x100) {
1837 SRC_EA(env, src, OS_LONG, 0, &addr);
1838 tcg_gen_and_i32(dest, src, reg);
1839 DEST_EA(env, insn, OS_LONG, dest, &addr);
1840 } else {
1841 SRC_EA(env, src, OS_LONG, 0, NULL);
1842 tcg_gen_and_i32(dest, src, reg);
1843 tcg_gen_mov_i32(reg, dest);
1844 }
1845 gen_logic_cc(s, dest);
1846 }
1847
1848 DISAS_INSN(adda)
1849 {
1850 TCGv src;
1851 TCGv reg;
1852
1853 SRC_EA(env, src, OS_LONG, 0, NULL);
1854 reg = AREG(insn, 9);
1855 tcg_gen_add_i32(reg, reg, src);
1856 }
1857
1858 DISAS_INSN(addx)
1859 {
1860 TCGv reg;
1861 TCGv src;
1862
1863 gen_flush_flags(s);
1864 reg = DREG(insn, 9);
1865 src = DREG(insn, 0);
1866 gen_helper_addx_cc(reg, cpu_env, reg, src);
1867 s->cc_op = CC_OP_FLAGS;
1868 }
1869
1870 /* TODO: This could be implemented without helper functions. */
1871 DISAS_INSN(shift_im)
1872 {
1873 TCGv reg;
1874 int tmp;
1875 TCGv shift;
1876
1877 reg = DREG(insn, 0);
1878 tmp = (insn >> 9) & 7;
1879 if (tmp == 0)
1880 tmp = 8;
1881 shift = tcg_const_i32(tmp);
1882 /* No need to flush flags becuse we know we will set C flag. */
1883 if (insn & 0x100) {
1884 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1885 } else {
1886 if (insn & 8) {
1887 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1888 } else {
1889 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1890 }
1891 }
1892 s->cc_op = CC_OP_SHIFT;
1893 }
1894
1895 DISAS_INSN(shift_reg)
1896 {
1897 TCGv reg;
1898 TCGv shift;
1899
1900 reg = DREG(insn, 0);
1901 shift = DREG(insn, 9);
1902 /* Shift by zero leaves C flag unmodified. */
1903 gen_flush_flags(s);
1904 if (insn & 0x100) {
1905 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1906 } else {
1907 if (insn & 8) {
1908 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1909 } else {
1910 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1911 }
1912 }
1913 s->cc_op = CC_OP_SHIFT;
1914 }
1915
1916 DISAS_INSN(ff1)
1917 {
1918 TCGv reg;
1919 reg = DREG(insn, 0);
1920 gen_logic_cc(s, reg);
1921 gen_helper_ff1(reg, reg);
1922 }
1923
1924 static TCGv gen_get_sr(DisasContext *s)
1925 {
1926 TCGv ccr;
1927 TCGv sr;
1928
1929 ccr = gen_get_ccr(s);
1930 sr = tcg_temp_new();
1931 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
1932 tcg_gen_or_i32(sr, sr, ccr);
1933 return sr;
1934 }
1935
1936 DISAS_INSN(strldsr)
1937 {
1938 uint16_t ext;
1939 uint32_t addr;
1940
1941 addr = s->pc - 2;
1942 ext = cpu_lduw_code(env, s->pc);
1943 s->pc += 2;
1944 if (ext != 0x46FC) {
1945 gen_exception(s, addr, EXCP_UNSUPPORTED);
1946 return;
1947 }
1948 ext = cpu_lduw_code(env, s->pc);
1949 s->pc += 2;
1950 if (IS_USER(s) || (ext & SR_S) == 0) {
1951 gen_exception(s, addr, EXCP_PRIVILEGE);
1952 return;
1953 }
1954 gen_push(s, gen_get_sr(s));
1955 gen_set_sr_im(s, ext, 0);
1956 }
1957
1958 DISAS_INSN(move_from_sr)
1959 {
1960 TCGv reg;
1961 TCGv sr;
1962
1963 if (IS_USER(s)) {
1964 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1965 return;
1966 }
1967 sr = gen_get_sr(s);
1968 reg = DREG(insn, 0);
1969 gen_partset_reg(OS_WORD, reg, sr);
1970 }
1971
1972 DISAS_INSN(move_to_sr)
1973 {
1974 if (IS_USER(s)) {
1975 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1976 return;
1977 }
1978 gen_set_sr(env, s, insn, 0);
1979 gen_lookup_tb(s);
1980 }
1981
1982 DISAS_INSN(move_from_usp)
1983 {
1984 if (IS_USER(s)) {
1985 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1986 return;
1987 }
1988 /* TODO: Implement USP. */
1989 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1990 }
1991
1992 DISAS_INSN(move_to_usp)
1993 {
1994 if (IS_USER(s)) {
1995 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1996 return;
1997 }
1998 /* TODO: Implement USP. */
1999 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
2000 }
2001
2002 DISAS_INSN(halt)
2003 {
2004 gen_exception(s, s->pc, EXCP_HALT_INSN);
2005 }
2006
2007 DISAS_INSN(stop)
2008 {
2009 uint16_t ext;
2010
2011 if (IS_USER(s)) {
2012 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2013 return;
2014 }
2015
2016 ext = cpu_lduw_code(env, s->pc);
2017 s->pc += 2;
2018
2019 gen_set_sr_im(s, ext, 0);
2020 tcg_gen_movi_i32(cpu_halted, 1);
2021 gen_exception(s, s->pc, EXCP_HLT);
2022 }
2023
2024 DISAS_INSN(rte)
2025 {
2026 if (IS_USER(s)) {
2027 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2028 return;
2029 }
2030 gen_exception(s, s->pc - 2, EXCP_RTE);
2031 }
2032
2033 DISAS_INSN(movec)
2034 {
2035 uint16_t ext;
2036 TCGv reg;
2037
2038 if (IS_USER(s)) {
2039 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2040 return;
2041 }
2042
2043 ext = cpu_lduw_code(env, s->pc);
2044 s->pc += 2;
2045
2046 if (ext & 0x8000) {
2047 reg = AREG(ext, 12);
2048 } else {
2049 reg = DREG(ext, 12);
2050 }
2051 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2052 gen_lookup_tb(s);
2053 }
2054
2055 DISAS_INSN(intouch)
2056 {
2057 if (IS_USER(s)) {
2058 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2059 return;
2060 }
2061 /* ICache fetch. Implement as no-op. */
2062 }
2063
2064 DISAS_INSN(cpushl)
2065 {
2066 if (IS_USER(s)) {
2067 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2068 return;
2069 }
2070 /* Cache push/invalidate. Implement as no-op. */
2071 }
2072
2073 DISAS_INSN(wddata)
2074 {
2075 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2076 }
2077
2078 DISAS_INSN(wdebug)
2079 {
2080 if (IS_USER(s)) {
2081 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2082 return;
2083 }
2084 /* TODO: Implement wdebug. */
2085 cpu_abort(env, "WDEBUG not implemented");
2086 }
2087
2088 DISAS_INSN(trap)
2089 {
2090 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2091 }
2092
2093 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2094 immediately before the next FP instruction is executed. */
2095 DISAS_INSN(fpu)
2096 {
2097 uint16_t ext;
2098 int32_t offset;
2099 int opmode;
2100 TCGv_i64 src;
2101 TCGv_i64 dest;
2102 TCGv_i64 res;
2103 TCGv tmp32;
2104 int round;
2105 int set_dest;
2106 int opsize;
2107
2108 ext = cpu_lduw_code(env, s->pc);
2109 s->pc += 2;
2110 opmode = ext & 0x7f;
2111 switch ((ext >> 13) & 7) {
2112 case 0: case 2:
2113 break;
2114 case 1:
2115 goto undef;
2116 case 3: /* fmove out */
2117 src = FREG(ext, 7);
2118 tmp32 = tcg_temp_new_i32();
2119 /* fmove */
2120 /* ??? TODO: Proper behavior on overflow. */
2121 switch ((ext >> 10) & 7) {
2122 case 0:
2123 opsize = OS_LONG;
2124 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2125 break;
2126 case 1:
2127 opsize = OS_SINGLE;
2128 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2129 break;
2130 case 4:
2131 opsize = OS_WORD;
2132 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2133 break;
2134 case 5: /* OS_DOUBLE */
2135 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2136 switch ((insn >> 3) & 7) {
2137 case 2:
2138 case 3:
2139 break;
2140 case 4:
2141 tcg_gen_addi_i32(tmp32, tmp32, -8);
2142 break;
2143 case 5:
2144 offset = cpu_ldsw_code(env, s->pc);
2145 s->pc += 2;
2146 tcg_gen_addi_i32(tmp32, tmp32, offset);
2147 break;
2148 default:
2149 goto undef;
2150 }
2151 gen_store64(s, tmp32, src);
2152 switch ((insn >> 3) & 7) {
2153 case 3:
2154 tcg_gen_addi_i32(tmp32, tmp32, 8);
2155 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2156 break;
2157 case 4:
2158 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2159 break;
2160 }
2161 tcg_temp_free_i32(tmp32);
2162 return;
2163 case 6:
2164 opsize = OS_BYTE;
2165 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2166 break;
2167 default:
2168 goto undef;
2169 }
2170 DEST_EA(env, insn, opsize, tmp32, NULL);
2171 tcg_temp_free_i32(tmp32);
2172 return;
2173 case 4: /* fmove to control register. */
2174 switch ((ext >> 10) & 7) {
2175 case 4: /* FPCR */
2176 /* Not implemented. Ignore writes. */
2177 break;
2178 case 1: /* FPIAR */
2179 case 2: /* FPSR */
2180 default:
2181 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2182 (ext >> 10) & 7);
2183 }
2184 break;
2185 case 5: /* fmove from control register. */
2186 switch ((ext >> 10) & 7) {
2187 case 4: /* FPCR */
2188 /* Not implemented. Always return zero. */
2189 tmp32 = tcg_const_i32(0);
2190 break;
2191 case 1: /* FPIAR */
2192 case 2: /* FPSR */
2193 default:
2194 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2195 (ext >> 10) & 7);
2196 goto undef;
2197 }
2198 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2199 break;
2200 case 6: /* fmovem */
2201 case 7:
2202 {
2203 TCGv addr;
2204 uint16_t mask;
2205 int i;
2206 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2207 goto undef;
2208 tmp32 = gen_lea(env, s, insn, OS_LONG);
2209 if (IS_NULL_QREG(tmp32)) {
2210 gen_addr_fault(s);
2211 return;
2212 }
2213 addr = tcg_temp_new_i32();
2214 tcg_gen_mov_i32(addr, tmp32);
2215 mask = 0x80;
2216 for (i = 0; i < 8; i++) {
2217 if (ext & mask) {
2218 s->is_mem = 1;
2219 dest = FREG(i, 0);
2220 if (ext & (1 << 13)) {
2221 /* store */
2222 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2223 } else {
2224 /* load */
2225 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2226 }
2227 if (ext & (mask - 1))
2228 tcg_gen_addi_i32(addr, addr, 8);
2229 }
2230 mask >>= 1;
2231 }
2232 tcg_temp_free_i32(addr);
2233 }
2234 return;
2235 }
2236 if (ext & (1 << 14)) {
2237 /* Source effective address. */
2238 switch ((ext >> 10) & 7) {
2239 case 0: opsize = OS_LONG; break;
2240 case 1: opsize = OS_SINGLE; break;
2241 case 4: opsize = OS_WORD; break;
2242 case 5: opsize = OS_DOUBLE; break;
2243 case 6: opsize = OS_BYTE; break;
2244 default:
2245 goto undef;
2246 }
2247 if (opsize == OS_DOUBLE) {
2248 tmp32 = tcg_temp_new_i32();
2249 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2250 switch ((insn >> 3) & 7) {
2251 case 2:
2252 case 3:
2253 break;
2254 case 4:
2255 tcg_gen_addi_i32(tmp32, tmp32, -8);
2256 break;
2257 case 5:
2258 offset = cpu_ldsw_code(env, s->pc);
2259 s->pc += 2;
2260 tcg_gen_addi_i32(tmp32, tmp32, offset);
2261 break;
2262 case 7:
2263 offset = cpu_ldsw_code(env, s->pc);
2264 offset += s->pc - 2;
2265 s->pc += 2;
2266 tcg_gen_addi_i32(tmp32, tmp32, offset);
2267 break;
2268 default:
2269 goto undef;
2270 }
2271 src = gen_load64(s, tmp32);
2272 switch ((insn >> 3) & 7) {
2273 case 3:
2274 tcg_gen_addi_i32(tmp32, tmp32, 8);
2275 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2276 break;
2277 case 4:
2278 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2279 break;
2280 }
2281 tcg_temp_free_i32(tmp32);
2282 } else {
2283 SRC_EA(env, tmp32, opsize, 1, NULL);
2284 src = tcg_temp_new_i64();
2285 switch (opsize) {
2286 case OS_LONG:
2287 case OS_WORD:
2288 case OS_BYTE:
2289 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2290 break;
2291 case OS_SINGLE:
2292 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2293 break;
2294 }
2295 }
2296 } else {
2297 /* Source register. */
2298 src = FREG(ext, 10);
2299 }
2300 dest = FREG(ext, 7);
2301 res = tcg_temp_new_i64();
2302 if (opmode != 0x3a)
2303 tcg_gen_mov_f64(res, dest);
2304 round = 1;
2305 set_dest = 1;
2306 switch (opmode) {
2307 case 0: case 0x40: case 0x44: /* fmove */
2308 tcg_gen_mov_f64(res, src);
2309 break;
2310 case 1: /* fint */
2311 gen_helper_iround_f64(res, cpu_env, src);
2312 round = 0;
2313 break;
2314 case 3: /* fintrz */
2315 gen_helper_itrunc_f64(res, cpu_env, src);
2316 round = 0;
2317 break;
2318 case 4: case 0x41: case 0x45: /* fsqrt */
2319 gen_helper_sqrt_f64(res, cpu_env, src);
2320 break;
2321 case 0x18: case 0x58: case 0x5c: /* fabs */
2322 gen_helper_abs_f64(res, src);
2323 break;
2324 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2325 gen_helper_chs_f64(res, src);
2326 break;
2327 case 0x20: case 0x60: case 0x64: /* fdiv */
2328 gen_helper_div_f64(res, cpu_env, res, src);
2329 break;
2330 case 0x22: case 0x62: case 0x66: /* fadd */
2331 gen_helper_add_f64(res, cpu_env, res, src);
2332 break;
2333 case 0x23: case 0x63: case 0x67: /* fmul */
2334 gen_helper_mul_f64(res, cpu_env, res, src);
2335 break;
2336 case 0x28: case 0x68: case 0x6c: /* fsub */
2337 gen_helper_sub_f64(res, cpu_env, res, src);
2338 break;
2339 case 0x38: /* fcmp */
2340 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2341 set_dest = 0;
2342 round = 0;
2343 break;
2344 case 0x3a: /* ftst */
2345 tcg_gen_mov_f64(res, src);
2346 set_dest = 0;
2347 round = 0;
2348 break;
2349 default:
2350 goto undef;
2351 }
2352 if (ext & (1 << 14)) {
2353 tcg_temp_free_i64(src);
2354 }
2355 if (round) {
2356 if (opmode & 0x40) {
2357 if ((opmode & 0x4) != 0)
2358 round = 0;
2359 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2360 round = 0;
2361 }
2362 }
2363 if (round) {
2364 TCGv tmp = tcg_temp_new_i32();
2365 gen_helper_f64_to_f32(tmp, cpu_env, res);
2366 gen_helper_f32_to_f64(res, cpu_env, tmp);
2367 tcg_temp_free_i32(tmp);
2368 }
2369 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2370 if (set_dest) {
2371 tcg_gen_mov_f64(dest, res);
2372 }
2373 tcg_temp_free_i64(res);
2374 return;
2375 undef:
2376 /* FIXME: Is this right for offset addressing modes? */
2377 s->pc -= 2;
2378 disas_undef_fpu(env, s, insn);
2379 }
2380
2381 DISAS_INSN(fbcc)
2382 {
2383 uint32_t offset;
2384 uint32_t addr;
2385 TCGv flag;
2386 int l1;
2387
2388 addr = s->pc;
2389 offset = cpu_ldsw_code(env, s->pc);
2390 s->pc += 2;
2391 if (insn & (1 << 6)) {
2392 offset = (offset << 16) | cpu_lduw_code(env, s->pc);
2393 s->pc += 2;
2394 }
2395
2396 l1 = gen_new_label();
2397 /* TODO: Raise BSUN exception. */
2398 flag = tcg_temp_new();
2399 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2400 /* Jump to l1 if condition is true. */
2401 switch (insn & 0xf) {
2402 case 0: /* f */
2403 break;
2404 case 1: /* eq (=0) */
2405 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2406 break;
2407 case 2: /* ogt (=1) */
2408 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2409 break;
2410 case 3: /* oge (=0 or =1) */
2411 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2412 break;
2413 case 4: /* olt (=-1) */
2414 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2415 break;
2416 case 5: /* ole (=-1 or =0) */
2417 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2418 break;
2419 case 6: /* ogl (=-1 or =1) */
2420 tcg_gen_andi_i32(flag, flag, 1);
2421 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2422 break;
2423 case 7: /* or (=2) */
2424 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2425 break;
2426 case 8: /* un (<2) */
2427 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2428 break;
2429 case 9: /* ueq (=0 or =2) */
2430 tcg_gen_andi_i32(flag, flag, 1);
2431 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2432 break;
2433 case 10: /* ugt (>0) */
2434 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2435 break;
2436 case 11: /* uge (>=0) */
2437 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2438 break;
2439 case 12: /* ult (=-1 or =2) */
2440 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2441 break;
2442 case 13: /* ule (!=1) */
2443 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2444 break;
2445 case 14: /* ne (!=0) */
2446 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2447 break;
2448 case 15: /* t */
2449 tcg_gen_br(l1);
2450 break;
2451 }
2452 gen_jmp_tb(s, 0, s->pc);
2453 gen_set_label(l1);
2454 gen_jmp_tb(s, 1, addr + offset);
2455 }
2456
2457 DISAS_INSN(frestore)
2458 {
2459 /* TODO: Implement frestore. */
2460 cpu_abort(env, "FRESTORE not implemented");
2461 }
2462
2463 DISAS_INSN(fsave)
2464 {
2465 /* TODO: Implement fsave. */
2466 cpu_abort(env, "FSAVE not implemented");
2467 }
2468
2469 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2470 {
2471 TCGv tmp = tcg_temp_new();
2472 if (s->env->macsr & MACSR_FI) {
2473 if (upper)
2474 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2475 else
2476 tcg_gen_shli_i32(tmp, val, 16);
2477 } else if (s->env->macsr & MACSR_SU) {
2478 if (upper)
2479 tcg_gen_sari_i32(tmp, val, 16);
2480 else
2481 tcg_gen_ext16s_i32(tmp, val);
2482 } else {
2483 if (upper)
2484 tcg_gen_shri_i32(tmp, val, 16);
2485 else
2486 tcg_gen_ext16u_i32(tmp, val);
2487 }
2488 return tmp;
2489 }
2490
2491 static void gen_mac_clear_flags(void)
2492 {
2493 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2494 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2495 }
2496
2497 DISAS_INSN(mac)
2498 {
2499 TCGv rx;
2500 TCGv ry;
2501 uint16_t ext;
2502 int acc;
2503 TCGv tmp;
2504 TCGv addr;
2505 TCGv loadval;
2506 int dual;
2507 TCGv saved_flags;
2508
2509 if (!s->done_mac) {
2510 s->mactmp = tcg_temp_new_i64();
2511 s->done_mac = 1;
2512 }
2513
2514 ext = cpu_lduw_code(env, s->pc);
2515 s->pc += 2;
2516
2517 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2518 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2519 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2520 disas_undef(env, s, insn);
2521 return;
2522 }
2523 if (insn & 0x30) {
2524 /* MAC with load. */
2525 tmp = gen_lea(env, s, insn, OS_LONG);
2526 addr = tcg_temp_new();
2527 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2528 /* Load the value now to ensure correct exception behavior.
2529 Perform writeback after reading the MAC inputs. */
2530 loadval = gen_load(s, OS_LONG, addr, 0);
2531
2532 acc ^= 1;
2533 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2534 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2535 } else {
2536 loadval = addr = NULL_QREG;
2537 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2538 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2539 }
2540
2541 gen_mac_clear_flags();
2542 #if 0
2543 l1 = -1;
2544 /* Disabled because conditional branches clobber temporary vars. */
2545 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2546 /* Skip the multiply if we know we will ignore it. */
2547 l1 = gen_new_label();
2548 tmp = tcg_temp_new();
2549 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2550 gen_op_jmp_nz32(tmp, l1);
2551 }
2552 #endif
2553
2554 if ((ext & 0x0800) == 0) {
2555 /* Word. */
2556 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2557 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2558 }
2559 if (s->env->macsr & MACSR_FI) {
2560 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2561 } else {
2562 if (s->env->macsr & MACSR_SU)
2563 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2564 else
2565 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2566 switch ((ext >> 9) & 3) {
2567 case 1:
2568 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2569 break;
2570 case 3:
2571 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2572 break;
2573 }
2574 }
2575
2576 if (dual) {
2577 /* Save the overflow flag from the multiply. */
2578 saved_flags = tcg_temp_new();
2579 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2580 } else {
2581 saved_flags = NULL_QREG;
2582 }
2583
2584 #if 0
2585 /* Disabled because conditional branches clobber temporary vars. */
2586 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2587 /* Skip the accumulate if the value is already saturated. */
2588 l1 = gen_new_label();
2589 tmp = tcg_temp_new();
2590 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2591 gen_op_jmp_nz32(tmp, l1);
2592 }
2593 #endif
2594
2595 if (insn & 0x100)
2596 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2597 else
2598 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2599
2600 if (s->env->macsr & MACSR_FI)
2601 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2602 else if (s->env->macsr & MACSR_SU)
2603 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2604 else
2605 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2606
2607 #if 0
2608 /* Disabled because conditional branches clobber temporary vars. */
2609 if (l1 != -1)
2610 gen_set_label(l1);
2611 #endif
2612
2613 if (dual) {
2614 /* Dual accumulate variant. */
2615 acc = (ext >> 2) & 3;
2616 /* Restore the overflow flag from the multiplier. */
2617 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2618 #if 0
2619 /* Disabled because conditional branches clobber temporary vars. */
2620 if ((s->env->macsr & MACSR_OMC) != 0) {
2621 /* Skip the accumulate if the value is already saturated. */
2622 l1 = gen_new_label();
2623 tmp = tcg_temp_new();
2624 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2625 gen_op_jmp_nz32(tmp, l1);
2626 }
2627 #endif
2628 if (ext & 2)
2629 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2630 else
2631 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2632 if (s->env->macsr & MACSR_FI)
2633 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2634 else if (s->env->macsr & MACSR_SU)
2635 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2636 else
2637 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2638 #if 0
2639 /* Disabled because conditional branches clobber temporary vars. */
2640 if (l1 != -1)
2641 gen_set_label(l1);
2642 #endif
2643 }
2644 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2645
2646 if (insn & 0x30) {
2647 TCGv rw;
2648 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2649 tcg_gen_mov_i32(rw, loadval);
2650 /* FIXME: Should address writeback happen with the masked or
2651 unmasked value? */
2652 switch ((insn >> 3) & 7) {
2653 case 3: /* Post-increment. */
2654 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2655 break;
2656 case 4: /* Pre-decrement. */
2657 tcg_gen_mov_i32(AREG(insn, 0), addr);
2658 }
2659 }
2660 }
2661
2662 DISAS_INSN(from_mac)
2663 {
2664 TCGv rx;
2665 TCGv_i64 acc;
2666 int accnum;
2667
2668 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2669 accnum = (insn >> 9) & 3;
2670 acc = MACREG(accnum);
2671 if (s->env->macsr & MACSR_FI) {
2672 gen_helper_get_macf(rx, cpu_env, acc);
2673 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2674 tcg_gen_trunc_i64_i32(rx, acc);
2675 } else if (s->env->macsr & MACSR_SU) {
2676 gen_helper_get_macs(rx, acc);
2677 } else {
2678 gen_helper_get_macu(rx, acc);
2679 }
2680 if (insn & 0x40) {
2681 tcg_gen_movi_i64(acc, 0);
2682 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2683 }
2684 }
2685
2686 DISAS_INSN(move_mac)
2687 {
2688 /* FIXME: This can be done without a helper. */
2689 int src;
2690 TCGv dest;
2691 src = insn & 3;
2692 dest = tcg_const_i32((insn >> 9) & 3);
2693 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2694 gen_mac_clear_flags();
2695 gen_helper_mac_set_flags(cpu_env, dest);
2696 }
2697
2698 DISAS_INSN(from_macsr)
2699 {
2700 TCGv reg;
2701
2702 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2703 tcg_gen_mov_i32(reg, QREG_MACSR);
2704 }
2705
2706 DISAS_INSN(from_mask)
2707 {
2708 TCGv reg;
2709 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2710 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2711 }
2712
2713 DISAS_INSN(from_mext)
2714 {
2715 TCGv reg;
2716 TCGv acc;
2717 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2718 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2719 if (s->env->macsr & MACSR_FI)
2720 gen_helper_get_mac_extf(reg, cpu_env, acc);
2721 else
2722 gen_helper_get_mac_exti(reg, cpu_env, acc);
2723 }
2724
2725 DISAS_INSN(macsr_to_ccr)
2726 {
2727 tcg_gen_movi_i32(QREG_CC_X, 0);
2728 tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
2729 s->cc_op = CC_OP_FLAGS;
2730 }
2731
2732 DISAS_INSN(to_mac)
2733 {
2734 TCGv_i64 acc;
2735 TCGv val;
2736 int accnum;
2737 accnum = (insn >> 9) & 3;
2738 acc = MACREG(accnum);
2739 SRC_EA(env, val, OS_LONG, 0, NULL);
2740 if (s->env->macsr & MACSR_FI) {
2741 tcg_gen_ext_i32_i64(acc, val);
2742 tcg_gen_shli_i64(acc, acc, 8);
2743 } else if (s->env->macsr & MACSR_SU) {
2744 tcg_gen_ext_i32_i64(acc, val);
2745 } else {
2746 tcg_gen_extu_i32_i64(acc, val);
2747 }
2748 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2749 gen_mac_clear_flags();
2750 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2751 }
2752
2753 DISAS_INSN(to_macsr)
2754 {
2755 TCGv val;
2756 SRC_EA(env, val, OS_LONG, 0, NULL);
2757 gen_helper_set_macsr(cpu_env, val);
2758 gen_lookup_tb(s);
2759 }
2760
2761 DISAS_INSN(to_mask)
2762 {
2763 TCGv val;
2764 SRC_EA(env, val, OS_LONG, 0, NULL);
2765 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2766 }
2767
2768 DISAS_INSN(to_mext)
2769 {
2770 TCGv val;
2771 TCGv acc;
2772 SRC_EA(env, val, OS_LONG, 0, NULL);
2773 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2774 if (s->env->macsr & MACSR_FI)
2775 gen_helper_set_mac_extf(cpu_env, val, acc);
2776 else if (s->env->macsr & MACSR_SU)
2777 gen_helper_set_mac_exts(cpu_env, val, acc);
2778 else
2779 gen_helper_set_mac_extu(cpu_env, val, acc);
2780 }
2781
2782 static disas_proc opcode_table[65536];
2783
2784 static void
2785 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2786 {
2787 int i;
2788 int from;
2789 int to;
2790
2791 /* Sanity check. All set bits must be included in the mask. */
2792 if (opcode & ~mask) {
2793 fprintf(stderr,
2794 "qemu internal error: bogus opcode definition %04x/%04x\n",
2795 opcode, mask);
2796 abort();
2797 }
2798 /* This could probably be cleverer. For now just optimize the case where
2799 the top bits are known. */
2800 /* Find the first zero bit in the mask. */
2801 i = 0x8000;
2802 while ((i & mask) != 0)
2803 i >>= 1;
2804 /* Iterate over all combinations of this and lower bits. */
2805 if (i == 0)
2806 i = 1;
2807 else
2808 i <<= 1;
2809 from = opcode & ~(i - 1);
2810 to = from + i;
2811 for (i = from; i < to; i++) {
2812 if ((i & mask) == opcode)
2813 opcode_table[i] = proc;
2814 }
2815 }
2816
2817 /* Register m68k opcode handlers. Order is important.
2818 Later insn override earlier ones. */
2819 void register_m68k_insns (CPUM68KState *env)
2820 {
2821 #define INSN(name, opcode, mask, feature) do { \
2822 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2823 register_opcode(disas_##name, 0x##opcode, 0x##mask); \
2824 } while(0)
2825 INSN(undef, 0000, 0000, CF_ISA_A);
2826 INSN(arith_im, 0080, fff8, CF_ISA_A);
2827 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
2828 INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
2829 INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
2830 INSN(bitop_reg, 0180, f1c0, CF_ISA_A);
2831 INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);
2832 INSN(arith_im, 0280, fff8, CF_ISA_A);
2833 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
2834 INSN(arith_im, 0480, fff8, CF_ISA_A);
2835 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
2836 INSN(arith_im, 0680, fff8, CF_ISA_A);
2837 INSN(bitop_im, 0800, ffc0, CF_ISA_A);
2838 INSN(bitop_im, 0840, ffc0, CF_ISA_A);
2839 INSN(bitop_im, 0880, ffc0, CF_ISA_A);
2840 INSN(bitop_im, 08c0, ffc0, CF_ISA_A);
2841 INSN(arith_im, 0a80, fff8, CF_ISA_A);
2842 INSN(arith_im, 0c00, ff38, CF_ISA_A);
2843 INSN(move, 1000, f000, CF_ISA_A);
2844 INSN(move, 2000, f000, CF_ISA_A);
2845 INSN(move, 3000, f000, CF_ISA_A);
2846 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
2847 INSN(negx, 4080, fff8, CF_ISA_A);
2848 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
2849 INSN(lea, 41c0, f1c0, CF_ISA_A);
2850 INSN(clr, 4200, ff00, CF_ISA_A);
2851 INSN(undef, 42c0, ffc0, CF_ISA_A);
2852 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
2853 INSN(neg, 4480, fff8, CF_ISA_A);
2854 INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);
2855 INSN(not, 4680, fff8, CF_ISA_A);
2856 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
2857 INSN(pea, 4840, ffc0, CF_ISA_A);
2858 INSN(swap, 4840, fff8, CF_ISA_A);
2859 INSN(movem, 48c0, fbc0, CF_ISA_A);
2860 INSN(ext, 4880, fff8, CF_ISA_A);
2861 INSN(ext, 48c0, fff8, CF_ISA_A);
2862 INSN(ext, 49c0, fff8, CF_ISA_A);
2863 INSN(tst, 4a00, ff00, CF_ISA_A);
2864 INSN(tas, 4ac0, ffc0, CF_ISA_B);
2865 INSN(halt, 4ac8, ffff, CF_ISA_A);
2866 INSN(pulse, 4acc, ffff, CF_ISA_A);
2867 INSN(illegal, 4afc, ffff, CF_ISA_A);
2868 INSN(mull, 4c00, ffc0, CF_ISA_A);
2869 INSN(divl, 4c40, ffc0, CF_ISA_A);
2870 INSN(sats, 4c80, fff8, CF_ISA_B);
2871 INSN(trap, 4e40, fff0, CF_ISA_A);
2872 INSN(link, 4e50, fff8, CF_ISA_A);
2873 INSN(unlk, 4e58, fff8, CF_ISA_A);
2874 INSN(move_to_usp, 4e60, fff8, USP);
2875 INSN(move_from_usp, 4e68, fff8, USP);
2876 INSN(nop, 4e71, ffff, CF_ISA_A);
2877 INSN(stop, 4e72, ffff, CF_ISA_A);
2878 INSN(rte, 4e73, ffff, CF_ISA_A);
2879 INSN(rts, 4e75, ffff, CF_ISA_A);
2880 INSN(movec, 4e7b, ffff, CF_ISA_A);
2881 INSN(jump, 4e80, ffc0, CF_ISA_A);
2882 INSN(jump, 4ec0, ffc0, CF_ISA_A);
2883 INSN(addsubq, 5180, f1c0, CF_ISA_A);
2884 INSN(scc, 50c0, f0f8, CF_ISA_A);
2885 INSN(addsubq, 5080, f1c0, CF_ISA_A);
2886 INSN(tpf, 51f8, fff8, CF_ISA_A);
2887
2888 /* Branch instructions. */
2889 INSN(branch, 6000, f000, CF_ISA_A);
2890 /* Disable long branch instructions, then add back the ones we want. */
2891 INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */
2892 INSN(branch, 60ff, f0ff, CF_ISA_B);
2893 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
2894 INSN(branch, 60ff, ffff, BRAL);
2895
2896 INSN(moveq, 7000, f100, CF_ISA_A);
2897 INSN(mvzs, 7100, f100, CF_ISA_B);
2898 INSN(or, 8000, f000, CF_ISA_A);
2899 INSN(divw, 80c0, f0c0, CF_ISA_A);
2900 INSN(addsub, 9000, f000, CF_ISA_A);
2901 INSN(subx, 9180, f1f8, CF_ISA_A);
2902 INSN(suba, 91c0, f1c0, CF_ISA_A);
2903
2904 INSN(undef_mac, a000, f000, CF_ISA_A);
2905 INSN(mac, a000, f100, CF_EMAC);
2906 INSN(from_mac, a180, f9b0, CF_EMAC);
2907 INSN(move_mac, a110, f9fc, CF_EMAC);
2908 INSN(from_macsr,a980, f9f0, CF_EMAC);
2909 INSN(from_mask, ad80, fff0, CF_EMAC);
2910 INSN(from_mext, ab80, fbf0, CF_EMAC);
2911 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
2912 INSN(to_mac, a100, f9c0, CF_EMAC);
2913 INSN(to_macsr, a900, ffc0, CF_EMAC);
2914 INSN(to_mext, ab00, fbc0, CF_EMAC);
2915 INSN(to_mask, ad00, ffc0, CF_EMAC);
2916
2917 INSN(mov3q, a140, f1c0, CF_ISA_B);
2918 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
2919 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
2920 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
2921 INSN(cmp, b080, f1c0, CF_ISA_A);
2922 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
2923 INSN(eor, b180, f1c0, CF_ISA_A);
2924 INSN(and, c000, f000, CF_ISA_A);
2925 INSN(mulw, c0c0, f0c0, CF_ISA_A);
2926 INSN(addsub, d000, f000, CF_ISA_A);
2927 INSN(addx, d180, f1f8, CF_ISA_A);
2928 INSN(adda, d1c0, f1c0, CF_ISA_A);
2929 INSN(shift_im, e080, f0f0, CF_ISA_A);
2930 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
2931 INSN(undef_fpu, f000, f000, CF_ISA_A);
2932 INSN(fpu, f200, ffc0, CF_FPU);
2933 INSN(fbcc, f280, ffc0, CF_FPU);
2934 INSN(frestore, f340, ffc0, CF_FPU);
2935 INSN(fsave, f340, ffc0, CF_FPU);
2936 INSN(intouch, f340, ffc0, CF_ISA_A);
2937 INSN(cpushl, f428, ff38, CF_ISA_A);
2938 INSN(wddata, fb00, ff00, CF_ISA_A);
2939 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
2940 #undef INSN
2941 }
2942
2943 /* ??? Some of this implementation is not exception safe. We should always
2944 write back the result to memory before setting the condition codes. */
2945 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
2946 {
2947 uint16_t insn;
2948
2949 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
2950 tcg_gen_debug_insn_start(s->pc);
2951 }
2952
2953 insn = cpu_lduw_code(env, s->pc);
2954 s->pc += 2;
2955
2956 opcode_table[insn](env, s, insn);
2957 }
2958
2959 /* generate intermediate code for basic block 'tb'. */
2960 static inline void
2961 gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
2962 bool search_pc)
2963 {
2964 CPUState *cs = CPU(cpu);
2965 CPUM68KState *env = &cpu->env;
2966 DisasContext dc1, *dc = &dc1;
2967 uint16_t *gen_opc_end;
2968 CPUBreakpoint *bp;
2969 int j, lj;
2970 target_ulong pc_start;
2971 int pc_offset;
2972 int num_insns;
2973 int max_insns;
2974
2975 /* generate intermediate code */
2976 pc_start = tb->pc;
2977
2978 dc->tb = tb;
2979
2980 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
2981
2982 dc->env = env;
2983 dc->is_jmp = DISAS_NEXT;
2984 dc->pc = pc_start;
2985 dc->cc_op = CC_OP_DYNAMIC;
2986 dc->singlestep_enabled = cs->singlestep_enabled;
2987 dc->fpcr = env->fpcr;
2988 dc->user = (env->sr & SR_S) == 0;
2989 dc->is_mem = 0;
2990 dc->done_mac = 0;
2991 lj = -1;
2992 num_insns = 0;
2993 max_insns = tb->cflags & CF_COUNT_MASK;
2994 if (max_insns == 0)
2995 max_insns = CF_COUNT_MASK;
2996
2997 gen_tb_start();
2998 do {
2999 pc_offset = dc->pc - pc_start;
3000 gen_throws_exception = NULL;
3001 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
3002 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3003 if (bp->pc == dc->pc) {
3004 gen_exception(dc, dc->pc, EXCP_DEBUG);
3005 dc->is_jmp = DISAS_JUMP;
3006 break;
3007 }
3008 }
3009 if (dc->is_jmp)
3010 break;
3011 }
3012 if (search_pc) {
3013 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3014 if (lj < j) {
3015 lj++;
3016 while (lj < j)
3017 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3018 }
3019 tcg_ctx.gen_opc_pc[lj] = dc->pc;
3020 tcg_ctx.gen_opc_instr_start[lj] = 1;
3021 tcg_ctx.gen_opc_icount[lj] = num_insns;
3022 }
3023 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3024 gen_io_start();
3025 dc->insn_pc = dc->pc;
3026 disas_m68k_insn(env, dc);
3027 num_insns++;
3028 } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
3029 !cs->singlestep_enabled &&
3030 !singlestep &&
3031 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3032 num_insns < max_insns);
3033
3034 if (tb->cflags & CF_LAST_IO)
3035 gen_io_end();
3036 if (unlikely(cs->singlestep_enabled)) {
3037 /* Make sure the pc is updated, and raise a debug exception. */
3038 if (!dc->is_jmp) {
3039 gen_flush_cc_op(dc);
3040 tcg_gen_movi_i32(QREG_PC, dc->pc);
3041 }
3042 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3043 } else {
3044 switch(dc->is_jmp) {
3045 case DISAS_NEXT:
3046 gen_flush_cc_op(dc);
3047 gen_jmp_tb(dc, 0, dc->pc);
3048 break;
3049 default:
3050 case DISAS_JUMP:
3051 case DISAS_UPDATE:
3052 gen_flush_cc_op(dc);
3053 /* indicate that the hash table must be used to find the next TB */
3054 tcg_gen_exit_tb(0);
3055 break;
3056 case DISAS_TB_JUMP:
3057 /* nothing more to generate */
3058 break;
3059 }
3060 }
3061 gen_tb_end(tb, num_insns);
3062 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3063
3064 #ifdef DEBUG_DISAS
3065 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3066 qemu_log("----------------\n");
3067 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3068 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
3069 qemu_log("\n");
3070 }
3071 #endif
3072 if (search_pc) {
3073 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3074 lj++;
3075 while (lj <= j)
3076 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3077 } else {
3078 tb->size = dc->pc - pc_start;
3079 tb->icount = num_insns;
3080 }
3081
3082 //optimize_flags();
3083 //expand_target_qops();
3084 }
3085
3086 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
3087 {
3088 gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, false);
3089 }
3090
3091 void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb)
3092 {
3093 gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, true);
3094 }
3095
3096 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3097 int flags)
3098 {
3099 M68kCPU *cpu = M68K_CPU(cs);
3100 CPUM68KState *env = &cpu->env;
3101 int i;
3102 uint16_t sr;
3103 CPU_DoubleU u;
3104 for (i = 0; i < 8; i++)
3105 {
3106 u.d = env->fregs[i];
3107 cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3108 i, env->dregs[i], i, env->aregs[i],
3109 i, u.l.upper, u.l.lower, *(double *)&u.d);
3110 }
3111 cpu_fprintf (f, "PC = %08x ", env->pc);
3112 sr = env->sr;
3113 cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-',
3114 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3115 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3116 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3117 }
3118
3119 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos)
3120 {
3121 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3122 }