cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / target-microblaze / cpu.c
1 /*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "cpu.h"
25 #include "qemu-common.h"
26 #include "hw/qdev-properties.h"
27 #include "migration/vmstate.h"
28
29
30 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
31 {
32 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
33
34 cpu->env.sregs[SR_PC] = value;
35 }
36
37 static bool mb_cpu_has_work(CPUState *cs)
38 {
39 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
40 }
41
42 #ifndef CONFIG_USER_ONLY
43 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
44 {
45 MicroBlazeCPU *cpu = opaque;
46 CPUState *cs = CPU(cpu);
47 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
48
49 if (level) {
50 cpu_interrupt(cs, type);
51 } else {
52 cpu_reset_interrupt(cs, type);
53 }
54 }
55 #endif
56
57 /* CPUClass::reset() */
58 static void mb_cpu_reset(CPUState *s)
59 {
60 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
61 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
62 CPUMBState *env = &cpu->env;
63
64 mcc->parent_reset(s);
65
66 memset(env, 0, sizeof(CPUMBState));
67 env->res_addr = RES_ADDR_NONE;
68 tlb_flush(s, 1);
69
70 /* Disable stack protector. */
71 env->shr = ~0;
72
73 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
74 | PVR0_USE_BARREL_MASK \
75 | PVR0_USE_DIV_MASK \
76 | PVR0_USE_HW_MUL_MASK \
77 | PVR0_USE_EXC_MASK \
78 | PVR0_USE_ICACHE_MASK \
79 | PVR0_USE_DCACHE_MASK \
80 | PVR0_USE_MMU \
81 | (0xb << 8);
82 env->pvr.regs[2] = PVR2_D_OPB_MASK \
83 | PVR2_D_LMB_MASK \
84 | PVR2_I_OPB_MASK \
85 | PVR2_I_LMB_MASK \
86 | PVR2_USE_MSR_INSTR \
87 | PVR2_USE_PCMP_INSTR \
88 | PVR2_USE_BARREL_MASK \
89 | PVR2_USE_DIV_MASK \
90 | PVR2_USE_HW_MUL_MASK \
91 | PVR2_USE_MUL64_MASK \
92 | PVR2_USE_FPU_MASK \
93 | PVR2_USE_FPU2_MASK \
94 | PVR2_FPU_EXC_MASK \
95 | 0;
96 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
97 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
98
99 #if defined(CONFIG_USER_ONLY)
100 /* start in user mode with interrupts enabled. */
101 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
102 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
103 #else
104 env->sregs[SR_MSR] = 0;
105 mmu_init(&env->mmu);
106 env->mmu.c_mmu = 3;
107 env->mmu.c_mmu_tlb_access = 3;
108 env->mmu.c_mmu_zones = 16;
109 #endif
110 }
111
112 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
113 {
114 CPUState *cs = CPU(dev);
115 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
116
117 cpu_reset(cs);
118 qemu_init_vcpu(cs);
119
120 mcc->parent_realize(dev, errp);
121 }
122
123 static void mb_cpu_initfn(Object *obj)
124 {
125 CPUState *cs = CPU(obj);
126 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
127 CPUMBState *env = &cpu->env;
128 static bool tcg_initialized;
129
130 cs->env_ptr = env;
131 cpu_exec_init(env);
132
133 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
134
135 #ifndef CONFIG_USER_ONLY
136 /* Inbound IRQ and FIR lines */
137 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
138 #endif
139
140 if (tcg_enabled() && !tcg_initialized) {
141 tcg_initialized = true;
142 mb_tcg_init();
143 }
144 }
145
146 static const VMStateDescription vmstate_mb_cpu = {
147 .name = "cpu",
148 .unmigratable = 1,
149 };
150
151 static Property mb_properties[] = {
152 DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
153 DEFINE_PROP_END_OF_LIST(),
154 };
155
156 static void mb_cpu_class_init(ObjectClass *oc, void *data)
157 {
158 DeviceClass *dc = DEVICE_CLASS(oc);
159 CPUClass *cc = CPU_CLASS(oc);
160 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
161
162 mcc->parent_realize = dc->realize;
163 dc->realize = mb_cpu_realizefn;
164
165 mcc->parent_reset = cc->reset;
166 cc->reset = mb_cpu_reset;
167
168 cc->has_work = mb_cpu_has_work;
169 cc->do_interrupt = mb_cpu_do_interrupt;
170 cc->dump_state = mb_cpu_dump_state;
171 cc->set_pc = mb_cpu_set_pc;
172 cc->gdb_read_register = mb_cpu_gdb_read_register;
173 cc->gdb_write_register = mb_cpu_gdb_write_register;
174 #ifdef CONFIG_USER_ONLY
175 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
176 #else
177 cc->do_unassigned_access = mb_cpu_unassigned_access;
178 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
179 #endif
180 dc->vmsd = &vmstate_mb_cpu;
181 dc->props = mb_properties;
182 cc->gdb_num_core_regs = 32 + 5;
183 }
184
185 static const TypeInfo mb_cpu_type_info = {
186 .name = TYPE_MICROBLAZE_CPU,
187 .parent = TYPE_CPU,
188 .instance_size = sizeof(MicroBlazeCPU),
189 .instance_init = mb_cpu_initfn,
190 .class_size = sizeof(MicroBlazeCPUClass),
191 .class_init = mb_cpu_class_init,
192 };
193
194 static void mb_cpu_register_types(void)
195 {
196 type_register_static(&mb_cpu_type_info);
197 }
198
199 type_init(mb_cpu_register_types)