trap signals for "-serial mon:stdio"
[qemu.git] / target-microblaze / cpu.c
1 /*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see
20 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 */
22
23 #include "cpu.h"
24 #include "qemu-common.h"
25 #include "hw/qdev-properties.h"
26 #include "migration/vmstate.h"
27
28
29 /* CPUClass::reset() */
30 static void mb_cpu_reset(CPUState *s)
31 {
32 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
33 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
34 CPUMBState *env = &cpu->env;
35
36 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
37 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
38 log_cpu_state(env, 0);
39 }
40
41 mcc->parent_reset(s);
42
43 memset(env, 0, offsetof(CPUMBState, breakpoints));
44 env->res_addr = RES_ADDR_NONE;
45 tlb_flush(env, 1);
46
47 /* Disable stack protector. */
48 env->shr = ~0;
49
50 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
51 | PVR0_USE_BARREL_MASK \
52 | PVR0_USE_DIV_MASK \
53 | PVR0_USE_HW_MUL_MASK \
54 | PVR0_USE_EXC_MASK \
55 | PVR0_USE_ICACHE_MASK \
56 | PVR0_USE_DCACHE_MASK \
57 | PVR0_USE_MMU \
58 | (0xb << 8);
59 env->pvr.regs[2] = PVR2_D_OPB_MASK \
60 | PVR2_D_LMB_MASK \
61 | PVR2_I_OPB_MASK \
62 | PVR2_I_LMB_MASK \
63 | PVR2_USE_MSR_INSTR \
64 | PVR2_USE_PCMP_INSTR \
65 | PVR2_USE_BARREL_MASK \
66 | PVR2_USE_DIV_MASK \
67 | PVR2_USE_HW_MUL_MASK \
68 | PVR2_USE_MUL64_MASK \
69 | PVR2_USE_FPU_MASK \
70 | PVR2_USE_FPU2_MASK \
71 | PVR2_FPU_EXC_MASK \
72 | 0;
73 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
74 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
75
76 #if defined(CONFIG_USER_ONLY)
77 /* start in user mode with interrupts enabled. */
78 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
79 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
80 #else
81 env->sregs[SR_MSR] = 0;
82 mmu_init(&env->mmu);
83 env->mmu.c_mmu = 3;
84 env->mmu.c_mmu_tlb_access = 3;
85 env->mmu.c_mmu_zones = 16;
86 #endif
87 }
88
89 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
90 {
91 MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
92 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
93
94 cpu_reset(CPU(cpu));
95
96 mcc->parent_realize(dev, errp);
97 }
98
99 static void mb_cpu_initfn(Object *obj)
100 {
101 CPUState *cs = CPU(obj);
102 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
103 CPUMBState *env = &cpu->env;
104 static bool tcg_initialized;
105
106 cs->env_ptr = env;
107 cpu_exec_init(env);
108
109 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
110
111 if (tcg_enabled() && !tcg_initialized) {
112 tcg_initialized = true;
113 mb_tcg_init();
114 }
115 }
116
117 static const VMStateDescription vmstate_mb_cpu = {
118 .name = "cpu",
119 .unmigratable = 1,
120 };
121
122 static Property mb_properties[] = {
123 DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
124 DEFINE_PROP_END_OF_LIST(),
125 };
126
127 static void mb_cpu_class_init(ObjectClass *oc, void *data)
128 {
129 DeviceClass *dc = DEVICE_CLASS(oc);
130 CPUClass *cc = CPU_CLASS(oc);
131 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
132
133 mcc->parent_realize = dc->realize;
134 dc->realize = mb_cpu_realizefn;
135
136 mcc->parent_reset = cc->reset;
137 cc->reset = mb_cpu_reset;
138
139 cc->do_interrupt = mb_cpu_do_interrupt;
140 cc->dump_state = mb_cpu_dump_state;
141 cpu_class_set_do_unassigned_access(cc, mb_cpu_unassigned_access);
142 dc->vmsd = &vmstate_mb_cpu;
143 dc->props = mb_properties;
144 }
145
146 static const TypeInfo mb_cpu_type_info = {
147 .name = TYPE_MICROBLAZE_CPU,
148 .parent = TYPE_CPU,
149 .instance_size = sizeof(MicroBlazeCPU),
150 .instance_init = mb_cpu_initfn,
151 .class_size = sizeof(MicroBlazeCPUClass),
152 .class_init = mb_cpu_class_init,
153 };
154
155 static void mb_cpu_register_types(void)
156 {
157 type_register_static(&mb_cpu_type_info);
158 }
159
160 type_init(mb_cpu_register_types)