vga: improve documentation
[qemu.git] / target-microblaze / cpu.h
1 /*
2 * MicroBlaze virtual CPU header
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_MICROBLAZE_H
20 #define CPU_MICROBLAZE_H
21
22 #define TARGET_LONG_BITS 32
23
24 #define CPUState struct CPUMBState
25
26 #include "cpu-defs.h"
27 #include "softfloat.h"
28 struct CPUMBState;
29 #if !defined(CONFIG_USER_ONLY)
30 #include "mmu.h"
31 #endif
32
33 #define TARGET_HAS_ICE 1
34
35 #define ELF_MACHINE EM_MICROBLAZE
36
37 #define EXCP_NMI 1
38 #define EXCP_MMU 2
39 #define EXCP_IRQ 3
40 #define EXCP_BREAK 4
41 #define EXCP_HW_BREAK 5
42 #define EXCP_HW_EXCP 6
43
44 /* MicroBlaze-specific interrupt pending bits. */
45 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
46
47 /* Register aliases. R0 - R15 */
48 #define R_SP 1
49 #define SR_PC 0
50 #define SR_MSR 1
51 #define SR_EAR 3
52 #define SR_ESR 5
53 #define SR_FSR 7
54 #define SR_BTR 0xb
55 #define SR_EDR 0xd
56
57 /* MSR flags. */
58 #define MSR_BE (1<<0) /* 0x001 */
59 #define MSR_IE (1<<1) /* 0x002 */
60 #define MSR_C (1<<2) /* 0x004 */
61 #define MSR_BIP (1<<3) /* 0x008 */
62 #define MSR_FSL (1<<4) /* 0x010 */
63 #define MSR_ICE (1<<5) /* 0x020 */
64 #define MSR_DZ (1<<6) /* 0x040 */
65 #define MSR_DCE (1<<7) /* 0x080 */
66 #define MSR_EE (1<<8) /* 0x100 */
67 #define MSR_EIP (1<<9) /* 0x200 */
68 #define MSR_PVR (1<<10) /* 0x400 */
69 #define MSR_CC (1<<31)
70
71 /* Machine State Register (MSR) Fields */
72 #define MSR_UM (1<<11) /* User Mode */
73 #define MSR_UMS (1<<12) /* User Mode Save */
74 #define MSR_VM (1<<13) /* Virtual Mode */
75 #define MSR_VMS (1<<14) /* Virtual Mode Save */
76
77 #define MSR_KERNEL MSR_EE|MSR_VM
78 //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
79 #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
80 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
81
82 /* Exception State Register (ESR) Fields */
83 #define ESR_DIZ (1<<11) /* Zone Protection */
84 #define ESR_S (1<<10) /* Store instruction */
85
86 #define ESR_ESS_FSL_OFFSET 5
87
88 #define ESR_EC_FSL 0
89 #define ESR_EC_UNALIGNED_DATA 1
90 #define ESR_EC_ILLEGAL_OP 2
91 #define ESR_EC_INSN_BUS 3
92 #define ESR_EC_DATA_BUS 4
93 #define ESR_EC_DIVZERO 5
94 #define ESR_EC_FPU 6
95 #define ESR_EC_PRIVINSN 7
96 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
97 #define ESR_EC_DATA_STORAGE 8
98 #define ESR_EC_INSN_STORAGE 9
99 #define ESR_EC_DATA_TLB 10
100 #define ESR_EC_INSN_TLB 11
101 #define ESR_EC_MASK 31
102
103 /* Floating Point Status Register (FSR) Bits */
104 #define FSR_IO (1<<4) /* Invalid operation */
105 #define FSR_DZ (1<<3) /* Divide-by-zero */
106 #define FSR_OF (1<<2) /* Overflow */
107 #define FSR_UF (1<<1) /* Underflow */
108 #define FSR_DO (1<<0) /* Denormalized operand error */
109
110 /* Version reg. */
111 /* Basic PVR mask */
112 #define PVR0_PVR_FULL_MASK 0x80000000
113 #define PVR0_USE_BARREL_MASK 0x40000000
114 #define PVR0_USE_DIV_MASK 0x20000000
115 #define PVR0_USE_HW_MUL_MASK 0x10000000
116 #define PVR0_USE_FPU_MASK 0x08000000
117 #define PVR0_USE_EXC_MASK 0x04000000
118 #define PVR0_USE_ICACHE_MASK 0x02000000
119 #define PVR0_USE_DCACHE_MASK 0x01000000
120 #define PVR0_USE_MMU 0x00800000 /* new */
121 #define PVR0_USE_BTC 0x00400000
122 #define PVR0_ENDI 0x00200000
123 #define PVR0_FAULT 0x00100000
124 #define PVR0_VERSION_MASK 0x0000FF00
125 #define PVR0_USER1_MASK 0x000000FF
126
127 /* User 2 PVR mask */
128 #define PVR1_USER2_MASK 0xFFFFFFFF
129
130 /* Configuration PVR masks */
131 #define PVR2_D_OPB_MASK 0x80000000
132 #define PVR2_D_LMB_MASK 0x40000000
133 #define PVR2_I_OPB_MASK 0x20000000
134 #define PVR2_I_LMB_MASK 0x10000000
135 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
136 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
137 #define PVR2_D_PLB_MASK 0x02000000 /* new */
138 #define PVR2_I_PLB_MASK 0x01000000 /* new */
139 #define PVR2_INTERCONNECT 0x00800000 /* new */
140 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
141 #define PVR2_USE_FSL_EXC 0x00040000 /* new */
142 #define PVR2_USE_MSR_INSTR 0x00020000
143 #define PVR2_USE_PCMP_INSTR 0x00010000
144 #define PVR2_AREA_OPTIMISED 0x00008000
145 #define PVR2_USE_BARREL_MASK 0x00004000
146 #define PVR2_USE_DIV_MASK 0x00002000
147 #define PVR2_USE_HW_MUL_MASK 0x00001000
148 #define PVR2_USE_FPU_MASK 0x00000800
149 #define PVR2_USE_MUL64_MASK 0x00000400
150 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
151 #define PVR2_USE_IPLBEXC 0x00000100
152 #define PVR2_USE_DPLBEXC 0x00000080
153 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
154 #define PVR2_UNALIGNED_EXC_MASK 0x00000020
155 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
156 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
157 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
158 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
159 #define PVR2_FPU_EXC_MASK 0x00000001
160
161 /* Debug and exception PVR masks */
162 #define PVR3_DEBUG_ENABLED_MASK 0x80000000
163 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
164 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
165 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
166 #define PVR3_FSL_LINKS_MASK 0x00000380
167
168 /* ICache config PVR masks */
169 #define PVR4_USE_ICACHE_MASK 0x80000000
170 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
171 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
172 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
173 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
174 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
175
176 /* DCache config PVR masks */
177 #define PVR5_USE_DCACHE_MASK 0x80000000
178 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
179 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
180 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
181 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
182 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
183 #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
184
185 /* ICache base address PVR mask */
186 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
187
188 /* ICache high address PVR mask */
189 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
190
191 /* DCache base address PVR mask */
192 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
193
194 /* DCache high address PVR mask */
195 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
196
197 /* Target family PVR mask */
198 #define PVR10_TARGET_FAMILY_MASK 0xFF000000
199
200 /* MMU descrtiption */
201 #define PVR11_USE_MMU 0xC0000000
202 #define PVR11_MMU_ITLB_SIZE 0x38000000
203 #define PVR11_MMU_DTLB_SIZE 0x07000000
204 #define PVR11_MMU_TLB_ACCESS 0x00C00000
205 #define PVR11_MMU_ZONES 0x003E0000
206 /* MSR Reset value PVR mask */
207 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
208
209
210
211 /* CPU flags. */
212
213 /* Condition codes. */
214 #define CC_GE 5
215 #define CC_GT 4
216 #define CC_LE 3
217 #define CC_LT 2
218 #define CC_NE 1
219 #define CC_EQ 0
220
221 #define NB_MMU_MODES 3
222
223 #define STREAM_EXCEPTION (1 << 0)
224 #define STREAM_ATOMIC (1 << 1)
225 #define STREAM_TEST (1 << 2)
226 #define STREAM_CONTROL (1 << 3)
227 #define STREAM_NONBLOCK (1 << 4)
228
229 typedef struct CPUMBState {
230 uint32_t debug;
231 uint32_t btaken;
232 uint32_t btarget;
233 uint32_t bimm;
234
235 uint32_t imm;
236 uint32_t regs[33];
237 uint32_t sregs[24];
238 float_status fp_status;
239 /* Stack protectors. Yes, it's a hw feature. */
240 uint32_t slr, shr;
241
242 /* Internal flags. */
243 #define IMM_FLAG 4
244 #define MSR_EE_FLAG (1 << 8)
245 #define DRTI_FLAG (1 << 16)
246 #define DRTE_FLAG (1 << 17)
247 #define DRTB_FLAG (1 << 18)
248 #define D_FLAG (1 << 19) /* Bit in ESR. */
249 /* TB dependent CPUState. */
250 #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
251 uint32_t iflags;
252
253 struct {
254 uint32_t regs[16];
255 } pvr;
256
257 #if !defined(CONFIG_USER_ONLY)
258 /* Unified MMU. */
259 struct microblaze_mmu mmu;
260 #endif
261
262 CPU_COMMON
263 } CPUMBState;
264
265 CPUState *cpu_mb_init(const char *cpu_model);
266 int cpu_mb_exec(CPUState *s);
267 void cpu_mb_close(CPUState *s);
268 void do_interrupt(CPUState *env);
269 /* you can call this signal handler from your SIGBUS and SIGSEGV
270 signal handlers to inform the virtual CPU of exceptions. non zero
271 is returned if the signal was handled by the virtual CPU. */
272 int cpu_mb_signal_handler(int host_signum, void *pinfo,
273 void *puc);
274
275 enum {
276 CC_OP_DYNAMIC, /* Use env->cc_op */
277 CC_OP_FLAGS,
278 CC_OP_CMP,
279 };
280
281 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
282 #define TARGET_PAGE_BITS 12
283 #define MMAP_SHIFT TARGET_PAGE_BITS
284
285 #define TARGET_PHYS_ADDR_SPACE_BITS 32
286 #define TARGET_VIRT_ADDR_SPACE_BITS 32
287
288 #define cpu_init cpu_mb_init
289 #define cpu_exec cpu_mb_exec
290 #define cpu_gen_code cpu_mb_gen_code
291 #define cpu_signal_handler cpu_mb_signal_handler
292
293 #define CPU_SAVE_VERSION 1
294
295 /* MMU modes definitions */
296 #define MMU_MODE0_SUFFIX _nommu
297 #define MMU_MODE1_SUFFIX _kernel
298 #define MMU_MODE2_SUFFIX _user
299 #define MMU_NOMMU_IDX 0
300 #define MMU_KERNEL_IDX 1
301 #define MMU_USER_IDX 2
302 /* See NB_MMU_MODES further up the file. */
303
304 static inline int cpu_mmu_index (CPUState *env)
305 {
306 /* Are we in nommu mode?. */
307 if (!(env->sregs[SR_MSR] & MSR_VM))
308 return MMU_NOMMU_IDX;
309
310 if (env->sregs[SR_MSR] & MSR_UM)
311 return MMU_USER_IDX;
312 return MMU_KERNEL_IDX;
313 }
314
315 int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
316 int mmu_idx);
317 #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
318
319 #if defined(CONFIG_USER_ONLY)
320 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
321 {
322 if (newsp)
323 env->regs[R_SP] = newsp;
324 env->regs[3] = 0;
325 }
326 #endif
327
328 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
329 {
330 }
331
332 static inline int cpu_interrupts_enabled(CPUState *env)
333 {
334 return env->sregs[SR_MSR] & MSR_IE;
335 }
336
337 #include "cpu-all.h"
338
339 static inline target_ulong cpu_get_pc(CPUState *env)
340 {
341 return env->sregs[SR_PC];
342 }
343
344 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
345 target_ulong *cs_base, int *flags)
346 {
347 *pc = env->sregs[SR_PC];
348 *cs_base = 0;
349 *flags = (env->iflags & IFLAGS_TB_MASK) |
350 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
351 }
352
353 #if !defined(CONFIG_USER_ONLY)
354 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
355 int is_write, int is_exec, int is_asi, int size);
356 #endif
357
358 static inline bool cpu_has_work(CPUState *env)
359 {
360 return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
361 }
362
363 #include "exec-all.h"
364
365 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
366 {
367 env->sregs[SR_PC] = tb->pc;
368 }
369
370 #endif