cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / target-microblaze / cpu.h
1 /*
2 * MicroBlaze virtual CPU header
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_MICROBLAZE_H
20 #define CPU_MICROBLAZE_H
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 #define TARGET_LONG_BITS 32
26
27 #define CPUArchState struct CPUMBState
28
29 #include "exec/cpu-defs.h"
30 #include "fpu/softfloat.h"
31 struct CPUMBState;
32 typedef struct CPUMBState CPUMBState;
33 #if !defined(CONFIG_USER_ONLY)
34 #include "mmu.h"
35 #endif
36
37 #define TARGET_HAS_ICE 1
38
39 #define ELF_MACHINE EM_MICROBLAZE
40
41 #define EXCP_NMI 1
42 #define EXCP_MMU 2
43 #define EXCP_IRQ 3
44 #define EXCP_BREAK 4
45 #define EXCP_HW_BREAK 5
46 #define EXCP_HW_EXCP 6
47
48 /* MicroBlaze-specific interrupt pending bits. */
49 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
50
51 /* Register aliases. R0 - R15 */
52 #define R_SP 1
53 #define SR_PC 0
54 #define SR_MSR 1
55 #define SR_EAR 3
56 #define SR_ESR 5
57 #define SR_FSR 7
58 #define SR_BTR 0xb
59 #define SR_EDR 0xd
60
61 /* MSR flags. */
62 #define MSR_BE (1<<0) /* 0x001 */
63 #define MSR_IE (1<<1) /* 0x002 */
64 #define MSR_C (1<<2) /* 0x004 */
65 #define MSR_BIP (1<<3) /* 0x008 */
66 #define MSR_FSL (1<<4) /* 0x010 */
67 #define MSR_ICE (1<<5) /* 0x020 */
68 #define MSR_DZ (1<<6) /* 0x040 */
69 #define MSR_DCE (1<<7) /* 0x080 */
70 #define MSR_EE (1<<8) /* 0x100 */
71 #define MSR_EIP (1<<9) /* 0x200 */
72 #define MSR_PVR (1<<10) /* 0x400 */
73 #define MSR_CC (1<<31)
74
75 /* Machine State Register (MSR) Fields */
76 #define MSR_UM (1<<11) /* User Mode */
77 #define MSR_UMS (1<<12) /* User Mode Save */
78 #define MSR_VM (1<<13) /* Virtual Mode */
79 #define MSR_VMS (1<<14) /* Virtual Mode Save */
80
81 #define MSR_KERNEL MSR_EE|MSR_VM
82 //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
83 #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
84 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
85
86 /* Exception State Register (ESR) Fields */
87 #define ESR_DIZ (1<<11) /* Zone Protection */
88 #define ESR_S (1<<10) /* Store instruction */
89
90 #define ESR_ESS_FSL_OFFSET 5
91
92 #define ESR_EC_FSL 0
93 #define ESR_EC_UNALIGNED_DATA 1
94 #define ESR_EC_ILLEGAL_OP 2
95 #define ESR_EC_INSN_BUS 3
96 #define ESR_EC_DATA_BUS 4
97 #define ESR_EC_DIVZERO 5
98 #define ESR_EC_FPU 6
99 #define ESR_EC_PRIVINSN 7
100 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
101 #define ESR_EC_DATA_STORAGE 8
102 #define ESR_EC_INSN_STORAGE 9
103 #define ESR_EC_DATA_TLB 10
104 #define ESR_EC_INSN_TLB 11
105 #define ESR_EC_MASK 31
106
107 /* Floating Point Status Register (FSR) Bits */
108 #define FSR_IO (1<<4) /* Invalid operation */
109 #define FSR_DZ (1<<3) /* Divide-by-zero */
110 #define FSR_OF (1<<2) /* Overflow */
111 #define FSR_UF (1<<1) /* Underflow */
112 #define FSR_DO (1<<0) /* Denormalized operand error */
113
114 /* Version reg. */
115 /* Basic PVR mask */
116 #define PVR0_PVR_FULL_MASK 0x80000000
117 #define PVR0_USE_BARREL_MASK 0x40000000
118 #define PVR0_USE_DIV_MASK 0x20000000
119 #define PVR0_USE_HW_MUL_MASK 0x10000000
120 #define PVR0_USE_FPU_MASK 0x08000000
121 #define PVR0_USE_EXC_MASK 0x04000000
122 #define PVR0_USE_ICACHE_MASK 0x02000000
123 #define PVR0_USE_DCACHE_MASK 0x01000000
124 #define PVR0_USE_MMU 0x00800000 /* new */
125 #define PVR0_USE_BTC 0x00400000
126 #define PVR0_ENDI 0x00200000
127 #define PVR0_FAULT 0x00100000
128 #define PVR0_VERSION_MASK 0x0000FF00
129 #define PVR0_USER1_MASK 0x000000FF
130
131 /* User 2 PVR mask */
132 #define PVR1_USER2_MASK 0xFFFFFFFF
133
134 /* Configuration PVR masks */
135 #define PVR2_D_OPB_MASK 0x80000000
136 #define PVR2_D_LMB_MASK 0x40000000
137 #define PVR2_I_OPB_MASK 0x20000000
138 #define PVR2_I_LMB_MASK 0x10000000
139 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
140 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
141 #define PVR2_D_PLB_MASK 0x02000000 /* new */
142 #define PVR2_I_PLB_MASK 0x01000000 /* new */
143 #define PVR2_INTERCONNECT 0x00800000 /* new */
144 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
145 #define PVR2_USE_FSL_EXC 0x00040000 /* new */
146 #define PVR2_USE_MSR_INSTR 0x00020000
147 #define PVR2_USE_PCMP_INSTR 0x00010000
148 #define PVR2_AREA_OPTIMISED 0x00008000
149 #define PVR2_USE_BARREL_MASK 0x00004000
150 #define PVR2_USE_DIV_MASK 0x00002000
151 #define PVR2_USE_HW_MUL_MASK 0x00001000
152 #define PVR2_USE_FPU_MASK 0x00000800
153 #define PVR2_USE_MUL64_MASK 0x00000400
154 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
155 #define PVR2_USE_IPLBEXC 0x00000100
156 #define PVR2_USE_DPLBEXC 0x00000080
157 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
158 #define PVR2_UNALIGNED_EXC_MASK 0x00000020
159 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
160 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
161 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
162 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
163 #define PVR2_FPU_EXC_MASK 0x00000001
164
165 /* Debug and exception PVR masks */
166 #define PVR3_DEBUG_ENABLED_MASK 0x80000000
167 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
168 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
169 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
170 #define PVR3_FSL_LINKS_MASK 0x00000380
171
172 /* ICache config PVR masks */
173 #define PVR4_USE_ICACHE_MASK 0x80000000
174 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
175 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
176 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
177 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
178 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
179
180 /* DCache config PVR masks */
181 #define PVR5_USE_DCACHE_MASK 0x80000000
182 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
183 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
184 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
185 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
186 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
187 #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
188
189 /* ICache base address PVR mask */
190 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
191
192 /* ICache high address PVR mask */
193 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
194
195 /* DCache base address PVR mask */
196 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
197
198 /* DCache high address PVR mask */
199 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
200
201 /* Target family PVR mask */
202 #define PVR10_TARGET_FAMILY_MASK 0xFF000000
203
204 /* MMU descrtiption */
205 #define PVR11_USE_MMU 0xC0000000
206 #define PVR11_MMU_ITLB_SIZE 0x38000000
207 #define PVR11_MMU_DTLB_SIZE 0x07000000
208 #define PVR11_MMU_TLB_ACCESS 0x00C00000
209 #define PVR11_MMU_ZONES 0x003E0000
210 /* MSR Reset value PVR mask */
211 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
212
213
214
215 /* CPU flags. */
216
217 /* Condition codes. */
218 #define CC_GE 5
219 #define CC_GT 4
220 #define CC_LE 3
221 #define CC_LT 2
222 #define CC_NE 1
223 #define CC_EQ 0
224
225 #define NB_MMU_MODES 3
226
227 #define STREAM_EXCEPTION (1 << 0)
228 #define STREAM_ATOMIC (1 << 1)
229 #define STREAM_TEST (1 << 2)
230 #define STREAM_CONTROL (1 << 3)
231 #define STREAM_NONBLOCK (1 << 4)
232
233 struct CPUMBState {
234 uint32_t debug;
235 uint32_t btaken;
236 uint32_t btarget;
237 uint32_t bimm;
238
239 uint32_t imm;
240 uint32_t regs[33];
241 uint32_t sregs[24];
242 float_status fp_status;
243 /* Stack protectors. Yes, it's a hw feature. */
244 uint32_t slr, shr;
245
246 /* lwx/swx reserved address */
247 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
248 uint32_t res_addr;
249
250 /* Internal flags. */
251 #define IMM_FLAG 4
252 #define MSR_EE_FLAG (1 << 8)
253 #define DRTI_FLAG (1 << 16)
254 #define DRTE_FLAG (1 << 17)
255 #define DRTB_FLAG (1 << 18)
256 #define D_FLAG (1 << 19) /* Bit in ESR. */
257 /* TB dependent CPUMBState. */
258 #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
259 uint32_t iflags;
260
261 struct {
262 uint32_t regs[16];
263 } pvr;
264
265 #if !defined(CONFIG_USER_ONLY)
266 /* Unified MMU. */
267 struct microblaze_mmu mmu;
268 #endif
269
270 CPU_COMMON
271 };
272
273 #include "cpu-qom.h"
274
275 void mb_tcg_init(void);
276 MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
277 int cpu_mb_exec(CPUMBState *s);
278 void do_interrupt(CPUMBState *env);
279 /* you can call this signal handler from your SIGBUS and SIGSEGV
280 signal handlers to inform the virtual CPU of exceptions. non zero
281 is returned if the signal was handled by the virtual CPU. */
282 int cpu_mb_signal_handler(int host_signum, void *pinfo,
283 void *puc);
284
285 enum {
286 CC_OP_DYNAMIC, /* Use env->cc_op */
287 CC_OP_FLAGS,
288 CC_OP_CMP,
289 };
290
291 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
292 #define TARGET_PAGE_BITS 12
293 #define MMAP_SHIFT TARGET_PAGE_BITS
294
295 #define TARGET_PHYS_ADDR_SPACE_BITS 32
296 #define TARGET_VIRT_ADDR_SPACE_BITS 32
297
298 static inline CPUMBState *cpu_init(const char *cpu_model)
299 {
300 MicroBlazeCPU *cpu = cpu_mb_init(cpu_model);
301 if (cpu == NULL) {
302 return NULL;
303 }
304 return &cpu->env;
305 }
306
307 #define cpu_exec cpu_mb_exec
308 #define cpu_gen_code cpu_mb_gen_code
309 #define cpu_signal_handler cpu_mb_signal_handler
310
311 /* MMU modes definitions */
312 #define MMU_MODE0_SUFFIX _nommu
313 #define MMU_MODE1_SUFFIX _kernel
314 #define MMU_MODE2_SUFFIX _user
315 #define MMU_NOMMU_IDX 0
316 #define MMU_KERNEL_IDX 1
317 #define MMU_USER_IDX 2
318 /* See NB_MMU_MODES further up the file. */
319
320 static inline int cpu_mmu_index (CPUMBState *env)
321 {
322 /* Are we in nommu mode?. */
323 if (!(env->sregs[SR_MSR] & MSR_VM))
324 return MMU_NOMMU_IDX;
325
326 if (env->sregs[SR_MSR] & MSR_UM)
327 return MMU_USER_IDX;
328 return MMU_KERNEL_IDX;
329 }
330
331 int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
332 int mmu_idx);
333 #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
334
335 #if defined(CONFIG_USER_ONLY)
336 static inline void cpu_clone_regs(CPUMBState *env, target_ulong newsp)
337 {
338 if (newsp)
339 env->regs[R_SP] = newsp;
340 env->regs[3] = 0;
341 }
342 #endif
343
344 static inline void cpu_set_tls(CPUMBState *env, target_ulong newtls)
345 {
346 env->regs[21] = newtls;
347 }
348
349 static inline int cpu_interrupts_enabled(CPUMBState *env)
350 {
351 return env->sregs[SR_MSR] & MSR_IE;
352 }
353
354 #include "exec/cpu-all.h"
355
356 static inline target_ulong cpu_get_pc(CPUMBState *env)
357 {
358 return env->sregs[SR_PC];
359 }
360
361 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
362 target_ulong *cs_base, int *flags)
363 {
364 *pc = env->sregs[SR_PC];
365 *cs_base = 0;
366 *flags = (env->iflags & IFLAGS_TB_MASK) |
367 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
368 }
369
370 #if !defined(CONFIG_USER_ONLY)
371 void cpu_unassigned_access(CPUMBState *env1, hwaddr addr,
372 int is_write, int is_exec, int is_asi, int size);
373 #endif
374
375 static inline bool cpu_has_work(CPUState *cpu)
376 {
377 return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
378 }
379
380 #include "exec/exec-all.h"
381
382 static inline void cpu_pc_from_tb(CPUMBState *env, TranslationBlock *tb)
383 {
384 env->sregs[SR_PC] = tb->pc;
385 }
386
387 #endif