vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-microblaze / cpu.h
1 /*
2 * MicroBlaze virtual CPU header
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_MICROBLAZE_H
20 #define CPU_MICROBLAZE_H
21
22 #include "qemu-common.h"
23 #include "cpu-qom.h"
24
25 #define TARGET_LONG_BITS 32
26
27 #define CPUArchState struct CPUMBState
28
29 #include "exec/cpu-defs.h"
30 #include "fpu/softfloat.h"
31 struct CPUMBState;
32 typedef struct CPUMBState CPUMBState;
33 #if !defined(CONFIG_USER_ONLY)
34 #include "mmu.h"
35 #endif
36
37 #define EXCP_MMU 1
38 #define EXCP_IRQ 2
39 #define EXCP_BREAK 3
40 #define EXCP_HW_BREAK 4
41 #define EXCP_HW_EXCP 5
42
43 /* MicroBlaze-specific interrupt pending bits. */
44 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
45
46 /* Meanings of the MBCPU object's two inbound GPIO lines */
47 #define MB_CPU_IRQ 0
48 #define MB_CPU_FIR 1
49
50 /* Register aliases. R0 - R15 */
51 #define R_SP 1
52 #define SR_PC 0
53 #define SR_MSR 1
54 #define SR_EAR 3
55 #define SR_ESR 5
56 #define SR_FSR 7
57 #define SR_BTR 0xb
58 #define SR_EDR 0xd
59
60 /* MSR flags. */
61 #define MSR_BE (1<<0) /* 0x001 */
62 #define MSR_IE (1<<1) /* 0x002 */
63 #define MSR_C (1<<2) /* 0x004 */
64 #define MSR_BIP (1<<3) /* 0x008 */
65 #define MSR_FSL (1<<4) /* 0x010 */
66 #define MSR_ICE (1<<5) /* 0x020 */
67 #define MSR_DZ (1<<6) /* 0x040 */
68 #define MSR_DCE (1<<7) /* 0x080 */
69 #define MSR_EE (1<<8) /* 0x100 */
70 #define MSR_EIP (1<<9) /* 0x200 */
71 #define MSR_PVR (1<<10) /* 0x400 */
72 #define MSR_CC (1<<31)
73
74 /* Machine State Register (MSR) Fields */
75 #define MSR_UM (1<<11) /* User Mode */
76 #define MSR_UMS (1<<12) /* User Mode Save */
77 #define MSR_VM (1<<13) /* Virtual Mode */
78 #define MSR_VMS (1<<14) /* Virtual Mode Save */
79
80 #define MSR_KERNEL MSR_EE|MSR_VM
81 //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
82 #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
83 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
84
85 /* Exception State Register (ESR) Fields */
86 #define ESR_DIZ (1<<11) /* Zone Protection */
87 #define ESR_S (1<<10) /* Store instruction */
88
89 #define ESR_ESS_FSL_OFFSET 5
90
91 #define ESR_EC_FSL 0
92 #define ESR_EC_UNALIGNED_DATA 1
93 #define ESR_EC_ILLEGAL_OP 2
94 #define ESR_EC_INSN_BUS 3
95 #define ESR_EC_DATA_BUS 4
96 #define ESR_EC_DIVZERO 5
97 #define ESR_EC_FPU 6
98 #define ESR_EC_PRIVINSN 7
99 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
100 #define ESR_EC_DATA_STORAGE 8
101 #define ESR_EC_INSN_STORAGE 9
102 #define ESR_EC_DATA_TLB 10
103 #define ESR_EC_INSN_TLB 11
104 #define ESR_EC_MASK 31
105
106 /* Floating Point Status Register (FSR) Bits */
107 #define FSR_IO (1<<4) /* Invalid operation */
108 #define FSR_DZ (1<<3) /* Divide-by-zero */
109 #define FSR_OF (1<<2) /* Overflow */
110 #define FSR_UF (1<<1) /* Underflow */
111 #define FSR_DO (1<<0) /* Denormalized operand error */
112
113 /* Version reg. */
114 /* Basic PVR mask */
115 #define PVR0_PVR_FULL_MASK 0x80000000
116 #define PVR0_USE_BARREL_MASK 0x40000000
117 #define PVR0_USE_DIV_MASK 0x20000000
118 #define PVR0_USE_HW_MUL_MASK 0x10000000
119 #define PVR0_USE_FPU_MASK 0x08000000
120 #define PVR0_USE_EXC_MASK 0x04000000
121 #define PVR0_USE_ICACHE_MASK 0x02000000
122 #define PVR0_USE_DCACHE_MASK 0x01000000
123 #define PVR0_USE_MMU_MASK 0x00800000
124 #define PVR0_USE_BTC 0x00400000
125 #define PVR0_ENDI_MASK 0x00200000
126 #define PVR0_FAULT 0x00100000
127 #define PVR0_VERSION_MASK 0x0000FF00
128 #define PVR0_USER1_MASK 0x000000FF
129 #define PVR0_SPROT_MASK 0x00000001
130
131 /* User 2 PVR mask */
132 #define PVR1_USER2_MASK 0xFFFFFFFF
133
134 /* Configuration PVR masks */
135 #define PVR2_D_OPB_MASK 0x80000000
136 #define PVR2_D_LMB_MASK 0x40000000
137 #define PVR2_I_OPB_MASK 0x20000000
138 #define PVR2_I_LMB_MASK 0x10000000
139 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
140 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
141 #define PVR2_D_PLB_MASK 0x02000000 /* new */
142 #define PVR2_I_PLB_MASK 0x01000000 /* new */
143 #define PVR2_INTERCONNECT 0x00800000 /* new */
144 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
145 #define PVR2_USE_FSL_EXC 0x00040000 /* new */
146 #define PVR2_USE_MSR_INSTR 0x00020000
147 #define PVR2_USE_PCMP_INSTR 0x00010000
148 #define PVR2_AREA_OPTIMISED 0x00008000
149 #define PVR2_USE_BARREL_MASK 0x00004000
150 #define PVR2_USE_DIV_MASK 0x00002000
151 #define PVR2_USE_HW_MUL_MASK 0x00001000
152 #define PVR2_USE_FPU_MASK 0x00000800
153 #define PVR2_USE_MUL64_MASK 0x00000400
154 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */
155 #define PVR2_USE_IPLBEXC 0x00000100
156 #define PVR2_USE_DPLBEXC 0x00000080
157 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
158 #define PVR2_UNALIGNED_EXC_MASK 0x00000020
159 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
160 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008
161 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004
162 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002
163 #define PVR2_FPU_EXC_MASK 0x00000001
164
165 /* Debug and exception PVR masks */
166 #define PVR3_DEBUG_ENABLED_MASK 0x80000000
167 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
168 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
169 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
170 #define PVR3_FSL_LINKS_MASK 0x00000380
171
172 /* ICache config PVR masks */
173 #define PVR4_USE_ICACHE_MASK 0x80000000
174 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
175 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000
176 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
177 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
178 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
179
180 /* DCache config PVR masks */
181 #define PVR5_USE_DCACHE_MASK 0x80000000
182 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
183 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000
184 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
185 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
186 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
187 #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
188
189 /* ICache base address PVR mask */
190 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
191
192 /* ICache high address PVR mask */
193 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
194
195 /* DCache base address PVR mask */
196 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
197
198 /* DCache high address PVR mask */
199 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
200
201 /* Target family PVR mask */
202 #define PVR10_TARGET_FAMILY_MASK 0xFF000000
203
204 /* MMU descrtiption */
205 #define PVR11_USE_MMU 0xC0000000
206 #define PVR11_MMU_ITLB_SIZE 0x38000000
207 #define PVR11_MMU_DTLB_SIZE 0x07000000
208 #define PVR11_MMU_TLB_ACCESS 0x00C00000
209 #define PVR11_MMU_ZONES 0x003E0000
210 /* MSR Reset value PVR mask */
211 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
212
213 #define C_PVR_NONE 0
214 #define C_PVR_BASIC 1
215 #define C_PVR_FULL 2
216
217 /* CPU flags. */
218
219 /* Condition codes. */
220 #define CC_GE 5
221 #define CC_GT 4
222 #define CC_LE 3
223 #define CC_LT 2
224 #define CC_NE 1
225 #define CC_EQ 0
226
227 #define NB_MMU_MODES 3
228
229 #define STREAM_EXCEPTION (1 << 0)
230 #define STREAM_ATOMIC (1 << 1)
231 #define STREAM_TEST (1 << 2)
232 #define STREAM_CONTROL (1 << 3)
233 #define STREAM_NONBLOCK (1 << 4)
234
235 struct CPUMBState {
236 uint32_t debug;
237 uint32_t btaken;
238 uint32_t btarget;
239 uint32_t bimm;
240
241 uint32_t imm;
242 uint32_t regs[33];
243 uint32_t sregs[24];
244 float_status fp_status;
245 /* Stack protectors. Yes, it's a hw feature. */
246 uint32_t slr, shr;
247
248 /* lwx/swx reserved address */
249 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
250 uint32_t res_addr;
251 uint32_t res_val;
252
253 /* Internal flags. */
254 #define IMM_FLAG 4
255 #define MSR_EE_FLAG (1 << 8)
256 #define DRTI_FLAG (1 << 16)
257 #define DRTE_FLAG (1 << 17)
258 #define DRTB_FLAG (1 << 18)
259 #define D_FLAG (1 << 19) /* Bit in ESR. */
260 /* TB dependent CPUMBState. */
261 #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
262 uint32_t iflags;
263
264 #if !defined(CONFIG_USER_ONLY)
265 /* Unified MMU. */
266 struct microblaze_mmu mmu;
267 #endif
268
269 CPU_COMMON
270
271 /* These fields are preserved on reset. */
272
273 struct {
274 uint32_t regs[16];
275 } pvr;
276 };
277
278 /**
279 * MicroBlazeCPU:
280 * @env: #CPUMBState
281 *
282 * A MicroBlaze CPU.
283 */
284 struct MicroBlazeCPU {
285 /*< private >*/
286 CPUState parent_obj;
287
288 /*< public >*/
289
290 /* Microblaze Configuration Settings */
291 struct {
292 bool stackprot;
293 uint32_t base_vectors;
294 uint8_t use_fpu;
295 bool use_mmu;
296 bool dcache_writeback;
297 bool endi;
298 char *version;
299 uint8_t pvr;
300 } cfg;
301
302 CPUMBState env;
303 };
304
305 static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
306 {
307 return container_of(env, MicroBlazeCPU, env);
308 }
309
310 #define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
311
312 #define ENV_OFFSET offsetof(MicroBlazeCPU, env)
313
314 void mb_cpu_do_interrupt(CPUState *cs);
315 bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
316 void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
317 int flags);
318 hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
319 int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
320 int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
321
322 void mb_tcg_init(void);
323 MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
324 int cpu_mb_exec(CPUState *cpu);
325 /* you can call this signal handler from your SIGBUS and SIGSEGV
326 signal handlers to inform the virtual CPU of exceptions. non zero
327 is returned if the signal was handled by the virtual CPU. */
328 int cpu_mb_signal_handler(int host_signum, void *pinfo,
329 void *puc);
330
331 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
332 #define TARGET_PAGE_BITS 12
333
334 #define TARGET_PHYS_ADDR_SPACE_BITS 32
335 #define TARGET_VIRT_ADDR_SPACE_BITS 32
336
337 #define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
338
339 #define cpu_exec cpu_mb_exec
340 #define cpu_signal_handler cpu_mb_signal_handler
341
342 /* MMU modes definitions */
343 #define MMU_MODE0_SUFFIX _nommu
344 #define MMU_MODE1_SUFFIX _kernel
345 #define MMU_MODE2_SUFFIX _user
346 #define MMU_NOMMU_IDX 0
347 #define MMU_KERNEL_IDX 1
348 #define MMU_USER_IDX 2
349 /* See NB_MMU_MODES further up the file. */
350
351 static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
352 {
353 /* Are we in nommu mode?. */
354 if (!(env->sregs[SR_MSR] & MSR_VM))
355 return MMU_NOMMU_IDX;
356
357 if (env->sregs[SR_MSR] & MSR_UM)
358 return MMU_USER_IDX;
359 return MMU_KERNEL_IDX;
360 }
361
362 int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
363 int mmu_idx);
364
365 #include "exec/cpu-all.h"
366
367 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
368 target_ulong *cs_base, uint32_t *flags)
369 {
370 *pc = env->sregs[SR_PC];
371 *cs_base = 0;
372 *flags = (env->iflags & IFLAGS_TB_MASK) |
373 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
374 }
375
376 #if !defined(CONFIG_USER_ONLY)
377 void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
378 bool is_write, bool is_exec, int is_asi,
379 unsigned size);
380 #endif
381
382 #endif