trap signals for "-serial mon:stdio"
[qemu.git] / target-microblaze / helper.c
1 /*
2 * MicroBlaze helper routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "qemu/host-utils.h"
23
24 #define D(x)
25 #define DMMU(x)
26
27 #if defined(CONFIG_USER_ONLY)
28
29 void mb_cpu_do_interrupt(CPUState *cs)
30 {
31 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
32 CPUMBState *env = &cpu->env;
33
34 env->exception_index = -1;
35 env->res_addr = RES_ADDR_NONE;
36 env->regs[14] = env->sregs[SR_PC];
37 }
38
39 int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
40 int mmu_idx)
41 {
42 MicroBlazeCPU *cpu = mb_env_get_cpu(env);
43
44 env->exception_index = 0xaa;
45 cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
46 return 1;
47 }
48
49 #else /* !CONFIG_USER_ONLY */
50
51 int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
52 int mmu_idx)
53 {
54 unsigned int hit;
55 unsigned int mmu_available;
56 int r = 1;
57 int prot;
58
59 mmu_available = 0;
60 if (env->pvr.regs[0] & PVR0_USE_MMU) {
61 mmu_available = 1;
62 if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
63 && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
64 mmu_available = 0;
65 }
66 }
67
68 /* Translate if the MMU is available and enabled. */
69 if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
70 target_ulong vaddr, paddr;
71 struct microblaze_mmu_lookup lu;
72
73 hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
74 if (hit) {
75 vaddr = address & TARGET_PAGE_MASK;
76 paddr = lu.paddr + vaddr - lu.vaddr;
77
78 DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
79 mmu_idx, vaddr, paddr, lu.prot));
80 tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
81 r = 0;
82 } else {
83 env->sregs[SR_EAR] = address;
84 DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
85
86 switch (lu.err) {
87 case ERR_PROT:
88 env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
89 env->sregs[SR_ESR] |= (rw == 1) << 10;
90 break;
91 case ERR_MISS:
92 env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
93 env->sregs[SR_ESR] |= (rw == 1) << 10;
94 break;
95 default:
96 abort();
97 break;
98 }
99
100 if (env->exception_index == EXCP_MMU) {
101 cpu_abort(env, "recursive faults\n");
102 }
103
104 /* TLB miss. */
105 env->exception_index = EXCP_MMU;
106 }
107 } else {
108 /* MMU disabled or not available. */
109 address &= TARGET_PAGE_MASK;
110 prot = PAGE_BITS;
111 tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
112 r = 0;
113 }
114 return r;
115 }
116
117 void mb_cpu_do_interrupt(CPUState *cs)
118 {
119 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
120 CPUMBState *env = &cpu->env;
121 uint32_t t;
122
123 /* IMM flag cannot propagate across a branch and into the dslot. */
124 assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
125 assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
126 /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
127 env->res_addr = RES_ADDR_NONE;
128 switch (env->exception_index) {
129 case EXCP_HW_EXCP:
130 if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
131 qemu_log("Exception raised on system without exceptions!\n");
132 return;
133 }
134
135 env->regs[17] = env->sregs[SR_PC] + 4;
136 env->sregs[SR_ESR] &= ~(1 << 12);
137
138 /* Exception breaks branch + dslot sequence? */
139 if (env->iflags & D_FLAG) {
140 env->sregs[SR_ESR] |= 1 << 12 ;
141 env->sregs[SR_BTR] = env->btarget;
142 }
143
144 /* Disable the MMU. */
145 t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
146 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
147 env->sregs[SR_MSR] |= t;
148 /* Exception in progress. */
149 env->sregs[SR_MSR] |= MSR_EIP;
150
151 qemu_log_mask(CPU_LOG_INT,
152 "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
153 env->sregs[SR_PC], env->sregs[SR_EAR],
154 env->sregs[SR_ESR], env->iflags);
155 log_cpu_state_mask(CPU_LOG_INT, env, 0);
156 env->iflags &= ~(IMM_FLAG | D_FLAG);
157 env->sregs[SR_PC] = cpu->base_vectors + 0x20;
158 break;
159
160 case EXCP_MMU:
161 env->regs[17] = env->sregs[SR_PC];
162
163 env->sregs[SR_ESR] &= ~(1 << 12);
164 /* Exception breaks branch + dslot sequence? */
165 if (env->iflags & D_FLAG) {
166 D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
167 env->sregs[SR_ESR] |= 1 << 12 ;
168 env->sregs[SR_BTR] = env->btarget;
169
170 /* Reexecute the branch. */
171 env->regs[17] -= 4;
172 /* was the branch immprefixed?. */
173 if (env->bimm) {
174 qemu_log_mask(CPU_LOG_INT,
175 "bimm exception at pc=%x iflags=%x\n",
176 env->sregs[SR_PC], env->iflags);
177 env->regs[17] -= 4;
178 log_cpu_state_mask(CPU_LOG_INT, env, 0);
179 }
180 } else if (env->iflags & IMM_FLAG) {
181 D(qemu_log("IMM_FLAG set at exception\n"));
182 env->regs[17] -= 4;
183 }
184
185 /* Disable the MMU. */
186 t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
187 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
188 env->sregs[SR_MSR] |= t;
189 /* Exception in progress. */
190 env->sregs[SR_MSR] |= MSR_EIP;
191
192 qemu_log_mask(CPU_LOG_INT,
193 "exception at pc=%x ear=%x iflags=%x\n",
194 env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
195 log_cpu_state_mask(CPU_LOG_INT, env, 0);
196 env->iflags &= ~(IMM_FLAG | D_FLAG);
197 env->sregs[SR_PC] = cpu->base_vectors + 0x20;
198 break;
199
200 case EXCP_IRQ:
201 assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
202 assert(env->sregs[SR_MSR] & MSR_IE);
203 assert(!(env->iflags & D_FLAG));
204
205 t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
206
207 #if 0
208 #include "disas/disas.h"
209
210 /* Useful instrumentation when debugging interrupt issues in either
211 the models or in sw. */
212 {
213 const char *sym;
214
215 sym = lookup_symbol(env->sregs[SR_PC]);
216 if (sym
217 && (!strcmp("netif_rx", sym)
218 || !strcmp("process_backlog", sym))) {
219
220 qemu_log(
221 "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
222 env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
223 sym);
224
225 log_cpu_state(env, 0);
226 }
227 }
228 #endif
229 qemu_log_mask(CPU_LOG_INT,
230 "interrupt at pc=%x msr=%x %x iflags=%x\n",
231 env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
232
233 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
234 | MSR_UM | MSR_IE);
235 env->sregs[SR_MSR] |= t;
236
237 env->regs[14] = env->sregs[SR_PC];
238 env->sregs[SR_PC] = cpu->base_vectors + 0x10;
239 //log_cpu_state_mask(CPU_LOG_INT, env, 0);
240 break;
241
242 case EXCP_BREAK:
243 case EXCP_HW_BREAK:
244 assert(!(env->iflags & IMM_FLAG));
245 assert(!(env->iflags & D_FLAG));
246 t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
247 qemu_log_mask(CPU_LOG_INT,
248 "break at pc=%x msr=%x %x iflags=%x\n",
249 env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
250 log_cpu_state_mask(CPU_LOG_INT, env, 0);
251 env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
252 env->sregs[SR_MSR] |= t;
253 env->sregs[SR_MSR] |= MSR_BIP;
254 if (env->exception_index == EXCP_HW_BREAK) {
255 env->regs[16] = env->sregs[SR_PC];
256 env->sregs[SR_MSR] |= MSR_BIP;
257 env->sregs[SR_PC] = cpu->base_vectors + 0x18;
258 } else
259 env->sregs[SR_PC] = env->btarget;
260 break;
261 default:
262 cpu_abort(env, "unhandled exception type=%d\n",
263 env->exception_index);
264 break;
265 }
266 }
267
268 hwaddr cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
269 {
270 target_ulong vaddr, paddr = 0;
271 struct microblaze_mmu_lookup lu;
272 unsigned int hit;
273
274 if (env->sregs[SR_MSR] & MSR_VM) {
275 hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
276 if (hit) {
277 vaddr = addr & TARGET_PAGE_MASK;
278 paddr = lu.paddr + vaddr - lu.vaddr;
279 } else
280 paddr = 0; /* ???. */
281 } else
282 paddr = addr & TARGET_PAGE_MASK;
283
284 return paddr;
285 }
286 #endif