block: User BdrvChild callback for device name
[qemu.git] / target-microblaze / mmu.c
1 /*
2 * Microblaze MMU emulation for qemu.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23
24 #define D(x)
25
26 static unsigned int tlb_decode_size(unsigned int f)
27 {
28 static const unsigned int sizes[] = {
29 1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
30 1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
31 };
32 assert(f < ARRAY_SIZE(sizes));
33 return sizes[f];
34 }
35
36 static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
37 {
38 CPUState *cs = CPU(mb_env_get_cpu(env));
39 struct microblaze_mmu *mmu = &env->mmu;
40 unsigned int tlb_size;
41 uint32_t tlb_tag, end, t;
42
43 t = mmu->rams[RAM_TAG][idx];
44 if (!(t & TLB_VALID))
45 return;
46
47 tlb_tag = t & TLB_EPN_MASK;
48 tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
49 end = tlb_tag + tlb_size;
50
51 while (tlb_tag < end) {
52 tlb_flush_page(cs, tlb_tag);
53 tlb_tag += TARGET_PAGE_SIZE;
54 }
55 }
56
57 static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
58 {
59 struct microblaze_mmu *mmu = &env->mmu;
60 unsigned int i;
61 uint32_t t;
62
63 if (newpid & ~0xff)
64 qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
65
66 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
67 /* Lookup and decode. */
68 t = mmu->rams[RAM_TAG][i];
69 if (t & TLB_VALID) {
70 if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
71 mmu_flush_idx(env, i);
72 }
73 }
74 }
75
76 /* rw - 0 = read, 1 = write, 2 = fetch. */
77 unsigned int mmu_translate(struct microblaze_mmu *mmu,
78 struct microblaze_mmu_lookup *lu,
79 target_ulong vaddr, int rw, int mmu_idx)
80 {
81 unsigned int i, hit = 0;
82 unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
83 unsigned int tlb_size;
84 uint32_t tlb_tag, tlb_rpn, mask, t0;
85
86 lu->err = ERR_MISS;
87 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
88 uint32_t t, d;
89
90 /* Lookup and decode. */
91 t = mmu->rams[RAM_TAG][i];
92 D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
93 if (t & TLB_VALID) {
94 tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
95 if (tlb_size < TARGET_PAGE_SIZE) {
96 qemu_log("%d pages not supported\n", tlb_size);
97 abort();
98 }
99
100 mask = ~(tlb_size - 1);
101 tlb_tag = t & TLB_EPN_MASK;
102 if ((vaddr & mask) != (tlb_tag & mask)) {
103 D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
104 i, vaddr & mask, tlb_tag & mask));
105 continue;
106 }
107 if (mmu->tids[i]
108 && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
109 D(qemu_log("TLB %d pid=%x != tid=%x\n",
110 i, mmu->regs[MMU_R_PID], mmu->tids[i]));
111 continue;
112 }
113
114 /* Bring in the data part. */
115 d = mmu->rams[RAM_DATA][i];
116 tlb_ex = d & TLB_EX;
117 tlb_wr = d & TLB_WR;
118
119 /* Now let's see if there is a zone that overrides the protbits. */
120 tlb_zsel = (d >> 4) & 0xf;
121 t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
122 t0 &= 0x3;
123
124 if (tlb_zsel > mmu->c_mmu_zones) {
125 qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel);
126 t0 = 1; /* Ignore. */
127 }
128
129 if (mmu->c_mmu == 1) {
130 t0 = 1; /* Zones are disabled. */
131 }
132
133 switch (t0) {
134 case 0:
135 if (mmu_idx == MMU_USER_IDX)
136 continue;
137 break;
138 case 2:
139 if (mmu_idx != MMU_USER_IDX) {
140 tlb_ex = 1;
141 tlb_wr = 1;
142 }
143 break;
144 case 3:
145 tlb_ex = 1;
146 tlb_wr = 1;
147 break;
148 default: break;
149 }
150
151 lu->err = ERR_PROT;
152 lu->prot = PAGE_READ;
153 if (tlb_wr)
154 lu->prot |= PAGE_WRITE;
155 else if (rw == 1)
156 goto done;
157 if (tlb_ex)
158 lu->prot |=PAGE_EXEC;
159 else if (rw == 2) {
160 goto done;
161 }
162
163 tlb_rpn = d & TLB_RPN_MASK;
164
165 lu->vaddr = tlb_tag;
166 lu->paddr = tlb_rpn;
167 lu->size = tlb_size;
168 lu->err = ERR_HIT;
169 lu->idx = i;
170 hit = 1;
171 goto done;
172 }
173 }
174 done:
175 D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
176 vaddr, rw, tlb_wr, tlb_ex, hit));
177 return hit;
178 }
179
180 /* Writes/reads to the MMU's special regs end up here. */
181 uint32_t mmu_read(CPUMBState *env, uint32_t rn)
182 {
183 unsigned int i;
184 uint32_t r;
185
186 if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
187 qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
188 return 0;
189 }
190
191 switch (rn) {
192 /* Reads to HI/LO trig reads from the mmu rams. */
193 case MMU_R_TLBLO:
194 case MMU_R_TLBHI:
195 if (!(env->mmu.c_mmu_tlb_access & 1)) {
196 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
197 return 0;
198 }
199
200 i = env->mmu.regs[MMU_R_TLBX] & 0xff;
201 r = env->mmu.rams[rn & 1][i];
202 if (rn == MMU_R_TLBHI)
203 env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
204 break;
205 case MMU_R_PID:
206 case MMU_R_ZPR:
207 if (!(env->mmu.c_mmu_tlb_access & 1)) {
208 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
209 return 0;
210 }
211 r = env->mmu.regs[rn];
212 break;
213 default:
214 r = env->mmu.regs[rn];
215 break;
216 }
217 D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
218 return r;
219 }
220
221 void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
222 {
223 MicroBlazeCPU *cpu = mb_env_get_cpu(env);
224 unsigned int i;
225 D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
226
227 if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
228 qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
229 return;
230 }
231
232 switch (rn) {
233 /* Writes to HI/LO trig writes to the mmu rams. */
234 case MMU_R_TLBLO:
235 case MMU_R_TLBHI:
236 i = env->mmu.regs[MMU_R_TLBX] & 0xff;
237 if (rn == MMU_R_TLBHI) {
238 if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
239 qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n",
240 i, env->sregs[SR_PC]);
241 env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
242 mmu_flush_idx(env, i);
243 }
244 env->mmu.rams[rn & 1][i] = v;
245
246 D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
247 break;
248 case MMU_R_ZPR:
249 if (env->mmu.c_mmu_tlb_access <= 1) {
250 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
251 return;
252 }
253
254 /* Changes to the zone protection reg flush the QEMU TLB.
255 Fortunately, these are very uncommon. */
256 if (v != env->mmu.regs[rn]) {
257 tlb_flush(CPU(cpu), 1);
258 }
259 env->mmu.regs[rn] = v;
260 break;
261 case MMU_R_PID:
262 if (env->mmu.c_mmu_tlb_access <= 1) {
263 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
264 return;
265 }
266
267 if (v != env->mmu.regs[rn]) {
268 mmu_change_pid(env, v);
269 env->mmu.regs[rn] = v;
270 }
271 break;
272 case MMU_R_TLBSX:
273 {
274 struct microblaze_mmu_lookup lu;
275 int hit;
276
277 if (env->mmu.c_mmu_tlb_access <= 1) {
278 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
279 return;
280 }
281
282 hit = mmu_translate(&env->mmu, &lu,
283 v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
284 if (hit) {
285 env->mmu.regs[MMU_R_TLBX] = lu.idx;
286 } else
287 env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
288 break;
289 }
290 default:
291 env->mmu.regs[rn] = v;
292 break;
293 }
294 }
295
296 void mmu_init(struct microblaze_mmu *mmu)
297 {
298 int i;
299 for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
300 mmu->regs[i] = 0;
301 }
302 }