trap signals for "-serial mon:stdio"
[qemu.git] / target-microblaze / translate.c
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "helper.h"
25 #include "microblaze-decode.h"
26
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define SIM_COMPAT 0
31 #define DISAS_GNU 1
32 #define DISAS_MB 1
33 #if DISAS_MB && !SIM_COMPAT
34 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
35 #else
36 # define LOG_DIS(...) do { } while (0)
37 #endif
38
39 #define D(x)
40
41 #define EXTRACT_FIELD(src, start, end) \
42 (((src) >> start) & ((1 << (end - start + 1)) - 1))
43
44 static TCGv env_debug;
45 static TCGv_ptr cpu_env;
46 static TCGv cpu_R[32];
47 static TCGv cpu_SR[18];
48 static TCGv env_imm;
49 static TCGv env_btaken;
50 static TCGv env_btarget;
51 static TCGv env_iflags;
52
53 #include "exec/gen-icount.h"
54
55 /* This is the state at translation time. */
56 typedef struct DisasContext {
57 CPUMBState *env;
58 target_ulong pc;
59
60 /* Decoder. */
61 int type_b;
62 uint32_t ir;
63 uint8_t opcode;
64 uint8_t rd, ra, rb;
65 uint16_t imm;
66
67 unsigned int cpustate_changed;
68 unsigned int delayed_branch;
69 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
70 unsigned int clear_imm;
71 int is_jmp;
72
73 #define JMP_NOJMP 0
74 #define JMP_DIRECT 1
75 #define JMP_DIRECT_CC 2
76 #define JMP_INDIRECT 3
77 unsigned int jmp;
78 uint32_t jmp_pc;
79
80 int abort_at_next_insn;
81 int nr_nops;
82 struct TranslationBlock *tb;
83 int singlestep_enabled;
84 } DisasContext;
85
86 static const char *regnames[] =
87 {
88 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
89 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
90 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
91 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
92 };
93
94 static const char *special_regnames[] =
95 {
96 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
97 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
98 "sr16", "sr17", "sr18"
99 };
100
101 /* Sign extend at translation time. */
102 static inline int sign_extend(unsigned int val, unsigned int width)
103 {
104 int sval;
105
106 /* LSL. */
107 val <<= 31 - width;
108 sval = val;
109 /* ASR. */
110 sval >>= 31 - width;
111 return sval;
112 }
113
114 static inline void t_sync_flags(DisasContext *dc)
115 {
116 /* Synch the tb dependent flags between translator and runtime. */
117 if (dc->tb_flags != dc->synced_flags) {
118 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
119 dc->synced_flags = dc->tb_flags;
120 }
121 }
122
123 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
124 {
125 TCGv_i32 tmp = tcg_const_i32(index);
126
127 t_sync_flags(dc);
128 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
129 gen_helper_raise_exception(cpu_env, tmp);
130 tcg_temp_free_i32(tmp);
131 dc->is_jmp = DISAS_UPDATE;
132 }
133
134 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
135 {
136 TranslationBlock *tb;
137 tb = dc->tb;
138 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
139 tcg_gen_goto_tb(n);
140 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
141 tcg_gen_exit_tb((tcg_target_long)tb + n);
142 } else {
143 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
144 tcg_gen_exit_tb(0);
145 }
146 }
147
148 static void read_carry(DisasContext *dc, TCGv d)
149 {
150 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
151 }
152
153 static void write_carry(DisasContext *dc, TCGv v)
154 {
155 TCGv t0 = tcg_temp_new();
156 tcg_gen_shli_tl(t0, v, 31);
157 tcg_gen_sari_tl(t0, t0, 31);
158 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
159 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
160 ~(MSR_C | MSR_CC));
161 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
162 tcg_temp_free(t0);
163 }
164
165 static void write_carryi(DisasContext *dc, int carry)
166 {
167 TCGv t0 = tcg_temp_new();
168 tcg_gen_movi_tl(t0, carry ? 1 : 0);
169 write_carry(dc, t0);
170 tcg_temp_free(t0);
171 }
172
173 /* True if ALU operand b is a small immediate that may deserve
174 faster treatment. */
175 static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
176 {
177 /* Immediate insn without the imm prefix ? */
178 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
179 }
180
181 static inline TCGv *dec_alu_op_b(DisasContext *dc)
182 {
183 if (dc->type_b) {
184 if (dc->tb_flags & IMM_FLAG)
185 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
186 else
187 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
188 return &env_imm;
189 } else
190 return &cpu_R[dc->rb];
191 }
192
193 static void dec_add(DisasContext *dc)
194 {
195 unsigned int k, c;
196 TCGv cf;
197
198 k = dc->opcode & 4;
199 c = dc->opcode & 2;
200
201 LOG_DIS("add%s%s%s r%d r%d r%d\n",
202 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
203 dc->rd, dc->ra, dc->rb);
204
205 /* Take care of the easy cases first. */
206 if (k) {
207 /* k - keep carry, no need to update MSR. */
208 /* If rd == r0, it's a nop. */
209 if (dc->rd) {
210 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
211
212 if (c) {
213 /* c - Add carry into the result. */
214 cf = tcg_temp_new();
215
216 read_carry(dc, cf);
217 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
218 tcg_temp_free(cf);
219 }
220 }
221 return;
222 }
223
224 /* From now on, we can assume k is zero. So we need to update MSR. */
225 /* Extract carry. */
226 cf = tcg_temp_new();
227 if (c) {
228 read_carry(dc, cf);
229 } else {
230 tcg_gen_movi_tl(cf, 0);
231 }
232
233 if (dc->rd) {
234 TCGv ncf = tcg_temp_new();
235 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
236 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
237 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
238 write_carry(dc, ncf);
239 tcg_temp_free(ncf);
240 } else {
241 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
242 write_carry(dc, cf);
243 }
244 tcg_temp_free(cf);
245 }
246
247 static void dec_sub(DisasContext *dc)
248 {
249 unsigned int u, cmp, k, c;
250 TCGv cf, na;
251
252 u = dc->imm & 2;
253 k = dc->opcode & 4;
254 c = dc->opcode & 2;
255 cmp = (dc->imm & 1) && (!dc->type_b) && k;
256
257 if (cmp) {
258 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
259 if (dc->rd) {
260 if (u)
261 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
262 else
263 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
264 }
265 return;
266 }
267
268 LOG_DIS("sub%s%s r%d, r%d r%d\n",
269 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
270
271 /* Take care of the easy cases first. */
272 if (k) {
273 /* k - keep carry, no need to update MSR. */
274 /* If rd == r0, it's a nop. */
275 if (dc->rd) {
276 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
277
278 if (c) {
279 /* c - Add carry into the result. */
280 cf = tcg_temp_new();
281
282 read_carry(dc, cf);
283 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
284 tcg_temp_free(cf);
285 }
286 }
287 return;
288 }
289
290 /* From now on, we can assume k is zero. So we need to update MSR. */
291 /* Extract carry. And complement a into na. */
292 cf = tcg_temp_new();
293 na = tcg_temp_new();
294 if (c) {
295 read_carry(dc, cf);
296 } else {
297 tcg_gen_movi_tl(cf, 1);
298 }
299
300 /* d = b + ~a + c. carry defaults to 1. */
301 tcg_gen_not_tl(na, cpu_R[dc->ra]);
302
303 if (dc->rd) {
304 TCGv ncf = tcg_temp_new();
305 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
306 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
307 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
308 write_carry(dc, ncf);
309 tcg_temp_free(ncf);
310 } else {
311 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
312 write_carry(dc, cf);
313 }
314 tcg_temp_free(cf);
315 tcg_temp_free(na);
316 }
317
318 static void dec_pattern(DisasContext *dc)
319 {
320 unsigned int mode;
321 int l1;
322
323 if ((dc->tb_flags & MSR_EE_FLAG)
324 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
325 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
326 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
327 t_gen_raise_exception(dc, EXCP_HW_EXCP);
328 }
329
330 mode = dc->opcode & 3;
331 switch (mode) {
332 case 0:
333 /* pcmpbf. */
334 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
335 if (dc->rd)
336 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
337 break;
338 case 2:
339 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
340 if (dc->rd) {
341 TCGv t0 = tcg_temp_local_new();
342 l1 = gen_new_label();
343 tcg_gen_movi_tl(t0, 1);
344 tcg_gen_brcond_tl(TCG_COND_EQ,
345 cpu_R[dc->ra], cpu_R[dc->rb], l1);
346 tcg_gen_movi_tl(t0, 0);
347 gen_set_label(l1);
348 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
349 tcg_temp_free(t0);
350 }
351 break;
352 case 3:
353 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
354 l1 = gen_new_label();
355 if (dc->rd) {
356 TCGv t0 = tcg_temp_local_new();
357 tcg_gen_movi_tl(t0, 1);
358 tcg_gen_brcond_tl(TCG_COND_NE,
359 cpu_R[dc->ra], cpu_R[dc->rb], l1);
360 tcg_gen_movi_tl(t0, 0);
361 gen_set_label(l1);
362 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
363 tcg_temp_free(t0);
364 }
365 break;
366 default:
367 cpu_abort(dc->env,
368 "unsupported pattern insn opcode=%x\n", dc->opcode);
369 break;
370 }
371 }
372
373 static void dec_and(DisasContext *dc)
374 {
375 unsigned int not;
376
377 if (!dc->type_b && (dc->imm & (1 << 10))) {
378 dec_pattern(dc);
379 return;
380 }
381
382 not = dc->opcode & (1 << 1);
383 LOG_DIS("and%s\n", not ? "n" : "");
384
385 if (!dc->rd)
386 return;
387
388 if (not) {
389 TCGv t = tcg_temp_new();
390 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
391 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
392 tcg_temp_free(t);
393 } else
394 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
395 }
396
397 static void dec_or(DisasContext *dc)
398 {
399 if (!dc->type_b && (dc->imm & (1 << 10))) {
400 dec_pattern(dc);
401 return;
402 }
403
404 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
405 if (dc->rd)
406 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
407 }
408
409 static void dec_xor(DisasContext *dc)
410 {
411 if (!dc->type_b && (dc->imm & (1 << 10))) {
412 dec_pattern(dc);
413 return;
414 }
415
416 LOG_DIS("xor r%d\n", dc->rd);
417 if (dc->rd)
418 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
419 }
420
421 static inline void msr_read(DisasContext *dc, TCGv d)
422 {
423 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
424 }
425
426 static inline void msr_write(DisasContext *dc, TCGv v)
427 {
428 TCGv t;
429
430 t = tcg_temp_new();
431 dc->cpustate_changed = 1;
432 /* PVR bit is not writable. */
433 tcg_gen_andi_tl(t, v, ~MSR_PVR);
434 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
435 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
436 tcg_temp_free(t);
437 }
438
439 static void dec_msr(DisasContext *dc)
440 {
441 TCGv t0, t1;
442 unsigned int sr, to, rn;
443 int mem_index = cpu_mmu_index(dc->env);
444
445 sr = dc->imm & ((1 << 14) - 1);
446 to = dc->imm & (1 << 14);
447 dc->type_b = 1;
448 if (to)
449 dc->cpustate_changed = 1;
450
451 /* msrclr and msrset. */
452 if (!(dc->imm & (1 << 15))) {
453 unsigned int clr = dc->ir & (1 << 16);
454
455 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
456 dc->rd, dc->imm);
457
458 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
459 /* nop??? */
460 return;
461 }
462
463 if ((dc->tb_flags & MSR_EE_FLAG)
464 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
465 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
466 t_gen_raise_exception(dc, EXCP_HW_EXCP);
467 return;
468 }
469
470 if (dc->rd)
471 msr_read(dc, cpu_R[dc->rd]);
472
473 t0 = tcg_temp_new();
474 t1 = tcg_temp_new();
475 msr_read(dc, t0);
476 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
477
478 if (clr) {
479 tcg_gen_not_tl(t1, t1);
480 tcg_gen_and_tl(t0, t0, t1);
481 } else
482 tcg_gen_or_tl(t0, t0, t1);
483 msr_write(dc, t0);
484 tcg_temp_free(t0);
485 tcg_temp_free(t1);
486 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
487 dc->is_jmp = DISAS_UPDATE;
488 return;
489 }
490
491 if (to) {
492 if ((dc->tb_flags & MSR_EE_FLAG)
493 && mem_index == MMU_USER_IDX) {
494 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
495 t_gen_raise_exception(dc, EXCP_HW_EXCP);
496 return;
497 }
498 }
499
500 #if !defined(CONFIG_USER_ONLY)
501 /* Catch read/writes to the mmu block. */
502 if ((sr & ~0xff) == 0x1000) {
503 sr &= 7;
504 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
505 if (to)
506 gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
507 else
508 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
509 return;
510 }
511 #endif
512
513 if (to) {
514 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
515 switch (sr) {
516 case 0:
517 break;
518 case 1:
519 msr_write(dc, cpu_R[dc->ra]);
520 break;
521 case 0x3:
522 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
523 break;
524 case 0x5:
525 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
526 break;
527 case 0x7:
528 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
529 break;
530 case 0x800:
531 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
532 break;
533 case 0x802:
534 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
535 break;
536 default:
537 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
538 break;
539 }
540 } else {
541 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
542
543 switch (sr) {
544 case 0:
545 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
546 break;
547 case 1:
548 msr_read(dc, cpu_R[dc->rd]);
549 break;
550 case 0x3:
551 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
552 break;
553 case 0x5:
554 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
555 break;
556 case 0x7:
557 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
558 break;
559 case 0xb:
560 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
561 break;
562 case 0x800:
563 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
564 break;
565 case 0x802:
566 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
567 break;
568 case 0x2000:
569 case 0x2001:
570 case 0x2002:
571 case 0x2003:
572 case 0x2004:
573 case 0x2005:
574 case 0x2006:
575 case 0x2007:
576 case 0x2008:
577 case 0x2009:
578 case 0x200a:
579 case 0x200b:
580 case 0x200c:
581 rn = sr & 0xf;
582 tcg_gen_ld_tl(cpu_R[dc->rd],
583 cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
584 break;
585 default:
586 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
587 break;
588 }
589 }
590
591 if (dc->rd == 0) {
592 tcg_gen_movi_tl(cpu_R[0], 0);
593 }
594 }
595
596 /* 64-bit signed mul, lower result in d and upper in d2. */
597 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
598 {
599 TCGv_i64 t0, t1;
600
601 t0 = tcg_temp_new_i64();
602 t1 = tcg_temp_new_i64();
603
604 tcg_gen_ext_i32_i64(t0, a);
605 tcg_gen_ext_i32_i64(t1, b);
606 tcg_gen_mul_i64(t0, t0, t1);
607
608 tcg_gen_trunc_i64_i32(d, t0);
609 tcg_gen_shri_i64(t0, t0, 32);
610 tcg_gen_trunc_i64_i32(d2, t0);
611
612 tcg_temp_free_i64(t0);
613 tcg_temp_free_i64(t1);
614 }
615
616 /* 64-bit unsigned muls, lower result in d and upper in d2. */
617 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
618 {
619 TCGv_i64 t0, t1;
620
621 t0 = tcg_temp_new_i64();
622 t1 = tcg_temp_new_i64();
623
624 tcg_gen_extu_i32_i64(t0, a);
625 tcg_gen_extu_i32_i64(t1, b);
626 tcg_gen_mul_i64(t0, t0, t1);
627
628 tcg_gen_trunc_i64_i32(d, t0);
629 tcg_gen_shri_i64(t0, t0, 32);
630 tcg_gen_trunc_i64_i32(d2, t0);
631
632 tcg_temp_free_i64(t0);
633 tcg_temp_free_i64(t1);
634 }
635
636 /* Multiplier unit. */
637 static void dec_mul(DisasContext *dc)
638 {
639 TCGv d[2];
640 unsigned int subcode;
641
642 if ((dc->tb_flags & MSR_EE_FLAG)
643 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
644 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
645 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
646 t_gen_raise_exception(dc, EXCP_HW_EXCP);
647 return;
648 }
649
650 subcode = dc->imm & 3;
651 d[0] = tcg_temp_new();
652 d[1] = tcg_temp_new();
653
654 if (dc->type_b) {
655 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
656 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
657 goto done;
658 }
659
660 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
661 if (subcode >= 1 && subcode <= 3
662 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
663 /* nop??? */
664 }
665
666 switch (subcode) {
667 case 0:
668 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
669 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
670 break;
671 case 1:
672 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
673 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
674 break;
675 case 2:
676 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
677 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
678 break;
679 case 3:
680 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
681 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
682 break;
683 default:
684 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
685 break;
686 }
687 done:
688 tcg_temp_free(d[0]);
689 tcg_temp_free(d[1]);
690 }
691
692 /* Div unit. */
693 static void dec_div(DisasContext *dc)
694 {
695 unsigned int u;
696
697 u = dc->imm & 2;
698 LOG_DIS("div\n");
699
700 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
701 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
702 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
703 t_gen_raise_exception(dc, EXCP_HW_EXCP);
704 }
705
706 if (u)
707 gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
708 cpu_R[dc->ra]);
709 else
710 gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
711 cpu_R[dc->ra]);
712 if (!dc->rd)
713 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
714 }
715
716 static void dec_barrel(DisasContext *dc)
717 {
718 TCGv t0;
719 unsigned int s, t;
720
721 if ((dc->tb_flags & MSR_EE_FLAG)
722 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
723 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
724 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
725 t_gen_raise_exception(dc, EXCP_HW_EXCP);
726 return;
727 }
728
729 s = dc->imm & (1 << 10);
730 t = dc->imm & (1 << 9);
731
732 LOG_DIS("bs%s%s r%d r%d r%d\n",
733 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
734
735 t0 = tcg_temp_new();
736
737 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
738 tcg_gen_andi_tl(t0, t0, 31);
739
740 if (s)
741 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
742 else {
743 if (t)
744 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
745 else
746 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
747 }
748 }
749
750 static void dec_bit(DisasContext *dc)
751 {
752 TCGv t0, t1;
753 unsigned int op;
754 int mem_index = cpu_mmu_index(dc->env);
755
756 op = dc->ir & ((1 << 9) - 1);
757 switch (op) {
758 case 0x21:
759 /* src. */
760 t0 = tcg_temp_new();
761
762 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
763 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
764 if (dc->rd) {
765 t1 = tcg_temp_new();
766 read_carry(dc, t1);
767 tcg_gen_shli_tl(t1, t1, 31);
768
769 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
770 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
771 tcg_temp_free(t1);
772 }
773
774 /* Update carry. */
775 write_carry(dc, t0);
776 tcg_temp_free(t0);
777 break;
778
779 case 0x1:
780 case 0x41:
781 /* srl. */
782 t0 = tcg_temp_new();
783 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
784
785 /* Update carry. */
786 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
787 write_carry(dc, t0);
788 tcg_temp_free(t0);
789 if (dc->rd) {
790 if (op == 0x41)
791 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
792 else
793 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
794 }
795 break;
796 case 0x60:
797 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
798 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
799 break;
800 case 0x61:
801 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
802 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
803 break;
804 case 0x64:
805 case 0x66:
806 case 0x74:
807 case 0x76:
808 /* wdc. */
809 LOG_DIS("wdc r%d\n", dc->ra);
810 if ((dc->tb_flags & MSR_EE_FLAG)
811 && mem_index == MMU_USER_IDX) {
812 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
813 t_gen_raise_exception(dc, EXCP_HW_EXCP);
814 return;
815 }
816 break;
817 case 0x68:
818 /* wic. */
819 LOG_DIS("wic r%d\n", dc->ra);
820 if ((dc->tb_flags & MSR_EE_FLAG)
821 && mem_index == MMU_USER_IDX) {
822 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
823 t_gen_raise_exception(dc, EXCP_HW_EXCP);
824 return;
825 }
826 break;
827 case 0xe0:
828 if ((dc->tb_flags & MSR_EE_FLAG)
829 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
830 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
831 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
832 t_gen_raise_exception(dc, EXCP_HW_EXCP);
833 }
834 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
835 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
836 }
837 break;
838 case 0x1e0:
839 /* swapb */
840 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
841 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
842 break;
843 case 0x1e2:
844 /*swaph */
845 LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
846 tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
847 break;
848 default:
849 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
850 dc->pc, op, dc->rd, dc->ra, dc->rb);
851 break;
852 }
853 }
854
855 static inline void sync_jmpstate(DisasContext *dc)
856 {
857 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
858 if (dc->jmp == JMP_DIRECT) {
859 tcg_gen_movi_tl(env_btaken, 1);
860 }
861 dc->jmp = JMP_INDIRECT;
862 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
863 }
864 }
865
866 static void dec_imm(DisasContext *dc)
867 {
868 LOG_DIS("imm %x\n", dc->imm << 16);
869 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
870 dc->tb_flags |= IMM_FLAG;
871 dc->clear_imm = 0;
872 }
873
874 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
875 unsigned int size)
876 {
877 int mem_index = cpu_mmu_index(dc->env);
878
879 if (size == 1) {
880 tcg_gen_qemu_ld8u(dst, addr, mem_index);
881 } else if (size == 2) {
882 tcg_gen_qemu_ld16u(dst, addr, mem_index);
883 } else if (size == 4) {
884 tcg_gen_qemu_ld32u(dst, addr, mem_index);
885 } else
886 cpu_abort(dc->env, "Incorrect load size %d\n", size);
887 }
888
889 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
890 {
891 unsigned int extimm = dc->tb_flags & IMM_FLAG;
892 /* Should be set to one if r1 is used by loadstores. */
893 int stackprot = 0;
894
895 /* All load/stores use ra. */
896 if (dc->ra == 1) {
897 stackprot = 1;
898 }
899
900 /* Treat the common cases first. */
901 if (!dc->type_b) {
902 /* If any of the regs is r0, return a ptr to the other. */
903 if (dc->ra == 0) {
904 return &cpu_R[dc->rb];
905 } else if (dc->rb == 0) {
906 return &cpu_R[dc->ra];
907 }
908
909 if (dc->rb == 1) {
910 stackprot = 1;
911 }
912
913 *t = tcg_temp_new();
914 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
915
916 if (stackprot) {
917 gen_helper_stackprot(cpu_env, *t);
918 }
919 return t;
920 }
921 /* Immediate. */
922 if (!extimm) {
923 if (dc->imm == 0) {
924 return &cpu_R[dc->ra];
925 }
926 *t = tcg_temp_new();
927 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
928 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
929 } else {
930 *t = tcg_temp_new();
931 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
932 }
933
934 if (stackprot) {
935 gen_helper_stackprot(cpu_env, *t);
936 }
937 return t;
938 }
939
940 static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
941 {
942 if (size == 4) {
943 tcg_gen_bswap32_tl(dst, src);
944 } else if (size == 2) {
945 TCGv t = tcg_temp_new();
946
947 /* bswap16 assumes the high bits are zero. */
948 tcg_gen_andi_tl(t, src, 0xffff);
949 tcg_gen_bswap16_tl(dst, t);
950 tcg_temp_free(t);
951 } else {
952 /* Ignore.
953 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
954 */
955 }
956 }
957
958 static void dec_load(DisasContext *dc)
959 {
960 TCGv t, *addr;
961 unsigned int size, rev = 0, ex = 0;
962
963 size = 1 << (dc->opcode & 3);
964
965 if (!dc->type_b) {
966 rev = (dc->ir >> 9) & 1;
967 ex = (dc->ir >> 10) & 1;
968 }
969
970 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
971 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
972 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
973 t_gen_raise_exception(dc, EXCP_HW_EXCP);
974 return;
975 }
976
977 LOG_DIS("l%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
978 ex ? "x" : "");
979
980 t_sync_flags(dc);
981 addr = compute_ldst_addr(dc, &t);
982
983 /*
984 * When doing reverse accesses we need to do two things.
985 *
986 * 1. Reverse the address wrt endianness.
987 * 2. Byteswap the data lanes on the way back into the CPU core.
988 */
989 if (rev && size != 4) {
990 /* Endian reverse the address. t is addr. */
991 switch (size) {
992 case 1:
993 {
994 /* 00 -> 11
995 01 -> 10
996 10 -> 10
997 11 -> 00 */
998 TCGv low = tcg_temp_new();
999
1000 /* Force addr into the temp. */
1001 if (addr != &t) {
1002 t = tcg_temp_new();
1003 tcg_gen_mov_tl(t, *addr);
1004 addr = &t;
1005 }
1006
1007 tcg_gen_andi_tl(low, t, 3);
1008 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1009 tcg_gen_andi_tl(t, t, ~3);
1010 tcg_gen_or_tl(t, t, low);
1011 tcg_gen_mov_tl(env_imm, t);
1012 tcg_temp_free(low);
1013 break;
1014 }
1015
1016 case 2:
1017 /* 00 -> 10
1018 10 -> 00. */
1019 /* Force addr into the temp. */
1020 if (addr != &t) {
1021 t = tcg_temp_new();
1022 tcg_gen_xori_tl(t, *addr, 2);
1023 addr = &t;
1024 } else {
1025 tcg_gen_xori_tl(t, t, 2);
1026 }
1027 break;
1028 default:
1029 cpu_abort(dc->env, "Invalid reverse size\n");
1030 break;
1031 }
1032 }
1033
1034 /* lwx does not throw unaligned access errors, so force alignment */
1035 if (ex) {
1036 /* Force addr into the temp. */
1037 if (addr != &t) {
1038 t = tcg_temp_new();
1039 tcg_gen_mov_tl(t, *addr);
1040 addr = &t;
1041 }
1042 tcg_gen_andi_tl(t, t, ~3);
1043 }
1044
1045 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1046 sync_jmpstate(dc);
1047
1048 /* Verify alignment if needed. */
1049 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1050 TCGv v = tcg_temp_new();
1051
1052 /*
1053 * Microblaze gives MMU faults priority over faults due to
1054 * unaligned addresses. That's why we speculatively do the load
1055 * into v. If the load succeeds, we verify alignment of the
1056 * address and if that succeeds we write into the destination reg.
1057 */
1058 gen_load(dc, v, *addr, size);
1059
1060 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1061 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
1062 tcg_const_tl(0), tcg_const_tl(size - 1));
1063 if (dc->rd) {
1064 if (rev) {
1065 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1066 } else {
1067 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1068 }
1069 }
1070 tcg_temp_free(v);
1071 } else {
1072 if (dc->rd) {
1073 gen_load(dc, cpu_R[dc->rd], *addr, size);
1074 if (rev) {
1075 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1076 }
1077 } else {
1078 /* We are loading into r0, no need to reverse. */
1079 gen_load(dc, env_imm, *addr, size);
1080 }
1081 }
1082
1083 if (ex) { /* lwx */
1084 /* no support for for AXI exclusive so always clear C */
1085 write_carryi(dc, 0);
1086 tcg_gen_st_tl(*addr, cpu_env, offsetof(CPUMBState, res_addr));
1087 }
1088
1089 if (addr == &t)
1090 tcg_temp_free(t);
1091 }
1092
1093 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1094 unsigned int size)
1095 {
1096 int mem_index = cpu_mmu_index(dc->env);
1097
1098 if (size == 1)
1099 tcg_gen_qemu_st8(val, addr, mem_index);
1100 else if (size == 2) {
1101 tcg_gen_qemu_st16(val, addr, mem_index);
1102 } else if (size == 4) {
1103 tcg_gen_qemu_st32(val, addr, mem_index);
1104 } else
1105 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1106 }
1107
1108 static void dec_store(DisasContext *dc)
1109 {
1110 TCGv t, *addr, swx_addr, r_check;
1111 int swx_skip = 0;
1112 unsigned int size, rev = 0, ex = 0;
1113
1114 size = 1 << (dc->opcode & 3);
1115 if (!dc->type_b) {
1116 rev = (dc->ir >> 9) & 1;
1117 ex = (dc->ir >> 10) & 1;
1118 }
1119
1120 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
1121 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1122 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1123 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1124 return;
1125 }
1126
1127 LOG_DIS("s%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
1128 ex ? "x" : "");
1129 t_sync_flags(dc);
1130 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1131 sync_jmpstate(dc);
1132 addr = compute_ldst_addr(dc, &t);
1133
1134 r_check = tcg_temp_new();
1135 swx_addr = tcg_temp_local_new();
1136 if (ex) { /* swx */
1137
1138 /* Force addr into the swx_addr. */
1139 tcg_gen_mov_tl(swx_addr, *addr);
1140 addr = &swx_addr;
1141 /* swx does not throw unaligned access errors, so force alignment */
1142 tcg_gen_andi_tl(swx_addr, swx_addr, ~3);
1143
1144 tcg_gen_ld_tl(r_check, cpu_env, offsetof(CPUMBState, res_addr));
1145 write_carryi(dc, 1);
1146 swx_skip = gen_new_label();
1147 tcg_gen_brcond_tl(TCG_COND_NE, r_check, swx_addr, swx_skip);
1148 write_carryi(dc, 0);
1149 }
1150
1151 if (rev && size != 4) {
1152 /* Endian reverse the address. t is addr. */
1153 switch (size) {
1154 case 1:
1155 {
1156 /* 00 -> 11
1157 01 -> 10
1158 10 -> 10
1159 11 -> 00 */
1160 TCGv low = tcg_temp_new();
1161
1162 /* Force addr into the temp. */
1163 if (addr != &t) {
1164 t = tcg_temp_new();
1165 tcg_gen_mov_tl(t, *addr);
1166 addr = &t;
1167 }
1168
1169 tcg_gen_andi_tl(low, t, 3);
1170 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1171 tcg_gen_andi_tl(t, t, ~3);
1172 tcg_gen_or_tl(t, t, low);
1173 tcg_gen_mov_tl(env_imm, t);
1174 tcg_temp_free(low);
1175 break;
1176 }
1177
1178 case 2:
1179 /* 00 -> 10
1180 10 -> 00. */
1181 /* Force addr into the temp. */
1182 if (addr != &t) {
1183 t = tcg_temp_new();
1184 tcg_gen_xori_tl(t, *addr, 2);
1185 addr = &t;
1186 } else {
1187 tcg_gen_xori_tl(t, t, 2);
1188 }
1189 break;
1190 default:
1191 cpu_abort(dc->env, "Invalid reverse size\n");
1192 break;
1193 }
1194
1195 if (size != 1) {
1196 TCGv bs_data = tcg_temp_new();
1197 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1198 gen_store(dc, *addr, bs_data, size);
1199 tcg_temp_free(bs_data);
1200 } else {
1201 gen_store(dc, *addr, cpu_R[dc->rd], size);
1202 }
1203 } else {
1204 if (rev) {
1205 TCGv bs_data = tcg_temp_new();
1206 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1207 gen_store(dc, *addr, bs_data, size);
1208 tcg_temp_free(bs_data);
1209 } else {
1210 gen_store(dc, *addr, cpu_R[dc->rd], size);
1211 }
1212 }
1213
1214 /* Verify alignment if needed. */
1215 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1216 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1217 /* FIXME: if the alignment is wrong, we should restore the value
1218 * in memory. One possible way to achieve this is to probe
1219 * the MMU prior to the memaccess, thay way we could put
1220 * the alignment checks in between the probe and the mem
1221 * access.
1222 */
1223 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
1224 tcg_const_tl(1), tcg_const_tl(size - 1));
1225 }
1226
1227 if (ex) {
1228 gen_set_label(swx_skip);
1229 }
1230 tcg_temp_free(r_check);
1231 tcg_temp_free(swx_addr);
1232
1233 if (addr == &t)
1234 tcg_temp_free(t);
1235 }
1236
1237 static inline void eval_cc(DisasContext *dc, unsigned int cc,
1238 TCGv d, TCGv a, TCGv b)
1239 {
1240 switch (cc) {
1241 case CC_EQ:
1242 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
1243 break;
1244 case CC_NE:
1245 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
1246 break;
1247 case CC_LT:
1248 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
1249 break;
1250 case CC_LE:
1251 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
1252 break;
1253 case CC_GE:
1254 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
1255 break;
1256 case CC_GT:
1257 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
1258 break;
1259 default:
1260 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1261 break;
1262 }
1263 }
1264
1265 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1266 {
1267 int l1;
1268
1269 l1 = gen_new_label();
1270 /* Conditional jmp. */
1271 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1272 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1273 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1274 gen_set_label(l1);
1275 }
1276
1277 static void dec_bcc(DisasContext *dc)
1278 {
1279 unsigned int cc;
1280 unsigned int dslot;
1281
1282 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1283 dslot = dc->ir & (1 << 25);
1284 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1285
1286 dc->delayed_branch = 1;
1287 if (dslot) {
1288 dc->delayed_branch = 2;
1289 dc->tb_flags |= D_FLAG;
1290 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1291 cpu_env, offsetof(CPUMBState, bimm));
1292 }
1293
1294 if (dec_alu_op_b_is_small_imm(dc)) {
1295 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1296
1297 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
1298 dc->jmp = JMP_DIRECT_CC;
1299 dc->jmp_pc = dc->pc + offset;
1300 } else {
1301 dc->jmp = JMP_INDIRECT;
1302 tcg_gen_movi_tl(env_btarget, dc->pc);
1303 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1304 }
1305 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
1306 }
1307
1308 static void dec_br(DisasContext *dc)
1309 {
1310 unsigned int dslot, link, abs, mbar;
1311 int mem_index = cpu_mmu_index(dc->env);
1312
1313 dslot = dc->ir & (1 << 20);
1314 abs = dc->ir & (1 << 19);
1315 link = dc->ir & (1 << 18);
1316
1317 /* Memory barrier. */
1318 mbar = (dc->ir >> 16) & 31;
1319 if (mbar == 2 && dc->imm == 4) {
1320 /* mbar IMM & 16 decodes to sleep. */
1321 if (dc->rd & 16) {
1322 TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
1323 TCGv_i32 tmp_1 = tcg_const_i32(1);
1324
1325 LOG_DIS("sleep\n");
1326
1327 t_sync_flags(dc);
1328 tcg_gen_st_i32(tmp_1, cpu_env,
1329 -offsetof(MicroBlazeCPU, env)
1330 +offsetof(CPUState, halted));
1331 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
1332 gen_helper_raise_exception(cpu_env, tmp_hlt);
1333 tcg_temp_free_i32(tmp_hlt);
1334 tcg_temp_free_i32(tmp_1);
1335 return;
1336 }
1337 LOG_DIS("mbar %d\n", dc->rd);
1338 /* Break the TB. */
1339 dc->cpustate_changed = 1;
1340 return;
1341 }
1342
1343 LOG_DIS("br%s%s%s%s imm=%x\n",
1344 abs ? "a" : "", link ? "l" : "",
1345 dc->type_b ? "i" : "", dslot ? "d" : "",
1346 dc->imm);
1347
1348 dc->delayed_branch = 1;
1349 if (dslot) {
1350 dc->delayed_branch = 2;
1351 dc->tb_flags |= D_FLAG;
1352 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1353 cpu_env, offsetof(CPUMBState, bimm));
1354 }
1355 if (link && dc->rd)
1356 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1357
1358 dc->jmp = JMP_INDIRECT;
1359 if (abs) {
1360 tcg_gen_movi_tl(env_btaken, 1);
1361 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1362 if (link && !dslot) {
1363 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1364 t_gen_raise_exception(dc, EXCP_BREAK);
1365 if (dc->imm == 0) {
1366 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1367 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1368 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1369 return;
1370 }
1371
1372 t_gen_raise_exception(dc, EXCP_DEBUG);
1373 }
1374 }
1375 } else {
1376 if (dec_alu_op_b_is_small_imm(dc)) {
1377 dc->jmp = JMP_DIRECT;
1378 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1379 } else {
1380 tcg_gen_movi_tl(env_btaken, 1);
1381 tcg_gen_movi_tl(env_btarget, dc->pc);
1382 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1383 }
1384 }
1385 }
1386
1387 static inline void do_rti(DisasContext *dc)
1388 {
1389 TCGv t0, t1;
1390 t0 = tcg_temp_new();
1391 t1 = tcg_temp_new();
1392 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1393 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1394 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1395
1396 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1397 tcg_gen_or_tl(t1, t1, t0);
1398 msr_write(dc, t1);
1399 tcg_temp_free(t1);
1400 tcg_temp_free(t0);
1401 dc->tb_flags &= ~DRTI_FLAG;
1402 }
1403
1404 static inline void do_rtb(DisasContext *dc)
1405 {
1406 TCGv t0, t1;
1407 t0 = tcg_temp_new();
1408 t1 = tcg_temp_new();
1409 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1410 tcg_gen_shri_tl(t0, t1, 1);
1411 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1412
1413 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1414 tcg_gen_or_tl(t1, t1, t0);
1415 msr_write(dc, t1);
1416 tcg_temp_free(t1);
1417 tcg_temp_free(t0);
1418 dc->tb_flags &= ~DRTB_FLAG;
1419 }
1420
1421 static inline void do_rte(DisasContext *dc)
1422 {
1423 TCGv t0, t1;
1424 t0 = tcg_temp_new();
1425 t1 = tcg_temp_new();
1426
1427 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1428 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1429 tcg_gen_shri_tl(t0, t1, 1);
1430 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1431
1432 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1433 tcg_gen_or_tl(t1, t1, t0);
1434 msr_write(dc, t1);
1435 tcg_temp_free(t1);
1436 tcg_temp_free(t0);
1437 dc->tb_flags &= ~DRTE_FLAG;
1438 }
1439
1440 static void dec_rts(DisasContext *dc)
1441 {
1442 unsigned int b_bit, i_bit, e_bit;
1443 int mem_index = cpu_mmu_index(dc->env);
1444
1445 i_bit = dc->ir & (1 << 21);
1446 b_bit = dc->ir & (1 << 22);
1447 e_bit = dc->ir & (1 << 23);
1448
1449 dc->delayed_branch = 2;
1450 dc->tb_flags |= D_FLAG;
1451 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1452 cpu_env, offsetof(CPUMBState, bimm));
1453
1454 if (i_bit) {
1455 LOG_DIS("rtid ir=%x\n", dc->ir);
1456 if ((dc->tb_flags & MSR_EE_FLAG)
1457 && mem_index == MMU_USER_IDX) {
1458 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1459 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1460 }
1461 dc->tb_flags |= DRTI_FLAG;
1462 } else if (b_bit) {
1463 LOG_DIS("rtbd ir=%x\n", dc->ir);
1464 if ((dc->tb_flags & MSR_EE_FLAG)
1465 && mem_index == MMU_USER_IDX) {
1466 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1467 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1468 }
1469 dc->tb_flags |= DRTB_FLAG;
1470 } else if (e_bit) {
1471 LOG_DIS("rted ir=%x\n", dc->ir);
1472 if ((dc->tb_flags & MSR_EE_FLAG)
1473 && mem_index == MMU_USER_IDX) {
1474 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1475 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1476 }
1477 dc->tb_flags |= DRTE_FLAG;
1478 } else
1479 LOG_DIS("rts ir=%x\n", dc->ir);
1480
1481 dc->jmp = JMP_INDIRECT;
1482 tcg_gen_movi_tl(env_btaken, 1);
1483 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1484 }
1485
1486 static int dec_check_fpuv2(DisasContext *dc)
1487 {
1488 int r;
1489
1490 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1491
1492 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1493 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1494 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1495 }
1496 return r;
1497 }
1498
1499 static void dec_fpu(DisasContext *dc)
1500 {
1501 unsigned int fpu_insn;
1502
1503 if ((dc->tb_flags & MSR_EE_FLAG)
1504 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1505 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1506 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1507 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1508 return;
1509 }
1510
1511 fpu_insn = (dc->ir >> 7) & 7;
1512
1513 switch (fpu_insn) {
1514 case 0:
1515 gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1516 cpu_R[dc->rb]);
1517 break;
1518
1519 case 1:
1520 gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1521 cpu_R[dc->rb]);
1522 break;
1523
1524 case 2:
1525 gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1526 cpu_R[dc->rb]);
1527 break;
1528
1529 case 3:
1530 gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1531 cpu_R[dc->rb]);
1532 break;
1533
1534 case 4:
1535 switch ((dc->ir >> 4) & 7) {
1536 case 0:
1537 gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
1538 cpu_R[dc->ra], cpu_R[dc->rb]);
1539 break;
1540 case 1:
1541 gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
1542 cpu_R[dc->ra], cpu_R[dc->rb]);
1543 break;
1544 case 2:
1545 gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
1546 cpu_R[dc->ra], cpu_R[dc->rb]);
1547 break;
1548 case 3:
1549 gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
1550 cpu_R[dc->ra], cpu_R[dc->rb]);
1551 break;
1552 case 4:
1553 gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
1554 cpu_R[dc->ra], cpu_R[dc->rb]);
1555 break;
1556 case 5:
1557 gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
1558 cpu_R[dc->ra], cpu_R[dc->rb]);
1559 break;
1560 case 6:
1561 gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
1562 cpu_R[dc->ra], cpu_R[dc->rb]);
1563 break;
1564 default:
1565 qemu_log_mask(LOG_UNIMP,
1566 "unimplemented fcmp fpu_insn=%x pc=%x"
1567 " opc=%x\n",
1568 fpu_insn, dc->pc, dc->opcode);
1569 dc->abort_at_next_insn = 1;
1570 break;
1571 }
1572 break;
1573
1574 case 5:
1575 if (!dec_check_fpuv2(dc)) {
1576 return;
1577 }
1578 gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1579 break;
1580
1581 case 6:
1582 if (!dec_check_fpuv2(dc)) {
1583 return;
1584 }
1585 gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1586 break;
1587
1588 case 7:
1589 if (!dec_check_fpuv2(dc)) {
1590 return;
1591 }
1592 gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1593 break;
1594
1595 default:
1596 qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
1597 " opc=%x\n",
1598 fpu_insn, dc->pc, dc->opcode);
1599 dc->abort_at_next_insn = 1;
1600 break;
1601 }
1602 }
1603
1604 static void dec_null(DisasContext *dc)
1605 {
1606 if ((dc->tb_flags & MSR_EE_FLAG)
1607 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1608 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1609 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1610 return;
1611 }
1612 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1613 dc->abort_at_next_insn = 1;
1614 }
1615
1616 /* Insns connected to FSL or AXI stream attached devices. */
1617 static void dec_stream(DisasContext *dc)
1618 {
1619 int mem_index = cpu_mmu_index(dc->env);
1620 TCGv_i32 t_id, t_ctrl;
1621 int ctrl;
1622
1623 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1624 dc->type_b ? "" : "d", dc->imm);
1625
1626 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1627 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1628 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1629 return;
1630 }
1631
1632 t_id = tcg_temp_new();
1633 if (dc->type_b) {
1634 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1635 ctrl = dc->imm >> 10;
1636 } else {
1637 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1638 ctrl = dc->imm >> 5;
1639 }
1640
1641 t_ctrl = tcg_const_tl(ctrl);
1642
1643 if (dc->rd == 0) {
1644 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1645 } else {
1646 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1647 }
1648 tcg_temp_free(t_id);
1649 tcg_temp_free(t_ctrl);
1650 }
1651
1652 static struct decoder_info {
1653 struct {
1654 uint32_t bits;
1655 uint32_t mask;
1656 };
1657 void (*dec)(DisasContext *dc);
1658 } decinfo[] = {
1659 {DEC_ADD, dec_add},
1660 {DEC_SUB, dec_sub},
1661 {DEC_AND, dec_and},
1662 {DEC_XOR, dec_xor},
1663 {DEC_OR, dec_or},
1664 {DEC_BIT, dec_bit},
1665 {DEC_BARREL, dec_barrel},
1666 {DEC_LD, dec_load},
1667 {DEC_ST, dec_store},
1668 {DEC_IMM, dec_imm},
1669 {DEC_BR, dec_br},
1670 {DEC_BCC, dec_bcc},
1671 {DEC_RTS, dec_rts},
1672 {DEC_FPU, dec_fpu},
1673 {DEC_MUL, dec_mul},
1674 {DEC_DIV, dec_div},
1675 {DEC_MSR, dec_msr},
1676 {DEC_STREAM, dec_stream},
1677 {{0, 0}, dec_null}
1678 };
1679
1680 static inline void decode(DisasContext *dc, uint32_t ir)
1681 {
1682 int i;
1683
1684 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1685 tcg_gen_debug_insn_start(dc->pc);
1686 }
1687
1688 dc->ir = ir;
1689 LOG_DIS("%8.8x\t", dc->ir);
1690
1691 if (dc->ir)
1692 dc->nr_nops = 0;
1693 else {
1694 if ((dc->tb_flags & MSR_EE_FLAG)
1695 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1696 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1697 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1698 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1699 return;
1700 }
1701
1702 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1703 dc->nr_nops++;
1704 if (dc->nr_nops > 4)
1705 cpu_abort(dc->env, "fetching nop sequence\n");
1706 }
1707 /* bit 2 seems to indicate insn type. */
1708 dc->type_b = ir & (1 << 29);
1709
1710 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1711 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1712 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1713 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1714 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1715
1716 /* Large switch for all insns. */
1717 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1718 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1719 decinfo[i].dec(dc);
1720 break;
1721 }
1722 }
1723 }
1724
1725 static void check_breakpoint(CPUMBState *env, DisasContext *dc)
1726 {
1727 CPUBreakpoint *bp;
1728
1729 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1730 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1731 if (bp->pc == dc->pc) {
1732 t_gen_raise_exception(dc, EXCP_DEBUG);
1733 dc->is_jmp = DISAS_UPDATE;
1734 }
1735 }
1736 }
1737 }
1738
1739 /* generate intermediate code for basic block 'tb'. */
1740 static void
1741 gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
1742 int search_pc)
1743 {
1744 uint16_t *gen_opc_end;
1745 uint32_t pc_start;
1746 int j, lj;
1747 struct DisasContext ctx;
1748 struct DisasContext *dc = &ctx;
1749 uint32_t next_page_start, org_flags;
1750 target_ulong npc;
1751 int num_insns;
1752 int max_insns;
1753
1754 pc_start = tb->pc;
1755 dc->env = env;
1756 dc->tb = tb;
1757 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1758
1759 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1760
1761 dc->is_jmp = DISAS_NEXT;
1762 dc->jmp = 0;
1763 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1764 if (dc->delayed_branch) {
1765 dc->jmp = JMP_INDIRECT;
1766 }
1767 dc->pc = pc_start;
1768 dc->singlestep_enabled = env->singlestep_enabled;
1769 dc->cpustate_changed = 0;
1770 dc->abort_at_next_insn = 0;
1771 dc->nr_nops = 0;
1772
1773 if (pc_start & 3)
1774 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1775
1776 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1777 #if !SIM_COMPAT
1778 qemu_log("--------------\n");
1779 log_cpu_state(env, 0);
1780 #endif
1781 }
1782
1783 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1784 lj = -1;
1785 num_insns = 0;
1786 max_insns = tb->cflags & CF_COUNT_MASK;
1787 if (max_insns == 0)
1788 max_insns = CF_COUNT_MASK;
1789
1790 gen_tb_start();
1791 do
1792 {
1793 #if SIM_COMPAT
1794 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1795 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1796 gen_helper_debug();
1797 }
1798 #endif
1799 check_breakpoint(env, dc);
1800
1801 if (search_pc) {
1802 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1803 if (lj < j) {
1804 lj++;
1805 while (lj < j)
1806 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1807 }
1808 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1809 tcg_ctx.gen_opc_instr_start[lj] = 1;
1810 tcg_ctx.gen_opc_icount[lj] = num_insns;
1811 }
1812
1813 /* Pretty disas. */
1814 LOG_DIS("%8.8x:\t", dc->pc);
1815
1816 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1817 gen_io_start();
1818
1819 dc->clear_imm = 1;
1820 decode(dc, cpu_ldl_code(env, dc->pc));
1821 if (dc->clear_imm)
1822 dc->tb_flags &= ~IMM_FLAG;
1823 dc->pc += 4;
1824 num_insns++;
1825
1826 if (dc->delayed_branch) {
1827 dc->delayed_branch--;
1828 if (!dc->delayed_branch) {
1829 if (dc->tb_flags & DRTI_FLAG)
1830 do_rti(dc);
1831 if (dc->tb_flags & DRTB_FLAG)
1832 do_rtb(dc);
1833 if (dc->tb_flags & DRTE_FLAG)
1834 do_rte(dc);
1835 /* Clear the delay slot flag. */
1836 dc->tb_flags &= ~D_FLAG;
1837 /* If it is a direct jump, try direct chaining. */
1838 if (dc->jmp == JMP_INDIRECT) {
1839 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1840 dc->is_jmp = DISAS_JUMP;
1841 } else if (dc->jmp == JMP_DIRECT) {
1842 t_sync_flags(dc);
1843 gen_goto_tb(dc, 0, dc->jmp_pc);
1844 dc->is_jmp = DISAS_TB_JUMP;
1845 } else if (dc->jmp == JMP_DIRECT_CC) {
1846 int l1;
1847
1848 t_sync_flags(dc);
1849 l1 = gen_new_label();
1850 /* Conditional jmp. */
1851 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1852 gen_goto_tb(dc, 1, dc->pc);
1853 gen_set_label(l1);
1854 gen_goto_tb(dc, 0, dc->jmp_pc);
1855
1856 dc->is_jmp = DISAS_TB_JUMP;
1857 }
1858 break;
1859 }
1860 }
1861 if (env->singlestep_enabled)
1862 break;
1863 } while (!dc->is_jmp && !dc->cpustate_changed
1864 && tcg_ctx.gen_opc_ptr < gen_opc_end
1865 && !singlestep
1866 && (dc->pc < next_page_start)
1867 && num_insns < max_insns);
1868
1869 npc = dc->pc;
1870 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1871 if (dc->tb_flags & D_FLAG) {
1872 dc->is_jmp = DISAS_UPDATE;
1873 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1874 sync_jmpstate(dc);
1875 } else
1876 npc = dc->jmp_pc;
1877 }
1878
1879 if (tb->cflags & CF_LAST_IO)
1880 gen_io_end();
1881 /* Force an update if the per-tb cpu state has changed. */
1882 if (dc->is_jmp == DISAS_NEXT
1883 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1884 dc->is_jmp = DISAS_UPDATE;
1885 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1886 }
1887 t_sync_flags(dc);
1888
1889 if (unlikely(env->singlestep_enabled)) {
1890 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1891
1892 if (dc->is_jmp != DISAS_JUMP) {
1893 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1894 }
1895 gen_helper_raise_exception(cpu_env, tmp);
1896 tcg_temp_free_i32(tmp);
1897 } else {
1898 switch(dc->is_jmp) {
1899 case DISAS_NEXT:
1900 gen_goto_tb(dc, 1, npc);
1901 break;
1902 default:
1903 case DISAS_JUMP:
1904 case DISAS_UPDATE:
1905 /* indicate that the hash table must be used
1906 to find the next TB */
1907 tcg_gen_exit_tb(0);
1908 break;
1909 case DISAS_TB_JUMP:
1910 /* nothing more to generate */
1911 break;
1912 }
1913 }
1914 gen_tb_end(tb, num_insns);
1915 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1916 if (search_pc) {
1917 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1918 lj++;
1919 while (lj <= j)
1920 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1921 } else {
1922 tb->size = dc->pc - pc_start;
1923 tb->icount = num_insns;
1924 }
1925
1926 #ifdef DEBUG_DISAS
1927 #if !SIM_COMPAT
1928 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1929 qemu_log("\n");
1930 #if DISAS_GNU
1931 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
1932 #endif
1933 qemu_log("\nisize=%d osize=%td\n",
1934 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1935 tcg_ctx.gen_opc_buf);
1936 }
1937 #endif
1938 #endif
1939 assert(!dc->abort_at_next_insn);
1940 }
1941
1942 void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
1943 {
1944 gen_intermediate_code_internal(env, tb, 0);
1945 }
1946
1947 void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
1948 {
1949 gen_intermediate_code_internal(env, tb, 1);
1950 }
1951
1952 void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1953 int flags)
1954 {
1955 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
1956 CPUMBState *env = &cpu->env;
1957 int i;
1958
1959 if (!env || !f)
1960 return;
1961
1962 cpu_fprintf(f, "IN: PC=%x %s\n",
1963 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1964 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1965 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1966 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1967 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1968 env->btaken, env->btarget,
1969 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1970 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1971 (env->sregs[SR_MSR] & MSR_EIP),
1972 (env->sregs[SR_MSR] & MSR_IE));
1973
1974 for (i = 0; i < 32; i++) {
1975 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1976 if ((i + 1) % 4 == 0)
1977 cpu_fprintf(f, "\n");
1978 }
1979 cpu_fprintf(f, "\n\n");
1980 }
1981
1982 MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
1983 {
1984 MicroBlazeCPU *cpu;
1985
1986 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
1987
1988 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1989
1990 return cpu;
1991 }
1992
1993 void mb_tcg_init(void)
1994 {
1995 int i;
1996
1997 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1998
1999 env_debug = tcg_global_mem_new(TCG_AREG0,
2000 offsetof(CPUMBState, debug),
2001 "debug0");
2002 env_iflags = tcg_global_mem_new(TCG_AREG0,
2003 offsetof(CPUMBState, iflags),
2004 "iflags");
2005 env_imm = tcg_global_mem_new(TCG_AREG0,
2006 offsetof(CPUMBState, imm),
2007 "imm");
2008 env_btarget = tcg_global_mem_new(TCG_AREG0,
2009 offsetof(CPUMBState, btarget),
2010 "btarget");
2011 env_btaken = tcg_global_mem_new(TCG_AREG0,
2012 offsetof(CPUMBState, btaken),
2013 "btaken");
2014 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
2015 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
2016 offsetof(CPUMBState, regs[i]),
2017 regnames[i]);
2018 }
2019 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
2020 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
2021 offsetof(CPUMBState, sregs[i]),
2022 special_regnames[i]);
2023 }
2024 #define GEN_HELPER 2
2025 #include "helper.h"
2026 }
2027
2028 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
2029 {
2030 env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos];
2031 }