cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / target-mips / cpu.h
1 #if !defined (__MIPS_CPU_H__)
2 #define __MIPS_CPU_H__
3
4 //#define DEBUG_OP
5
6 #define TARGET_HAS_ICE 1
7
8 #define ELF_MACHINE EM_MIPS
9
10 #define CPUArchState struct CPUMIPSState
11
12 #include "config.h"
13 #include "qemu-common.h"
14 #include "mips-defs.h"
15 #include "exec/cpu-defs.h"
16 #include "fpu/softfloat.h"
17
18 struct CPUMIPSState;
19
20 typedef struct r4k_tlb_t r4k_tlb_t;
21 struct r4k_tlb_t {
22 target_ulong VPN;
23 uint32_t PageMask;
24 uint_fast8_t ASID;
25 uint_fast16_t G:1;
26 uint_fast16_t C0:3;
27 uint_fast16_t C1:3;
28 uint_fast16_t V0:1;
29 uint_fast16_t V1:1;
30 uint_fast16_t D0:1;
31 uint_fast16_t D1:1;
32 target_ulong PFN[2];
33 };
34
35 #if !defined(CONFIG_USER_ONLY)
36 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
37 struct CPUMIPSTLBContext {
38 uint32_t nb_tlb;
39 uint32_t tlb_in_use;
40 int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
41 void (*helper_tlbwi)(struct CPUMIPSState *env);
42 void (*helper_tlbwr)(struct CPUMIPSState *env);
43 void (*helper_tlbp)(struct CPUMIPSState *env);
44 void (*helper_tlbr)(struct CPUMIPSState *env);
45 union {
46 struct {
47 r4k_tlb_t tlb[MIPS_TLB_MAX];
48 } r4k;
49 } mmu;
50 };
51 #endif
52
53 typedef union fpr_t fpr_t;
54 union fpr_t {
55 float64 fd; /* ieee double precision */
56 float32 fs[2];/* ieee single precision */
57 uint64_t d; /* binary double fixed-point */
58 uint32_t w[2]; /* binary single fixed-point */
59 };
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianness
62 */
63 #if defined(HOST_WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
65 #else
66 # define FP_ENDIAN_IDX 0
67 #endif
68
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70 struct CPUMIPSFPUContext {
71 /* Floating point registers */
72 fpr_t fpr[32];
73 float_status fp_status;
74 /* fpu implementation/revision register (fir) */
75 uint32_t fcr0;
76 #define FCR0_F64 22
77 #define FCR0_L 21
78 #define FCR0_W 20
79 #define FCR0_3D 19
80 #define FCR0_PS 18
81 #define FCR0_D 17
82 #define FCR0_S 16
83 #define FCR0_PRID 8
84 #define FCR0_REV 0
85 /* fcsr */
86 uint32_t fcr31;
87 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
88 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
90 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
91 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
92 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
93 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
94 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
95 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
96 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
97 #define FP_INEXACT 1
98 #define FP_UNDERFLOW 2
99 #define FP_OVERFLOW 4
100 #define FP_DIV0 8
101 #define FP_INVALID 16
102 #define FP_UNIMPLEMENTED 32
103 };
104
105 #define NB_MMU_MODES 3
106
107 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
108 struct CPUMIPSMVPContext {
109 int32_t CP0_MVPControl;
110 #define CP0MVPCo_CPA 3
111 #define CP0MVPCo_STLB 2
112 #define CP0MVPCo_VPC 1
113 #define CP0MVPCo_EVP 0
114 int32_t CP0_MVPConf0;
115 #define CP0MVPC0_M 31
116 #define CP0MVPC0_TLBS 29
117 #define CP0MVPC0_GS 28
118 #define CP0MVPC0_PCP 27
119 #define CP0MVPC0_PTLBE 16
120 #define CP0MVPC0_TCA 15
121 #define CP0MVPC0_PVPE 10
122 #define CP0MVPC0_PTC 0
123 int32_t CP0_MVPConf1;
124 #define CP0MVPC1_CIM 31
125 #define CP0MVPC1_CIF 30
126 #define CP0MVPC1_PCX 20
127 #define CP0MVPC1_PCP2 10
128 #define CP0MVPC1_PCP1 0
129 };
130
131 typedef struct mips_def_t mips_def_t;
132
133 #define MIPS_SHADOW_SET_MAX 16
134 #define MIPS_TC_MAX 5
135 #define MIPS_FPU_MAX 1
136 #define MIPS_DSP_ACC 4
137
138 typedef struct TCState TCState;
139 struct TCState {
140 target_ulong gpr[32];
141 target_ulong PC;
142 target_ulong HI[MIPS_DSP_ACC];
143 target_ulong LO[MIPS_DSP_ACC];
144 target_ulong ACX[MIPS_DSP_ACC];
145 target_ulong DSPControl;
146 int32_t CP0_TCStatus;
147 #define CP0TCSt_TCU3 31
148 #define CP0TCSt_TCU2 30
149 #define CP0TCSt_TCU1 29
150 #define CP0TCSt_TCU0 28
151 #define CP0TCSt_TMX 27
152 #define CP0TCSt_RNST 23
153 #define CP0TCSt_TDS 21
154 #define CP0TCSt_DT 20
155 #define CP0TCSt_DA 15
156 #define CP0TCSt_A 13
157 #define CP0TCSt_TKSU 11
158 #define CP0TCSt_IXMT 10
159 #define CP0TCSt_TASID 0
160 int32_t CP0_TCBind;
161 #define CP0TCBd_CurTC 21
162 #define CP0TCBd_TBE 17
163 #define CP0TCBd_CurVPE 0
164 target_ulong CP0_TCHalt;
165 target_ulong CP0_TCContext;
166 target_ulong CP0_TCSchedule;
167 target_ulong CP0_TCScheFBack;
168 int32_t CP0_Debug_tcstatus;
169 };
170
171 typedef struct CPUMIPSState CPUMIPSState;
172 struct CPUMIPSState {
173 TCState active_tc;
174 CPUMIPSFPUContext active_fpu;
175
176 uint32_t current_tc;
177 uint32_t current_fpu;
178
179 uint32_t SEGBITS;
180 uint32_t PABITS;
181 target_ulong SEGMask;
182 target_ulong PAMask;
183
184 int32_t CP0_Index;
185 /* CP0_MVP* are per MVP registers. */
186 int32_t CP0_Random;
187 int32_t CP0_VPEControl;
188 #define CP0VPECo_YSI 21
189 #define CP0VPECo_GSI 20
190 #define CP0VPECo_EXCPT 16
191 #define CP0VPECo_TE 15
192 #define CP0VPECo_TargTC 0
193 int32_t CP0_VPEConf0;
194 #define CP0VPEC0_M 31
195 #define CP0VPEC0_XTC 21
196 #define CP0VPEC0_TCS 19
197 #define CP0VPEC0_SCS 18
198 #define CP0VPEC0_DSC 17
199 #define CP0VPEC0_ICS 16
200 #define CP0VPEC0_MVP 1
201 #define CP0VPEC0_VPA 0
202 int32_t CP0_VPEConf1;
203 #define CP0VPEC1_NCX 20
204 #define CP0VPEC1_NCP2 10
205 #define CP0VPEC1_NCP1 0
206 target_ulong CP0_YQMask;
207 target_ulong CP0_VPESchedule;
208 target_ulong CP0_VPEScheFBack;
209 int32_t CP0_VPEOpt;
210 #define CP0VPEOpt_IWX7 15
211 #define CP0VPEOpt_IWX6 14
212 #define CP0VPEOpt_IWX5 13
213 #define CP0VPEOpt_IWX4 12
214 #define CP0VPEOpt_IWX3 11
215 #define CP0VPEOpt_IWX2 10
216 #define CP0VPEOpt_IWX1 9
217 #define CP0VPEOpt_IWX0 8
218 #define CP0VPEOpt_DWX7 7
219 #define CP0VPEOpt_DWX6 6
220 #define CP0VPEOpt_DWX5 5
221 #define CP0VPEOpt_DWX4 4
222 #define CP0VPEOpt_DWX3 3
223 #define CP0VPEOpt_DWX2 2
224 #define CP0VPEOpt_DWX1 1
225 #define CP0VPEOpt_DWX0 0
226 target_ulong CP0_EntryLo0;
227 target_ulong CP0_EntryLo1;
228 target_ulong CP0_Context;
229 int32_t CP0_PageMask;
230 int32_t CP0_PageGrain;
231 int32_t CP0_Wired;
232 int32_t CP0_SRSConf0_rw_bitmask;
233 int32_t CP0_SRSConf0;
234 #define CP0SRSC0_M 31
235 #define CP0SRSC0_SRS3 20
236 #define CP0SRSC0_SRS2 10
237 #define CP0SRSC0_SRS1 0
238 int32_t CP0_SRSConf1_rw_bitmask;
239 int32_t CP0_SRSConf1;
240 #define CP0SRSC1_M 31
241 #define CP0SRSC1_SRS6 20
242 #define CP0SRSC1_SRS5 10
243 #define CP0SRSC1_SRS4 0
244 int32_t CP0_SRSConf2_rw_bitmask;
245 int32_t CP0_SRSConf2;
246 #define CP0SRSC2_M 31
247 #define CP0SRSC2_SRS9 20
248 #define CP0SRSC2_SRS8 10
249 #define CP0SRSC2_SRS7 0
250 int32_t CP0_SRSConf3_rw_bitmask;
251 int32_t CP0_SRSConf3;
252 #define CP0SRSC3_M 31
253 #define CP0SRSC3_SRS12 20
254 #define CP0SRSC3_SRS11 10
255 #define CP0SRSC3_SRS10 0
256 int32_t CP0_SRSConf4_rw_bitmask;
257 int32_t CP0_SRSConf4;
258 #define CP0SRSC4_SRS15 20
259 #define CP0SRSC4_SRS14 10
260 #define CP0SRSC4_SRS13 0
261 int32_t CP0_HWREna;
262 target_ulong CP0_BadVAddr;
263 int32_t CP0_Count;
264 target_ulong CP0_EntryHi;
265 int32_t CP0_Compare;
266 int32_t CP0_Status;
267 #define CP0St_CU3 31
268 #define CP0St_CU2 30
269 #define CP0St_CU1 29
270 #define CP0St_CU0 28
271 #define CP0St_RP 27
272 #define CP0St_FR 26
273 #define CP0St_RE 25
274 #define CP0St_MX 24
275 #define CP0St_PX 23
276 #define CP0St_BEV 22
277 #define CP0St_TS 21
278 #define CP0St_SR 20
279 #define CP0St_NMI 19
280 #define CP0St_IM 8
281 #define CP0St_KX 7
282 #define CP0St_SX 6
283 #define CP0St_UX 5
284 #define CP0St_KSU 3
285 #define CP0St_ERL 2
286 #define CP0St_EXL 1
287 #define CP0St_IE 0
288 int32_t CP0_IntCtl;
289 #define CP0IntCtl_IPTI 29
290 #define CP0IntCtl_IPPC1 26
291 #define CP0IntCtl_VS 5
292 int32_t CP0_SRSCtl;
293 #define CP0SRSCtl_HSS 26
294 #define CP0SRSCtl_EICSS 18
295 #define CP0SRSCtl_ESS 12
296 #define CP0SRSCtl_PSS 6
297 #define CP0SRSCtl_CSS 0
298 int32_t CP0_SRSMap;
299 #define CP0SRSMap_SSV7 28
300 #define CP0SRSMap_SSV6 24
301 #define CP0SRSMap_SSV5 20
302 #define CP0SRSMap_SSV4 16
303 #define CP0SRSMap_SSV3 12
304 #define CP0SRSMap_SSV2 8
305 #define CP0SRSMap_SSV1 4
306 #define CP0SRSMap_SSV0 0
307 int32_t CP0_Cause;
308 #define CP0Ca_BD 31
309 #define CP0Ca_TI 30
310 #define CP0Ca_CE 28
311 #define CP0Ca_DC 27
312 #define CP0Ca_PCI 26
313 #define CP0Ca_IV 23
314 #define CP0Ca_WP 22
315 #define CP0Ca_IP 8
316 #define CP0Ca_IP_mask 0x0000FF00
317 #define CP0Ca_EC 2
318 target_ulong CP0_EPC;
319 int32_t CP0_PRid;
320 int32_t CP0_EBase;
321 int32_t CP0_Config0;
322 #define CP0C0_M 31
323 #define CP0C0_K23 28
324 #define CP0C0_KU 25
325 #define CP0C0_MDU 20
326 #define CP0C0_MM 17
327 #define CP0C0_BM 16
328 #define CP0C0_BE 15
329 #define CP0C0_AT 13
330 #define CP0C0_AR 10
331 #define CP0C0_MT 7
332 #define CP0C0_VI 3
333 #define CP0C0_K0 0
334 int32_t CP0_Config1;
335 #define CP0C1_M 31
336 #define CP0C1_MMU 25
337 #define CP0C1_IS 22
338 #define CP0C1_IL 19
339 #define CP0C1_IA 16
340 #define CP0C1_DS 13
341 #define CP0C1_DL 10
342 #define CP0C1_DA 7
343 #define CP0C1_C2 6
344 #define CP0C1_MD 5
345 #define CP0C1_PC 4
346 #define CP0C1_WR 3
347 #define CP0C1_CA 2
348 #define CP0C1_EP 1
349 #define CP0C1_FP 0
350 int32_t CP0_Config2;
351 #define CP0C2_M 31
352 #define CP0C2_TU 28
353 #define CP0C2_TS 24
354 #define CP0C2_TL 20
355 #define CP0C2_TA 16
356 #define CP0C2_SU 12
357 #define CP0C2_SS 8
358 #define CP0C2_SL 4
359 #define CP0C2_SA 0
360 int32_t CP0_Config3;
361 #define CP0C3_M 31
362 #define CP0C3_ISA_ON_EXC 16
363 #define CP0C3_DSPP 10
364 #define CP0C3_LPA 7
365 #define CP0C3_VEIC 6
366 #define CP0C3_VInt 5
367 #define CP0C3_SP 4
368 #define CP0C3_MT 2
369 #define CP0C3_SM 1
370 #define CP0C3_TL 0
371 int32_t CP0_Config6;
372 int32_t CP0_Config7;
373 /* XXX: Maybe make LLAddr per-TC? */
374 target_ulong lladdr;
375 target_ulong llval;
376 target_ulong llnewval;
377 target_ulong llreg;
378 target_ulong CP0_LLAddr_rw_bitmask;
379 int CP0_LLAddr_shift;
380 target_ulong CP0_WatchLo[8];
381 int32_t CP0_WatchHi[8];
382 target_ulong CP0_XContext;
383 int32_t CP0_Framemask;
384 int32_t CP0_Debug;
385 #define CP0DB_DBD 31
386 #define CP0DB_DM 30
387 #define CP0DB_LSNM 28
388 #define CP0DB_Doze 27
389 #define CP0DB_Halt 26
390 #define CP0DB_CNT 25
391 #define CP0DB_IBEP 24
392 #define CP0DB_DBEP 21
393 #define CP0DB_IEXI 20
394 #define CP0DB_VER 15
395 #define CP0DB_DEC 10
396 #define CP0DB_SSt 8
397 #define CP0DB_DINT 5
398 #define CP0DB_DIB 4
399 #define CP0DB_DDBS 3
400 #define CP0DB_DDBL 2
401 #define CP0DB_DBp 1
402 #define CP0DB_DSS 0
403 target_ulong CP0_DEPC;
404 int32_t CP0_Performance0;
405 int32_t CP0_TagLo;
406 int32_t CP0_DataLo;
407 int32_t CP0_TagHi;
408 int32_t CP0_DataHi;
409 target_ulong CP0_ErrorEPC;
410 int32_t CP0_DESAVE;
411 /* We waste some space so we can handle shadow registers like TCs. */
412 TCState tcs[MIPS_SHADOW_SET_MAX];
413 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
414 /* QEMU */
415 int error_code;
416 uint32_t hflags; /* CPU State */
417 /* TMASK defines different execution modes */
418 #define MIPS_HFLAG_TMASK 0xC07FF
419 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
420 /* The KSU flags must be the lowest bits in hflags. The flag order
421 must be the same as defined for CP0 Status. This allows to use
422 the bits as the value of mmu_idx. */
423 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
424 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
425 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
426 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
427 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
428 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
429 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
430 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
431 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
432 /* True if the MIPS IV COP1X instructions can be used. This also
433 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
434 and RSQRT.D. */
435 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
436 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
437 #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
438 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
439 #define MIPS_HFLAG_M16_SHIFT 10
440 /* If translation is interrupted between the branch instruction and
441 * the delay slot, record what type of branch it is so that we can
442 * resume translation properly. It might be possible to reduce
443 * this from three bits to two. */
444 #define MIPS_HFLAG_BMASK_BASE 0x03800
445 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
446 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
447 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
448 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
449 /* Extra flags about the current pending branch. */
450 #define MIPS_HFLAG_BMASK_EXT 0x3C000
451 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
452 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
453 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
454 #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
455 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
456 /* MIPS DSP resources access. */
457 #define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */
458 #define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */
459 target_ulong btarget; /* Jump / branch target */
460 target_ulong bcond; /* Branch condition (if needed) */
461
462 int SYNCI_Step; /* Address step size for SYNCI */
463 int CCRes; /* Cycle count resolution/divisor */
464 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
465 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
466 int insn_flags; /* Supported instruction set */
467
468 target_ulong tls_value; /* For usermode emulation */
469
470 CPU_COMMON
471
472 CPUMIPSMVPContext *mvp;
473 #if !defined(CONFIG_USER_ONLY)
474 CPUMIPSTLBContext *tlb;
475 #endif
476
477 const mips_def_t *cpu_model;
478 void *irq[8];
479 struct QEMUTimer *timer; /* Internal timer */
480 };
481
482 #include "cpu-qom.h"
483
484 #if !defined(CONFIG_USER_ONLY)
485 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
486 target_ulong address, int rw, int access_type);
487 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
488 target_ulong address, int rw, int access_type);
489 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
490 target_ulong address, int rw, int access_type);
491 void r4k_helper_tlbwi(CPUMIPSState *env);
492 void r4k_helper_tlbwr(CPUMIPSState *env);
493 void r4k_helper_tlbp(CPUMIPSState *env);
494 void r4k_helper_tlbr(CPUMIPSState *env);
495
496 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
497 int is_write, int is_exec, int unused, int size);
498 #endif
499
500 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
501
502 #define cpu_exec cpu_mips_exec
503 #define cpu_gen_code cpu_mips_gen_code
504 #define cpu_signal_handler cpu_mips_signal_handler
505 #define cpu_list mips_cpu_list
506
507 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
508 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
509
510 #define CPU_SAVE_VERSION 3
511
512 /* MMU modes definitions. We carefully match the indices with our
513 hflags layout. */
514 #define MMU_MODE0_SUFFIX _kernel
515 #define MMU_MODE1_SUFFIX _super
516 #define MMU_MODE2_SUFFIX _user
517 #define MMU_USER_IDX 2
518 static inline int cpu_mmu_index (CPUMIPSState *env)
519 {
520 return env->hflags & MIPS_HFLAG_KSU;
521 }
522
523 static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp)
524 {
525 if (newsp)
526 env->active_tc.gpr[29] = newsp;
527 env->active_tc.gpr[7] = 0;
528 env->active_tc.gpr[2] = 0;
529 }
530
531 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
532 {
533 int32_t pending;
534 int32_t status;
535 int r;
536
537 if (!(env->CP0_Status & (1 << CP0St_IE)) ||
538 (env->CP0_Status & (1 << CP0St_EXL)) ||
539 (env->CP0_Status & (1 << CP0St_ERL)) ||
540 /* Note that the TCStatus IXMT field is initialized to zero,
541 and only MT capable cores can set it to one. So we don't
542 need to check for MT capabilities here. */
543 (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
544 (env->hflags & MIPS_HFLAG_DM)) {
545 /* Interrupts are disabled */
546 return 0;
547 }
548
549 pending = env->CP0_Cause & CP0Ca_IP_mask;
550 status = env->CP0_Status & CP0Ca_IP_mask;
551
552 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
553 /* A MIPS configured with a vectorizing external interrupt controller
554 will feed a vector into the Cause pending lines. The core treats
555 the status lines as a vector level, not as indiviual masks. */
556 r = pending > status;
557 } else {
558 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
559 treats the pending lines as individual interrupt lines, the status
560 lines are individual masks. */
561 r = pending & status;
562 }
563 return r;
564 }
565
566 #include "exec/cpu-all.h"
567
568 /* Memory access type :
569 * may be needed for precise access rights control and precise exceptions.
570 */
571 enum {
572 /* 1 bit to define user level / supervisor access */
573 ACCESS_USER = 0x00,
574 ACCESS_SUPER = 0x01,
575 /* 1 bit to indicate direction */
576 ACCESS_STORE = 0x02,
577 /* Type of instruction that generated the access */
578 ACCESS_CODE = 0x10, /* Code fetch access */
579 ACCESS_INT = 0x20, /* Integer load/store access */
580 ACCESS_FLOAT = 0x30, /* floating point load/store access */
581 };
582
583 /* Exceptions */
584 enum {
585 EXCP_NONE = -1,
586 EXCP_RESET = 0,
587 EXCP_SRESET,
588 EXCP_DSS,
589 EXCP_DINT,
590 EXCP_DDBL,
591 EXCP_DDBS,
592 EXCP_NMI,
593 EXCP_MCHECK,
594 EXCP_EXT_INTERRUPT, /* 8 */
595 EXCP_DFWATCH,
596 EXCP_DIB,
597 EXCP_IWATCH,
598 EXCP_AdEL,
599 EXCP_AdES,
600 EXCP_TLBF,
601 EXCP_IBE,
602 EXCP_DBp, /* 16 */
603 EXCP_SYSCALL,
604 EXCP_BREAK,
605 EXCP_CpU,
606 EXCP_RI,
607 EXCP_OVERFLOW,
608 EXCP_TRAP,
609 EXCP_FPE,
610 EXCP_DWATCH, /* 24 */
611 EXCP_LTLBL,
612 EXCP_TLBL,
613 EXCP_TLBS,
614 EXCP_DBE,
615 EXCP_THREAD,
616 EXCP_MDMX,
617 EXCP_C2E,
618 EXCP_CACHE, /* 32 */
619 EXCP_DSPDIS,
620
621 EXCP_LAST = EXCP_DSPDIS,
622 };
623 /* Dummy exception for conditional stores. */
624 #define EXCP_SC 0x100
625
626 /*
627 * This is an interrnally generated WAKE request line.
628 * It is driven by the CPU itself. Raised when the MT
629 * block wants to wake a VPE from an inactive state and
630 * cleared when VPE goes from active to inactive.
631 */
632 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
633
634 int cpu_mips_exec(CPUMIPSState *s);
635 void mips_tcg_init(void);
636 MIPSCPU *cpu_mips_init(const char *cpu_model);
637 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
638
639 static inline CPUMIPSState *cpu_init(const char *cpu_model)
640 {
641 MIPSCPU *cpu = cpu_mips_init(cpu_model);
642 if (cpu == NULL) {
643 return NULL;
644 }
645 return &cpu->env;
646 }
647
648 /* TODO QOM'ify CPU reset and remove */
649 void cpu_state_reset(CPUMIPSState *s);
650
651 /* mips_timer.c */
652 uint32_t cpu_mips_get_random (CPUMIPSState *env);
653 uint32_t cpu_mips_get_count (CPUMIPSState *env);
654 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
655 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
656 void cpu_mips_start_count(CPUMIPSState *env);
657 void cpu_mips_stop_count(CPUMIPSState *env);
658
659 /* mips_int.c */
660 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
661
662 /* helper.c */
663 int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
664 int mmu_idx);
665 #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
666 void do_interrupt (CPUMIPSState *env);
667 #if !defined(CONFIG_USER_ONLY)
668 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
669 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
670 int rw);
671 #endif
672
673 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
674 target_ulong *cs_base, int *flags)
675 {
676 *pc = env->active_tc.PC;
677 *cs_base = 0;
678 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
679 }
680
681 static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls)
682 {
683 env->tls_value = newtls;
684 }
685
686 static inline int mips_vpe_active(CPUMIPSState *env)
687 {
688 int active = 1;
689
690 /* Check that the VPE is enabled. */
691 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
692 active = 0;
693 }
694 /* Check that the VPE is activated. */
695 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
696 active = 0;
697 }
698
699 /* Now verify that there are active thread contexts in the VPE.
700
701 This assumes the CPU model will internally reschedule threads
702 if the active one goes to sleep. If there are no threads available
703 the active one will be in a sleeping state, and we can turn off
704 the entire VPE. */
705 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
706 /* TC is not activated. */
707 active = 0;
708 }
709 if (env->active_tc.CP0_TCHalt & 1) {
710 /* TC is in halt state. */
711 active = 0;
712 }
713
714 return active;
715 }
716
717 static inline bool cpu_has_work(CPUState *cpu)
718 {
719 CPUMIPSState *env = &MIPS_CPU(cpu)->env;
720 bool has_work = false;
721
722 /* It is implementation dependent if non-enabled interrupts
723 wake-up the CPU, however most of the implementations only
724 check for interrupts that can be taken. */
725 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
726 cpu_mips_hw_interrupts_pending(env)) {
727 has_work = true;
728 }
729
730 /* MIPS-MT has the ability to halt the CPU. */
731 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
732 /* The QEMU model will issue an _WAKE request whenever the CPUs
733 should be woken up. */
734 if (cpu->interrupt_request & CPU_INTERRUPT_WAKE) {
735 has_work = true;
736 }
737
738 if (!mips_vpe_active(env)) {
739 has_work = false;
740 }
741 }
742 return has_work;
743 }
744
745 #include "exec/exec-all.h"
746
747 static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
748 {
749 env->active_tc.PC = tb->pc;
750 env->hflags &= ~MIPS_HFLAG_BMASK;
751 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
752 }
753
754 static inline void compute_hflags(CPUMIPSState *env)
755 {
756 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
757 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
758 MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
759 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
760 !(env->CP0_Status & (1 << CP0St_ERL)) &&
761 !(env->hflags & MIPS_HFLAG_DM)) {
762 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
763 }
764 #if defined(TARGET_MIPS64)
765 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
766 (env->CP0_Status & (1 << CP0St_PX)) ||
767 (env->CP0_Status & (1 << CP0St_UX))) {
768 env->hflags |= MIPS_HFLAG_64;
769 }
770 if (env->CP0_Status & (1 << CP0St_UX)) {
771 env->hflags |= MIPS_HFLAG_UX;
772 }
773 #endif
774 if ((env->CP0_Status & (1 << CP0St_CU0)) ||
775 !(env->hflags & MIPS_HFLAG_KSU)) {
776 env->hflags |= MIPS_HFLAG_CP0;
777 }
778 if (env->CP0_Status & (1 << CP0St_CU1)) {
779 env->hflags |= MIPS_HFLAG_FPU;
780 }
781 if (env->CP0_Status & (1 << CP0St_FR)) {
782 env->hflags |= MIPS_HFLAG_F64;
783 }
784 if (env->insn_flags & ASE_DSPR2) {
785 /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
786 so enable to access DSPR2 resources. */
787 if (env->CP0_Status & (1 << CP0St_MX)) {
788 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
789 }
790
791 } else if (env->insn_flags & ASE_DSP) {
792 /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
793 so enable to access DSP resources. */
794 if (env->CP0_Status & (1 << CP0St_MX)) {
795 env->hflags |= MIPS_HFLAG_DSP;
796 }
797
798 }
799 if (env->insn_flags & ISA_MIPS32R2) {
800 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
801 env->hflags |= MIPS_HFLAG_COP1X;
802 }
803 } else if (env->insn_flags & ISA_MIPS32) {
804 if (env->hflags & MIPS_HFLAG_64) {
805 env->hflags |= MIPS_HFLAG_COP1X;
806 }
807 } else if (env->insn_flags & ISA_MIPS4) {
808 /* All supported MIPS IV CPUs use the XX (CU3) to enable
809 and disable the MIPS IV extensions to the MIPS III ISA.
810 Some other MIPS IV CPUs ignore the bit, so the check here
811 would be too restrictive for them. */
812 if (env->CP0_Status & (1 << CP0St_CU3)) {
813 env->hflags |= MIPS_HFLAG_COP1X;
814 }
815 }
816 }
817
818 #endif /* !defined (__MIPS_CPU_H__) */