cpu: Move breakpoints field from CPU_COMMON to CPUState
[qemu.git] / target-mips / cpu.h
1 #if !defined (__MIPS_CPU_H__)
2 #define __MIPS_CPU_H__
3
4 //#define DEBUG_OP
5
6 #define TARGET_HAS_ICE 1
7
8 #define ELF_MACHINE EM_MIPS
9
10 #define CPUArchState struct CPUMIPSState
11
12 #include "config.h"
13 #include "qemu-common.h"
14 #include "mips-defs.h"
15 #include "exec/cpu-defs.h"
16 #include "fpu/softfloat.h"
17
18 struct CPUMIPSState;
19
20 typedef struct r4k_tlb_t r4k_tlb_t;
21 struct r4k_tlb_t {
22 target_ulong VPN;
23 uint32_t PageMask;
24 uint_fast8_t ASID;
25 uint_fast16_t G:1;
26 uint_fast16_t C0:3;
27 uint_fast16_t C1:3;
28 uint_fast16_t V0:1;
29 uint_fast16_t V1:1;
30 uint_fast16_t D0:1;
31 uint_fast16_t D1:1;
32 target_ulong PFN[2];
33 };
34
35 #if !defined(CONFIG_USER_ONLY)
36 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
37 struct CPUMIPSTLBContext {
38 uint32_t nb_tlb;
39 uint32_t tlb_in_use;
40 int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
41 void (*helper_tlbwi)(struct CPUMIPSState *env);
42 void (*helper_tlbwr)(struct CPUMIPSState *env);
43 void (*helper_tlbp)(struct CPUMIPSState *env);
44 void (*helper_tlbr)(struct CPUMIPSState *env);
45 union {
46 struct {
47 r4k_tlb_t tlb[MIPS_TLB_MAX];
48 } r4k;
49 } mmu;
50 };
51 #endif
52
53 typedef union fpr_t fpr_t;
54 union fpr_t {
55 float64 fd; /* ieee double precision */
56 float32 fs[2];/* ieee single precision */
57 uint64_t d; /* binary double fixed-point */
58 uint32_t w[2]; /* binary single fixed-point */
59 };
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianness
62 */
63 #if defined(HOST_WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
65 #else
66 # define FP_ENDIAN_IDX 0
67 #endif
68
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70 struct CPUMIPSFPUContext {
71 /* Floating point registers */
72 fpr_t fpr[32];
73 float_status fp_status;
74 /* fpu implementation/revision register (fir) */
75 uint32_t fcr0;
76 #define FCR0_UFRP 28
77 #define FCR0_F64 22
78 #define FCR0_L 21
79 #define FCR0_W 20
80 #define FCR0_3D 19
81 #define FCR0_PS 18
82 #define FCR0_D 17
83 #define FCR0_S 16
84 #define FCR0_PRID 8
85 #define FCR0_REV 0
86 /* fcsr */
87 uint32_t fcr31;
88 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
90 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
91 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
92 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
93 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
94 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
95 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
96 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
97 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
98 #define FP_INEXACT 1
99 #define FP_UNDERFLOW 2
100 #define FP_OVERFLOW 4
101 #define FP_DIV0 8
102 #define FP_INVALID 16
103 #define FP_UNIMPLEMENTED 32
104 };
105
106 #define NB_MMU_MODES 3
107
108 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
109 struct CPUMIPSMVPContext {
110 int32_t CP0_MVPControl;
111 #define CP0MVPCo_CPA 3
112 #define CP0MVPCo_STLB 2
113 #define CP0MVPCo_VPC 1
114 #define CP0MVPCo_EVP 0
115 int32_t CP0_MVPConf0;
116 #define CP0MVPC0_M 31
117 #define CP0MVPC0_TLBS 29
118 #define CP0MVPC0_GS 28
119 #define CP0MVPC0_PCP 27
120 #define CP0MVPC0_PTLBE 16
121 #define CP0MVPC0_TCA 15
122 #define CP0MVPC0_PVPE 10
123 #define CP0MVPC0_PTC 0
124 int32_t CP0_MVPConf1;
125 #define CP0MVPC1_CIM 31
126 #define CP0MVPC1_CIF 30
127 #define CP0MVPC1_PCX 20
128 #define CP0MVPC1_PCP2 10
129 #define CP0MVPC1_PCP1 0
130 };
131
132 typedef struct mips_def_t mips_def_t;
133
134 #define MIPS_SHADOW_SET_MAX 16
135 #define MIPS_TC_MAX 5
136 #define MIPS_FPU_MAX 1
137 #define MIPS_DSP_ACC 4
138
139 typedef struct TCState TCState;
140 struct TCState {
141 target_ulong gpr[32];
142 target_ulong PC;
143 target_ulong HI[MIPS_DSP_ACC];
144 target_ulong LO[MIPS_DSP_ACC];
145 target_ulong ACX[MIPS_DSP_ACC];
146 target_ulong DSPControl;
147 int32_t CP0_TCStatus;
148 #define CP0TCSt_TCU3 31
149 #define CP0TCSt_TCU2 30
150 #define CP0TCSt_TCU1 29
151 #define CP0TCSt_TCU0 28
152 #define CP0TCSt_TMX 27
153 #define CP0TCSt_RNST 23
154 #define CP0TCSt_TDS 21
155 #define CP0TCSt_DT 20
156 #define CP0TCSt_DA 15
157 #define CP0TCSt_A 13
158 #define CP0TCSt_TKSU 11
159 #define CP0TCSt_IXMT 10
160 #define CP0TCSt_TASID 0
161 int32_t CP0_TCBind;
162 #define CP0TCBd_CurTC 21
163 #define CP0TCBd_TBE 17
164 #define CP0TCBd_CurVPE 0
165 target_ulong CP0_TCHalt;
166 target_ulong CP0_TCContext;
167 target_ulong CP0_TCSchedule;
168 target_ulong CP0_TCScheFBack;
169 int32_t CP0_Debug_tcstatus;
170 };
171
172 typedef struct CPUMIPSState CPUMIPSState;
173 struct CPUMIPSState {
174 TCState active_tc;
175 CPUMIPSFPUContext active_fpu;
176
177 uint32_t current_tc;
178 uint32_t current_fpu;
179
180 uint32_t SEGBITS;
181 uint32_t PABITS;
182 target_ulong SEGMask;
183 target_ulong PAMask;
184
185 int32_t CP0_Index;
186 /* CP0_MVP* are per MVP registers. */
187 int32_t CP0_Random;
188 int32_t CP0_VPEControl;
189 #define CP0VPECo_YSI 21
190 #define CP0VPECo_GSI 20
191 #define CP0VPECo_EXCPT 16
192 #define CP0VPECo_TE 15
193 #define CP0VPECo_TargTC 0
194 int32_t CP0_VPEConf0;
195 #define CP0VPEC0_M 31
196 #define CP0VPEC0_XTC 21
197 #define CP0VPEC0_TCS 19
198 #define CP0VPEC0_SCS 18
199 #define CP0VPEC0_DSC 17
200 #define CP0VPEC0_ICS 16
201 #define CP0VPEC0_MVP 1
202 #define CP0VPEC0_VPA 0
203 int32_t CP0_VPEConf1;
204 #define CP0VPEC1_NCX 20
205 #define CP0VPEC1_NCP2 10
206 #define CP0VPEC1_NCP1 0
207 target_ulong CP0_YQMask;
208 target_ulong CP0_VPESchedule;
209 target_ulong CP0_VPEScheFBack;
210 int32_t CP0_VPEOpt;
211 #define CP0VPEOpt_IWX7 15
212 #define CP0VPEOpt_IWX6 14
213 #define CP0VPEOpt_IWX5 13
214 #define CP0VPEOpt_IWX4 12
215 #define CP0VPEOpt_IWX3 11
216 #define CP0VPEOpt_IWX2 10
217 #define CP0VPEOpt_IWX1 9
218 #define CP0VPEOpt_IWX0 8
219 #define CP0VPEOpt_DWX7 7
220 #define CP0VPEOpt_DWX6 6
221 #define CP0VPEOpt_DWX5 5
222 #define CP0VPEOpt_DWX4 4
223 #define CP0VPEOpt_DWX3 3
224 #define CP0VPEOpt_DWX2 2
225 #define CP0VPEOpt_DWX1 1
226 #define CP0VPEOpt_DWX0 0
227 target_ulong CP0_EntryLo0;
228 target_ulong CP0_EntryLo1;
229 target_ulong CP0_Context;
230 int32_t CP0_PageMask;
231 int32_t CP0_PageGrain;
232 int32_t CP0_Wired;
233 int32_t CP0_SRSConf0_rw_bitmask;
234 int32_t CP0_SRSConf0;
235 #define CP0SRSC0_M 31
236 #define CP0SRSC0_SRS3 20
237 #define CP0SRSC0_SRS2 10
238 #define CP0SRSC0_SRS1 0
239 int32_t CP0_SRSConf1_rw_bitmask;
240 int32_t CP0_SRSConf1;
241 #define CP0SRSC1_M 31
242 #define CP0SRSC1_SRS6 20
243 #define CP0SRSC1_SRS5 10
244 #define CP0SRSC1_SRS4 0
245 int32_t CP0_SRSConf2_rw_bitmask;
246 int32_t CP0_SRSConf2;
247 #define CP0SRSC2_M 31
248 #define CP0SRSC2_SRS9 20
249 #define CP0SRSC2_SRS8 10
250 #define CP0SRSC2_SRS7 0
251 int32_t CP0_SRSConf3_rw_bitmask;
252 int32_t CP0_SRSConf3;
253 #define CP0SRSC3_M 31
254 #define CP0SRSC3_SRS12 20
255 #define CP0SRSC3_SRS11 10
256 #define CP0SRSC3_SRS10 0
257 int32_t CP0_SRSConf4_rw_bitmask;
258 int32_t CP0_SRSConf4;
259 #define CP0SRSC4_SRS15 20
260 #define CP0SRSC4_SRS14 10
261 #define CP0SRSC4_SRS13 0
262 int32_t CP0_HWREna;
263 target_ulong CP0_BadVAddr;
264 int32_t CP0_Count;
265 target_ulong CP0_EntryHi;
266 int32_t CP0_Compare;
267 int32_t CP0_Status;
268 #define CP0St_CU3 31
269 #define CP0St_CU2 30
270 #define CP0St_CU1 29
271 #define CP0St_CU0 28
272 #define CP0St_RP 27
273 #define CP0St_FR 26
274 #define CP0St_RE 25
275 #define CP0St_MX 24
276 #define CP0St_PX 23
277 #define CP0St_BEV 22
278 #define CP0St_TS 21
279 #define CP0St_SR 20
280 #define CP0St_NMI 19
281 #define CP0St_IM 8
282 #define CP0St_KX 7
283 #define CP0St_SX 6
284 #define CP0St_UX 5
285 #define CP0St_KSU 3
286 #define CP0St_ERL 2
287 #define CP0St_EXL 1
288 #define CP0St_IE 0
289 int32_t CP0_IntCtl;
290 #define CP0IntCtl_IPTI 29
291 #define CP0IntCtl_IPPC1 26
292 #define CP0IntCtl_VS 5
293 int32_t CP0_SRSCtl;
294 #define CP0SRSCtl_HSS 26
295 #define CP0SRSCtl_EICSS 18
296 #define CP0SRSCtl_ESS 12
297 #define CP0SRSCtl_PSS 6
298 #define CP0SRSCtl_CSS 0
299 int32_t CP0_SRSMap;
300 #define CP0SRSMap_SSV7 28
301 #define CP0SRSMap_SSV6 24
302 #define CP0SRSMap_SSV5 20
303 #define CP0SRSMap_SSV4 16
304 #define CP0SRSMap_SSV3 12
305 #define CP0SRSMap_SSV2 8
306 #define CP0SRSMap_SSV1 4
307 #define CP0SRSMap_SSV0 0
308 int32_t CP0_Cause;
309 #define CP0Ca_BD 31
310 #define CP0Ca_TI 30
311 #define CP0Ca_CE 28
312 #define CP0Ca_DC 27
313 #define CP0Ca_PCI 26
314 #define CP0Ca_IV 23
315 #define CP0Ca_WP 22
316 #define CP0Ca_IP 8
317 #define CP0Ca_IP_mask 0x0000FF00
318 #define CP0Ca_EC 2
319 target_ulong CP0_EPC;
320 int32_t CP0_PRid;
321 int32_t CP0_EBase;
322 int32_t CP0_Config0;
323 #define CP0C0_M 31
324 #define CP0C0_K23 28
325 #define CP0C0_KU 25
326 #define CP0C0_MDU 20
327 #define CP0C0_MM 17
328 #define CP0C0_BM 16
329 #define CP0C0_BE 15
330 #define CP0C0_AT 13
331 #define CP0C0_AR 10
332 #define CP0C0_MT 7
333 #define CP0C0_VI 3
334 #define CP0C0_K0 0
335 int32_t CP0_Config1;
336 #define CP0C1_M 31
337 #define CP0C1_MMU 25
338 #define CP0C1_IS 22
339 #define CP0C1_IL 19
340 #define CP0C1_IA 16
341 #define CP0C1_DS 13
342 #define CP0C1_DL 10
343 #define CP0C1_DA 7
344 #define CP0C1_C2 6
345 #define CP0C1_MD 5
346 #define CP0C1_PC 4
347 #define CP0C1_WR 3
348 #define CP0C1_CA 2
349 #define CP0C1_EP 1
350 #define CP0C1_FP 0
351 int32_t CP0_Config2;
352 #define CP0C2_M 31
353 #define CP0C2_TU 28
354 #define CP0C2_TS 24
355 #define CP0C2_TL 20
356 #define CP0C2_TA 16
357 #define CP0C2_SU 12
358 #define CP0C2_SS 8
359 #define CP0C2_SL 4
360 #define CP0C2_SA 0
361 int32_t CP0_Config3;
362 #define CP0C3_M 31
363 #define CP0C3_ISA_ON_EXC 16
364 #define CP0C3_DSPP 10
365 #define CP0C3_LPA 7
366 #define CP0C3_VEIC 6
367 #define CP0C3_VInt 5
368 #define CP0C3_SP 4
369 #define CP0C3_MT 2
370 #define CP0C3_SM 1
371 #define CP0C3_TL 0
372 uint32_t CP0_Config4;
373 uint32_t CP0_Config4_rw_bitmask;
374 #define CP0C4_M 31
375 uint32_t CP0_Config5;
376 uint32_t CP0_Config5_rw_bitmask;
377 #define CP0C5_M 31
378 #define CP0C5_K 30
379 #define CP0C5_CV 29
380 #define CP0C5_EVA 28
381 #define CP0C5_MSAEn 27
382 #define CP0C5_UFR 2
383 #define CP0C5_NFExists 0
384 int32_t CP0_Config6;
385 int32_t CP0_Config7;
386 /* XXX: Maybe make LLAddr per-TC? */
387 target_ulong lladdr;
388 target_ulong llval;
389 target_ulong llnewval;
390 target_ulong llreg;
391 target_ulong CP0_LLAddr_rw_bitmask;
392 int CP0_LLAddr_shift;
393 target_ulong CP0_WatchLo[8];
394 int32_t CP0_WatchHi[8];
395 target_ulong CP0_XContext;
396 int32_t CP0_Framemask;
397 int32_t CP0_Debug;
398 #define CP0DB_DBD 31
399 #define CP0DB_DM 30
400 #define CP0DB_LSNM 28
401 #define CP0DB_Doze 27
402 #define CP0DB_Halt 26
403 #define CP0DB_CNT 25
404 #define CP0DB_IBEP 24
405 #define CP0DB_DBEP 21
406 #define CP0DB_IEXI 20
407 #define CP0DB_VER 15
408 #define CP0DB_DEC 10
409 #define CP0DB_SSt 8
410 #define CP0DB_DINT 5
411 #define CP0DB_DIB 4
412 #define CP0DB_DDBS 3
413 #define CP0DB_DDBL 2
414 #define CP0DB_DBp 1
415 #define CP0DB_DSS 0
416 target_ulong CP0_DEPC;
417 int32_t CP0_Performance0;
418 int32_t CP0_TagLo;
419 int32_t CP0_DataLo;
420 int32_t CP0_TagHi;
421 int32_t CP0_DataHi;
422 target_ulong CP0_ErrorEPC;
423 int32_t CP0_DESAVE;
424 /* We waste some space so we can handle shadow registers like TCs. */
425 TCState tcs[MIPS_SHADOW_SET_MAX];
426 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
427 /* QEMU */
428 int error_code;
429 uint32_t hflags; /* CPU State */
430 /* TMASK defines different execution modes */
431 #define MIPS_HFLAG_TMASK 0xC07FF
432 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
433 /* The KSU flags must be the lowest bits in hflags. The flag order
434 must be the same as defined for CP0 Status. This allows to use
435 the bits as the value of mmu_idx. */
436 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
437 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
438 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
439 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
440 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
441 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
442 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
443 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
444 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
445 /* True if the MIPS IV COP1X instructions can be used. This also
446 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
447 and RSQRT.D. */
448 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
449 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
450 #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
451 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
452 #define MIPS_HFLAG_M16_SHIFT 10
453 /* If translation is interrupted between the branch instruction and
454 * the delay slot, record what type of branch it is so that we can
455 * resume translation properly. It might be possible to reduce
456 * this from three bits to two. */
457 #define MIPS_HFLAG_BMASK_BASE 0x03800
458 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
459 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
460 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
461 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
462 /* Extra flags about the current pending branch. */
463 #define MIPS_HFLAG_BMASK_EXT 0x3C000
464 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
465 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
466 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
467 #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
468 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
469 /* MIPS DSP resources access. */
470 #define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */
471 #define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */
472 target_ulong btarget; /* Jump / branch target */
473 target_ulong bcond; /* Branch condition (if needed) */
474
475 int SYNCI_Step; /* Address step size for SYNCI */
476 int CCRes; /* Cycle count resolution/divisor */
477 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
478 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
479 int insn_flags; /* Supported instruction set */
480
481 target_ulong tls_value; /* For usermode emulation */
482
483 CPU_COMMON
484
485 /* Fields from here on are preserved across CPU reset. */
486 CPUMIPSMVPContext *mvp;
487 #if !defined(CONFIG_USER_ONLY)
488 CPUMIPSTLBContext *tlb;
489 #endif
490
491 const mips_def_t *cpu_model;
492 void *irq[8];
493 QEMUTimer *timer; /* Internal timer */
494 };
495
496 #include "cpu-qom.h"
497
498 #if !defined(CONFIG_USER_ONLY)
499 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
500 target_ulong address, int rw, int access_type);
501 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
502 target_ulong address, int rw, int access_type);
503 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
504 target_ulong address, int rw, int access_type);
505 void r4k_helper_tlbwi(CPUMIPSState *env);
506 void r4k_helper_tlbwr(CPUMIPSState *env);
507 void r4k_helper_tlbp(CPUMIPSState *env);
508 void r4k_helper_tlbr(CPUMIPSState *env);
509
510 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
511 bool is_write, bool is_exec, int unused,
512 unsigned size);
513 #endif
514
515 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
516
517 #define cpu_exec cpu_mips_exec
518 #define cpu_gen_code cpu_mips_gen_code
519 #define cpu_signal_handler cpu_mips_signal_handler
520 #define cpu_list mips_cpu_list
521
522 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
523 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
524
525 #define CPU_SAVE_VERSION 3
526
527 /* MMU modes definitions. We carefully match the indices with our
528 hflags layout. */
529 #define MMU_MODE0_SUFFIX _kernel
530 #define MMU_MODE1_SUFFIX _super
531 #define MMU_MODE2_SUFFIX _user
532 #define MMU_USER_IDX 2
533 static inline int cpu_mmu_index (CPUMIPSState *env)
534 {
535 return env->hflags & MIPS_HFLAG_KSU;
536 }
537
538 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
539 {
540 int32_t pending;
541 int32_t status;
542 int r;
543
544 if (!(env->CP0_Status & (1 << CP0St_IE)) ||
545 (env->CP0_Status & (1 << CP0St_EXL)) ||
546 (env->CP0_Status & (1 << CP0St_ERL)) ||
547 /* Note that the TCStatus IXMT field is initialized to zero,
548 and only MT capable cores can set it to one. So we don't
549 need to check for MT capabilities here. */
550 (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
551 (env->hflags & MIPS_HFLAG_DM)) {
552 /* Interrupts are disabled */
553 return 0;
554 }
555
556 pending = env->CP0_Cause & CP0Ca_IP_mask;
557 status = env->CP0_Status & CP0Ca_IP_mask;
558
559 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
560 /* A MIPS configured with a vectorizing external interrupt controller
561 will feed a vector into the Cause pending lines. The core treats
562 the status lines as a vector level, not as indiviual masks. */
563 r = pending > status;
564 } else {
565 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
566 treats the pending lines as individual interrupt lines, the status
567 lines are individual masks. */
568 r = pending & status;
569 }
570 return r;
571 }
572
573 #include "exec/cpu-all.h"
574
575 /* Memory access type :
576 * may be needed for precise access rights control and precise exceptions.
577 */
578 enum {
579 /* 1 bit to define user level / supervisor access */
580 ACCESS_USER = 0x00,
581 ACCESS_SUPER = 0x01,
582 /* 1 bit to indicate direction */
583 ACCESS_STORE = 0x02,
584 /* Type of instruction that generated the access */
585 ACCESS_CODE = 0x10, /* Code fetch access */
586 ACCESS_INT = 0x20, /* Integer load/store access */
587 ACCESS_FLOAT = 0x30, /* floating point load/store access */
588 };
589
590 /* Exceptions */
591 enum {
592 EXCP_NONE = -1,
593 EXCP_RESET = 0,
594 EXCP_SRESET,
595 EXCP_DSS,
596 EXCP_DINT,
597 EXCP_DDBL,
598 EXCP_DDBS,
599 EXCP_NMI,
600 EXCP_MCHECK,
601 EXCP_EXT_INTERRUPT, /* 8 */
602 EXCP_DFWATCH,
603 EXCP_DIB,
604 EXCP_IWATCH,
605 EXCP_AdEL,
606 EXCP_AdES,
607 EXCP_TLBF,
608 EXCP_IBE,
609 EXCP_DBp, /* 16 */
610 EXCP_SYSCALL,
611 EXCP_BREAK,
612 EXCP_CpU,
613 EXCP_RI,
614 EXCP_OVERFLOW,
615 EXCP_TRAP,
616 EXCP_FPE,
617 EXCP_DWATCH, /* 24 */
618 EXCP_LTLBL,
619 EXCP_TLBL,
620 EXCP_TLBS,
621 EXCP_DBE,
622 EXCP_THREAD,
623 EXCP_MDMX,
624 EXCP_C2E,
625 EXCP_CACHE, /* 32 */
626 EXCP_DSPDIS,
627
628 EXCP_LAST = EXCP_DSPDIS,
629 };
630 /* Dummy exception for conditional stores. */
631 #define EXCP_SC 0x100
632
633 /*
634 * This is an interrnally generated WAKE request line.
635 * It is driven by the CPU itself. Raised when the MT
636 * block wants to wake a VPE from an inactive state and
637 * cleared when VPE goes from active to inactive.
638 */
639 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
640
641 int cpu_mips_exec(CPUMIPSState *s);
642 void mips_tcg_init(void);
643 MIPSCPU *cpu_mips_init(const char *cpu_model);
644 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
645
646 static inline CPUMIPSState *cpu_init(const char *cpu_model)
647 {
648 MIPSCPU *cpu = cpu_mips_init(cpu_model);
649 if (cpu == NULL) {
650 return NULL;
651 }
652 return &cpu->env;
653 }
654
655 /* TODO QOM'ify CPU reset and remove */
656 void cpu_state_reset(CPUMIPSState *s);
657
658 /* mips_timer.c */
659 uint32_t cpu_mips_get_random (CPUMIPSState *env);
660 uint32_t cpu_mips_get_count (CPUMIPSState *env);
661 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
662 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
663 void cpu_mips_start_count(CPUMIPSState *env);
664 void cpu_mips_stop_count(CPUMIPSState *env);
665
666 /* mips_int.c */
667 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
668
669 /* helper.c */
670 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
671 int mmu_idx);
672 #if !defined(CONFIG_USER_ONLY)
673 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
674 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
675 int rw);
676 #endif
677 target_ulong exception_resume_pc (CPUMIPSState *env);
678
679 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
680 target_ulong *cs_base, int *flags)
681 {
682 *pc = env->active_tc.PC;
683 *cs_base = 0;
684 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
685 }
686
687 static inline int mips_vpe_active(CPUMIPSState *env)
688 {
689 int active = 1;
690
691 /* Check that the VPE is enabled. */
692 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
693 active = 0;
694 }
695 /* Check that the VPE is activated. */
696 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
697 active = 0;
698 }
699
700 /* Now verify that there are active thread contexts in the VPE.
701
702 This assumes the CPU model will internally reschedule threads
703 if the active one goes to sleep. If there are no threads available
704 the active one will be in a sleeping state, and we can turn off
705 the entire VPE. */
706 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
707 /* TC is not activated. */
708 active = 0;
709 }
710 if (env->active_tc.CP0_TCHalt & 1) {
711 /* TC is in halt state. */
712 active = 0;
713 }
714
715 return active;
716 }
717
718 #include "exec/exec-all.h"
719
720 static inline void compute_hflags(CPUMIPSState *env)
721 {
722 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
723 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
724 MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
725 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
726 !(env->CP0_Status & (1 << CP0St_ERL)) &&
727 !(env->hflags & MIPS_HFLAG_DM)) {
728 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
729 }
730 #if defined(TARGET_MIPS64)
731 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
732 (env->CP0_Status & (1 << CP0St_PX)) ||
733 (env->CP0_Status & (1 << CP0St_UX))) {
734 env->hflags |= MIPS_HFLAG_64;
735 }
736 if (env->CP0_Status & (1 << CP0St_UX)) {
737 env->hflags |= MIPS_HFLAG_UX;
738 }
739 #endif
740 if ((env->CP0_Status & (1 << CP0St_CU0)) ||
741 !(env->hflags & MIPS_HFLAG_KSU)) {
742 env->hflags |= MIPS_HFLAG_CP0;
743 }
744 if (env->CP0_Status & (1 << CP0St_CU1)) {
745 env->hflags |= MIPS_HFLAG_FPU;
746 }
747 if (env->CP0_Status & (1 << CP0St_FR)) {
748 env->hflags |= MIPS_HFLAG_F64;
749 }
750 if (env->insn_flags & ASE_DSPR2) {
751 /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
752 so enable to access DSPR2 resources. */
753 if (env->CP0_Status & (1 << CP0St_MX)) {
754 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
755 }
756
757 } else if (env->insn_flags & ASE_DSP) {
758 /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
759 so enable to access DSP resources. */
760 if (env->CP0_Status & (1 << CP0St_MX)) {
761 env->hflags |= MIPS_HFLAG_DSP;
762 }
763
764 }
765 if (env->insn_flags & ISA_MIPS32R2) {
766 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
767 env->hflags |= MIPS_HFLAG_COP1X;
768 }
769 } else if (env->insn_flags & ISA_MIPS32) {
770 if (env->hflags & MIPS_HFLAG_64) {
771 env->hflags |= MIPS_HFLAG_COP1X;
772 }
773 } else if (env->insn_flags & ISA_MIPS4) {
774 /* All supported MIPS IV CPUs use the XX (CU3) to enable
775 and disable the MIPS IV extensions to the MIPS III ISA.
776 Some other MIPS IV CPUs ignore the bit, so the check here
777 would be too restrictive for them. */
778 if (env->CP0_Status & (1 << CP0St_CU3)) {
779 env->hflags |= MIPS_HFLAG_COP1X;
780 }
781 }
782 }
783
784 #endif /* !defined (__MIPS_CPU_H__) */