target-mips: fix offset calculation for Interrupts
[qemu.git] / target-mips / helper.c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "sysemu/kvm.h"
28 #include "exec/cpu_ldst.h"
29
30 enum {
31 TLBRET_XI = -6,
32 TLBRET_RI = -5,
33 TLBRET_DIRTY = -4,
34 TLBRET_INVALID = -3,
35 TLBRET_NOMATCH = -2,
36 TLBRET_BADADDR = -1,
37 TLBRET_MATCH = 0
38 };
39
40 #if !defined(CONFIG_USER_ONLY)
41
42 /* no MMU emulation */
43 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
44 target_ulong address, int rw, int access_type)
45 {
46 *physical = address;
47 *prot = PAGE_READ | PAGE_WRITE;
48 return TLBRET_MATCH;
49 }
50
51 /* fixed mapping MMU emulation */
52 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
53 target_ulong address, int rw, int access_type)
54 {
55 if (address <= (int32_t)0x7FFFFFFFUL) {
56 if (!(env->CP0_Status & (1 << CP0St_ERL)))
57 *physical = address + 0x40000000UL;
58 else
59 *physical = address;
60 } else if (address <= (int32_t)0xBFFFFFFFUL)
61 *physical = address & 0x1FFFFFFF;
62 else
63 *physical = address;
64
65 *prot = PAGE_READ | PAGE_WRITE;
66 return TLBRET_MATCH;
67 }
68
69 /* MIPS32/MIPS64 R4000-style MMU emulation */
70 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
71 target_ulong address, int rw, int access_type)
72 {
73 uint8_t ASID = env->CP0_EntryHi & 0xFF;
74 int i;
75
76 for (i = 0; i < env->tlb->tlb_in_use; i++) {
77 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
78 /* 1k pages are not supported. */
79 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
80 target_ulong tag = address & ~mask;
81 target_ulong VPN = tlb->VPN & ~mask;
82 #if defined(TARGET_MIPS64)
83 tag &= env->SEGMask;
84 #endif
85
86 /* Check ASID, virtual page number & size */
87 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
88 /* TLB match */
89 int n = !!(address & mask & ~(mask >> 1));
90 /* Check access rights */
91 if (!(n ? tlb->V1 : tlb->V0)) {
92 return TLBRET_INVALID;
93 }
94 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
95 return TLBRET_XI;
96 }
97 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
98 return TLBRET_RI;
99 }
100 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
101 *physical = tlb->PFN[n] | (address & (mask >> 1));
102 *prot = PAGE_READ;
103 if (n ? tlb->D1 : tlb->D0)
104 *prot |= PAGE_WRITE;
105 return TLBRET_MATCH;
106 }
107 return TLBRET_DIRTY;
108 }
109 }
110 return TLBRET_NOMATCH;
111 }
112
113 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
114 int *prot, target_ulong real_address,
115 int rw, int access_type)
116 {
117 /* User mode can only access useg/xuseg */
118 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
119 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
120 int kernel_mode = !user_mode && !supervisor_mode;
121 #if defined(TARGET_MIPS64)
122 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
123 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
124 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
125 #endif
126 int ret = TLBRET_MATCH;
127 /* effective address (modified for KVM T&E kernel segments) */
128 target_ulong address = real_address;
129
130 #if 0
131 qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
132 #endif
133
134 #define USEG_LIMIT 0x7FFFFFFFUL
135 #define KSEG0_BASE 0x80000000UL
136 #define KSEG1_BASE 0xA0000000UL
137 #define KSEG2_BASE 0xC0000000UL
138 #define KSEG3_BASE 0xE0000000UL
139
140 #define KVM_KSEG0_BASE 0x40000000UL
141 #define KVM_KSEG2_BASE 0x60000000UL
142
143 if (kvm_enabled()) {
144 /* KVM T&E adds guest kernel segments in useg */
145 if (real_address >= KVM_KSEG0_BASE) {
146 if (real_address < KVM_KSEG2_BASE) {
147 /* kseg0 */
148 address += KSEG0_BASE - KVM_KSEG0_BASE;
149 } else if (real_address <= USEG_LIMIT) {
150 /* kseg2/3 */
151 address += KSEG2_BASE - KVM_KSEG2_BASE;
152 }
153 }
154 }
155
156 if (address <= USEG_LIMIT) {
157 /* useg */
158 if (env->CP0_Status & (1 << CP0St_ERL)) {
159 *physical = address & 0xFFFFFFFF;
160 *prot = PAGE_READ | PAGE_WRITE;
161 } else {
162 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
163 }
164 #if defined(TARGET_MIPS64)
165 } else if (address < 0x4000000000000000ULL) {
166 /* xuseg */
167 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
168 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
169 } else {
170 ret = TLBRET_BADADDR;
171 }
172 } else if (address < 0x8000000000000000ULL) {
173 /* xsseg */
174 if ((supervisor_mode || kernel_mode) &&
175 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
176 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
177 } else {
178 ret = TLBRET_BADADDR;
179 }
180 } else if (address < 0xC000000000000000ULL) {
181 /* xkphys */
182 if (kernel_mode && KX &&
183 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
184 *physical = address & env->PAMask;
185 *prot = PAGE_READ | PAGE_WRITE;
186 } else {
187 ret = TLBRET_BADADDR;
188 }
189 } else if (address < 0xFFFFFFFF80000000ULL) {
190 /* xkseg */
191 if (kernel_mode && KX &&
192 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
193 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
194 } else {
195 ret = TLBRET_BADADDR;
196 }
197 #endif
198 } else if (address < (int32_t)KSEG1_BASE) {
199 /* kseg0 */
200 if (kernel_mode) {
201 *physical = address - (int32_t)KSEG0_BASE;
202 *prot = PAGE_READ | PAGE_WRITE;
203 } else {
204 ret = TLBRET_BADADDR;
205 }
206 } else if (address < (int32_t)KSEG2_BASE) {
207 /* kseg1 */
208 if (kernel_mode) {
209 *physical = address - (int32_t)KSEG1_BASE;
210 *prot = PAGE_READ | PAGE_WRITE;
211 } else {
212 ret = TLBRET_BADADDR;
213 }
214 } else if (address < (int32_t)KSEG3_BASE) {
215 /* sseg (kseg2) */
216 if (supervisor_mode || kernel_mode) {
217 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
218 } else {
219 ret = TLBRET_BADADDR;
220 }
221 } else {
222 /* kseg3 */
223 /* XXX: debug segment is not emulated */
224 if (kernel_mode) {
225 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
226 } else {
227 ret = TLBRET_BADADDR;
228 }
229 }
230 #if 0
231 qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
232 address, rw, access_type, *physical, *prot, ret);
233 #endif
234
235 return ret;
236 }
237 #endif
238
239 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
240 int rw, int tlb_error)
241 {
242 CPUState *cs = CPU(mips_env_get_cpu(env));
243 int exception = 0, error_code = 0;
244
245 if (rw == MMU_INST_FETCH) {
246 error_code |= EXCP_INST_NOTAVAIL;
247 }
248
249 switch (tlb_error) {
250 default:
251 case TLBRET_BADADDR:
252 /* Reference to kernel address from user mode or supervisor mode */
253 /* Reference to supervisor address from user mode */
254 if (rw == MMU_DATA_STORE) {
255 exception = EXCP_AdES;
256 } else {
257 exception = EXCP_AdEL;
258 }
259 break;
260 case TLBRET_NOMATCH:
261 /* No TLB match for a mapped address */
262 if (rw == MMU_DATA_STORE) {
263 exception = EXCP_TLBS;
264 } else {
265 exception = EXCP_TLBL;
266 }
267 error_code |= EXCP_TLB_NOMATCH;
268 break;
269 case TLBRET_INVALID:
270 /* TLB match with no valid bit */
271 if (rw == MMU_DATA_STORE) {
272 exception = EXCP_TLBS;
273 } else {
274 exception = EXCP_TLBL;
275 }
276 break;
277 case TLBRET_DIRTY:
278 /* TLB match but 'D' bit is cleared */
279 exception = EXCP_LTLBL;
280 break;
281 case TLBRET_XI:
282 /* Execute-Inhibit Exception */
283 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
284 exception = EXCP_TLBXI;
285 } else {
286 exception = EXCP_TLBL;
287 }
288 break;
289 case TLBRET_RI:
290 /* Read-Inhibit Exception */
291 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
292 exception = EXCP_TLBRI;
293 } else {
294 exception = EXCP_TLBL;
295 }
296 break;
297 }
298 /* Raise exception */
299 env->CP0_BadVAddr = address;
300 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
301 ((address >> 9) & 0x007ffff0);
302 env->CP0_EntryHi =
303 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
304 #if defined(TARGET_MIPS64)
305 env->CP0_EntryHi &= env->SEGMask;
306 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
307 ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
308 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
309 #endif
310 cs->exception_index = exception;
311 env->error_code = error_code;
312 }
313
314 #if !defined(CONFIG_USER_ONLY)
315 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
316 {
317 MIPSCPU *cpu = MIPS_CPU(cs);
318 hwaddr phys_addr;
319 int prot;
320
321 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
322 ACCESS_INT) != 0) {
323 return -1;
324 }
325 return phys_addr;
326 }
327 #endif
328
329 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
330 int mmu_idx)
331 {
332 MIPSCPU *cpu = MIPS_CPU(cs);
333 CPUMIPSState *env = &cpu->env;
334 #if !defined(CONFIG_USER_ONLY)
335 hwaddr physical;
336 int prot;
337 int access_type;
338 #endif
339 int ret = 0;
340
341 #if 0
342 log_cpu_state(cs, 0);
343 #endif
344 qemu_log_mask(CPU_LOG_MMU,
345 "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
346 __func__, env->active_tc.PC, address, rw, mmu_idx);
347
348 /* data access */
349 #if !defined(CONFIG_USER_ONLY)
350 /* XXX: put correct access by using cpu_restore_state()
351 correctly */
352 access_type = ACCESS_INT;
353 ret = get_physical_address(env, &physical, &prot,
354 address, rw, access_type);
355 qemu_log_mask(CPU_LOG_MMU,
356 "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
357 " prot %d\n",
358 __func__, address, ret, physical, prot);
359 if (ret == TLBRET_MATCH) {
360 tlb_set_page(cs, address & TARGET_PAGE_MASK,
361 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
362 mmu_idx, TARGET_PAGE_SIZE);
363 ret = 0;
364 } else if (ret < 0)
365 #endif
366 {
367 raise_mmu_exception(env, address, rw, ret);
368 ret = 1;
369 }
370
371 return ret;
372 }
373
374 #if !defined(CONFIG_USER_ONLY)
375 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
376 {
377 hwaddr physical;
378 int prot;
379 int access_type;
380 int ret = 0;
381
382 /* data access */
383 access_type = ACCESS_INT;
384 ret = get_physical_address(env, &physical, &prot,
385 address, rw, access_type);
386 if (ret != TLBRET_MATCH) {
387 raise_mmu_exception(env, address, rw, ret);
388 return -1LL;
389 } else {
390 return physical;
391 }
392 }
393
394 static const char * const excp_names[EXCP_LAST + 1] = {
395 [EXCP_RESET] = "reset",
396 [EXCP_SRESET] = "soft reset",
397 [EXCP_DSS] = "debug single step",
398 [EXCP_DINT] = "debug interrupt",
399 [EXCP_NMI] = "non-maskable interrupt",
400 [EXCP_MCHECK] = "machine check",
401 [EXCP_EXT_INTERRUPT] = "interrupt",
402 [EXCP_DFWATCH] = "deferred watchpoint",
403 [EXCP_DIB] = "debug instruction breakpoint",
404 [EXCP_IWATCH] = "instruction fetch watchpoint",
405 [EXCP_AdEL] = "address error load",
406 [EXCP_AdES] = "address error store",
407 [EXCP_TLBF] = "TLB refill",
408 [EXCP_IBE] = "instruction bus error",
409 [EXCP_DBp] = "debug breakpoint",
410 [EXCP_SYSCALL] = "syscall",
411 [EXCP_BREAK] = "break",
412 [EXCP_CpU] = "coprocessor unusable",
413 [EXCP_RI] = "reserved instruction",
414 [EXCP_OVERFLOW] = "arithmetic overflow",
415 [EXCP_TRAP] = "trap",
416 [EXCP_FPE] = "floating point",
417 [EXCP_DDBS] = "debug data break store",
418 [EXCP_DWATCH] = "data watchpoint",
419 [EXCP_LTLBL] = "TLB modify",
420 [EXCP_TLBL] = "TLB load",
421 [EXCP_TLBS] = "TLB store",
422 [EXCP_DBE] = "data bus error",
423 [EXCP_DDBL] = "debug data break load",
424 [EXCP_THREAD] = "thread",
425 [EXCP_MDMX] = "MDMX",
426 [EXCP_C2E] = "precise coprocessor 2",
427 [EXCP_CACHE] = "cache error",
428 [EXCP_TLBXI] = "TLB execute-inhibit",
429 [EXCP_TLBRI] = "TLB read-inhibit",
430 [EXCP_MSADIS] = "MSA disabled",
431 [EXCP_MSAFPE] = "MSA floating point",
432 };
433 #endif
434
435 target_ulong exception_resume_pc (CPUMIPSState *env)
436 {
437 target_ulong bad_pc;
438 target_ulong isa_mode;
439
440 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
441 bad_pc = env->active_tc.PC | isa_mode;
442 if (env->hflags & MIPS_HFLAG_BMASK) {
443 /* If the exception was raised from a delay slot, come back to
444 the jump. */
445 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
446 }
447
448 return bad_pc;
449 }
450
451 #if !defined(CONFIG_USER_ONLY)
452 static void set_hflags_for_handler (CPUMIPSState *env)
453 {
454 /* Exception handlers are entered in 32-bit mode. */
455 env->hflags &= ~(MIPS_HFLAG_M16);
456 /* ...except that microMIPS lets you choose. */
457 if (env->insn_flags & ASE_MICROMIPS) {
458 env->hflags |= (!!(env->CP0_Config3
459 & (1 << CP0C3_ISA_ON_EXC))
460 << MIPS_HFLAG_M16_SHIFT);
461 }
462 }
463
464 static inline void set_badinstr_registers(CPUMIPSState *env)
465 {
466 if (env->hflags & MIPS_HFLAG_M16) {
467 /* TODO: add BadInstr support for microMIPS */
468 return;
469 }
470 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
471 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
472 }
473 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
474 (env->hflags & MIPS_HFLAG_BMASK)) {
475 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
476 }
477 }
478 #endif
479
480 void mips_cpu_do_interrupt(CPUState *cs)
481 {
482 #if !defined(CONFIG_USER_ONLY)
483 MIPSCPU *cpu = MIPS_CPU(cs);
484 CPUMIPSState *env = &cpu->env;
485 bool update_badinstr = 0;
486 target_ulong offset;
487 int cause = -1;
488 const char *name;
489
490 if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
491 if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
492 name = "unknown";
493 } else {
494 name = excp_names[cs->exception_index];
495 }
496
497 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
498 __func__, env->active_tc.PC, env->CP0_EPC, name);
499 }
500 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
501 (env->hflags & MIPS_HFLAG_DM)) {
502 cs->exception_index = EXCP_DINT;
503 }
504 offset = 0x180;
505 switch (cs->exception_index) {
506 case EXCP_DSS:
507 env->CP0_Debug |= 1 << CP0DB_DSS;
508 /* Debug single step cannot be raised inside a delay slot and
509 resume will always occur on the next instruction
510 (but we assume the pc has always been updated during
511 code translation). */
512 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
513 goto enter_debug_mode;
514 case EXCP_DINT:
515 env->CP0_Debug |= 1 << CP0DB_DINT;
516 goto set_DEPC;
517 case EXCP_DIB:
518 env->CP0_Debug |= 1 << CP0DB_DIB;
519 goto set_DEPC;
520 case EXCP_DBp:
521 env->CP0_Debug |= 1 << CP0DB_DBp;
522 goto set_DEPC;
523 case EXCP_DDBS:
524 env->CP0_Debug |= 1 << CP0DB_DDBS;
525 goto set_DEPC;
526 case EXCP_DDBL:
527 env->CP0_Debug |= 1 << CP0DB_DDBL;
528 set_DEPC:
529 env->CP0_DEPC = exception_resume_pc(env);
530 env->hflags &= ~MIPS_HFLAG_BMASK;
531 enter_debug_mode:
532 if (env->insn_flags & ISA_MIPS3) {
533 env->hflags |= MIPS_HFLAG_64;
534 }
535 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
536 env->hflags &= ~(MIPS_HFLAG_KSU);
537 /* EJTAG probe trap enable is not implemented... */
538 if (!(env->CP0_Status & (1 << CP0St_EXL)))
539 env->CP0_Cause &= ~(1U << CP0Ca_BD);
540 env->active_tc.PC = (int32_t)0xBFC00480;
541 set_hflags_for_handler(env);
542 break;
543 case EXCP_RESET:
544 cpu_reset(CPU(cpu));
545 break;
546 case EXCP_SRESET:
547 env->CP0_Status |= (1 << CP0St_SR);
548 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
549 goto set_error_EPC;
550 case EXCP_NMI:
551 env->CP0_Status |= (1 << CP0St_NMI);
552 set_error_EPC:
553 env->CP0_ErrorEPC = exception_resume_pc(env);
554 env->hflags &= ~MIPS_HFLAG_BMASK;
555 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
556 if (env->insn_flags & ISA_MIPS3) {
557 env->hflags |= MIPS_HFLAG_64;
558 }
559 env->hflags |= MIPS_HFLAG_CP0;
560 env->hflags &= ~(MIPS_HFLAG_KSU);
561 if (!(env->CP0_Status & (1 << CP0St_EXL)))
562 env->CP0_Cause &= ~(1U << CP0Ca_BD);
563 env->active_tc.PC = (int32_t)0xBFC00000;
564 set_hflags_for_handler(env);
565 break;
566 case EXCP_EXT_INTERRUPT:
567 cause = 0;
568 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
569 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
570
571 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
572 offset = 0x200;
573 } else {
574 uint32_t vector = 0;
575 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
576
577 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
578 /* For VEIC mode, the external interrupt controller feeds
579 * the vector through the CP0Cause IP lines. */
580 vector = pending;
581 } else {
582 /* Vectored Interrupts
583 * Mask with Status.IM7-IM0 to get enabled interrupts. */
584 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
585 /* Find the highest-priority interrupt. */
586 while (pending >>= 1) {
587 vector++;
588 }
589 }
590 offset = 0x200 + (vector * (spacing << 5));
591 }
592 }
593 goto set_EPC;
594 case EXCP_LTLBL:
595 cause = 1;
596 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
597 goto set_EPC;
598 case EXCP_TLBL:
599 cause = 2;
600 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
601 if ((env->error_code & EXCP_TLB_NOMATCH) &&
602 !(env->CP0_Status & (1 << CP0St_EXL))) {
603 #if defined(TARGET_MIPS64)
604 int R = env->CP0_BadVAddr >> 62;
605 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
606 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
607 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
608
609 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
610 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
611 offset = 0x080;
612 else
613 #endif
614 offset = 0x000;
615 }
616 goto set_EPC;
617 case EXCP_TLBS:
618 cause = 3;
619 update_badinstr = 1;
620 if ((env->error_code & EXCP_TLB_NOMATCH) &&
621 !(env->CP0_Status & (1 << CP0St_EXL))) {
622 #if defined(TARGET_MIPS64)
623 int R = env->CP0_BadVAddr >> 62;
624 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
625 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
626 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
627
628 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
629 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
630 offset = 0x080;
631 else
632 #endif
633 offset = 0x000;
634 }
635 goto set_EPC;
636 case EXCP_AdEL:
637 cause = 4;
638 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
639 goto set_EPC;
640 case EXCP_AdES:
641 cause = 5;
642 update_badinstr = 1;
643 goto set_EPC;
644 case EXCP_IBE:
645 cause = 6;
646 goto set_EPC;
647 case EXCP_DBE:
648 cause = 7;
649 goto set_EPC;
650 case EXCP_SYSCALL:
651 cause = 8;
652 update_badinstr = 1;
653 goto set_EPC;
654 case EXCP_BREAK:
655 cause = 9;
656 update_badinstr = 1;
657 goto set_EPC;
658 case EXCP_RI:
659 cause = 10;
660 update_badinstr = 1;
661 goto set_EPC;
662 case EXCP_CpU:
663 cause = 11;
664 update_badinstr = 1;
665 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
666 (env->error_code << CP0Ca_CE);
667 goto set_EPC;
668 case EXCP_OVERFLOW:
669 cause = 12;
670 update_badinstr = 1;
671 goto set_EPC;
672 case EXCP_TRAP:
673 cause = 13;
674 update_badinstr = 1;
675 goto set_EPC;
676 case EXCP_MSAFPE:
677 cause = 14;
678 update_badinstr = 1;
679 goto set_EPC;
680 case EXCP_FPE:
681 cause = 15;
682 update_badinstr = 1;
683 goto set_EPC;
684 case EXCP_C2E:
685 cause = 18;
686 goto set_EPC;
687 case EXCP_TLBRI:
688 cause = 19;
689 update_badinstr = 1;
690 goto set_EPC;
691 case EXCP_TLBXI:
692 cause = 20;
693 goto set_EPC;
694 case EXCP_MSADIS:
695 cause = 21;
696 update_badinstr = 1;
697 goto set_EPC;
698 case EXCP_MDMX:
699 cause = 22;
700 goto set_EPC;
701 case EXCP_DWATCH:
702 cause = 23;
703 /* XXX: TODO: manage defered watch exceptions */
704 goto set_EPC;
705 case EXCP_MCHECK:
706 cause = 24;
707 goto set_EPC;
708 case EXCP_THREAD:
709 cause = 25;
710 goto set_EPC;
711 case EXCP_DSPDIS:
712 cause = 26;
713 goto set_EPC;
714 case EXCP_CACHE:
715 cause = 30;
716 if (env->CP0_Status & (1 << CP0St_BEV)) {
717 offset = 0x100;
718 } else {
719 offset = 0x20000100;
720 }
721 set_EPC:
722 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
723 env->CP0_EPC = exception_resume_pc(env);
724 if (update_badinstr) {
725 set_badinstr_registers(env);
726 }
727 if (env->hflags & MIPS_HFLAG_BMASK) {
728 env->CP0_Cause |= (1U << CP0Ca_BD);
729 } else {
730 env->CP0_Cause &= ~(1U << CP0Ca_BD);
731 }
732 env->CP0_Status |= (1 << CP0St_EXL);
733 if (env->insn_flags & ISA_MIPS3) {
734 env->hflags |= MIPS_HFLAG_64;
735 }
736 env->hflags |= MIPS_HFLAG_CP0;
737 env->hflags &= ~(MIPS_HFLAG_KSU);
738 }
739 env->hflags &= ~MIPS_HFLAG_BMASK;
740 if (env->CP0_Status & (1 << CP0St_BEV)) {
741 env->active_tc.PC = (int32_t)0xBFC00200;
742 } else {
743 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
744 }
745 env->active_tc.PC += offset;
746 set_hflags_for_handler(env);
747 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
748 break;
749 default:
750 qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
751 printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
752 exit(1);
753 }
754 if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
755 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
756 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
757 __func__, env->active_tc.PC, env->CP0_EPC, cause,
758 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
759 env->CP0_DEPC);
760 }
761 #endif
762 cs->exception_index = EXCP_NONE;
763 }
764
765 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
766 {
767 if (interrupt_request & CPU_INTERRUPT_HARD) {
768 MIPSCPU *cpu = MIPS_CPU(cs);
769 CPUMIPSState *env = &cpu->env;
770
771 if (cpu_mips_hw_interrupts_pending(env)) {
772 /* Raise it */
773 cs->exception_index = EXCP_EXT_INTERRUPT;
774 env->error_code = 0;
775 mips_cpu_do_interrupt(cs);
776 return true;
777 }
778 }
779 return false;
780 }
781
782 #if !defined(CONFIG_USER_ONLY)
783 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
784 {
785 MIPSCPU *cpu = mips_env_get_cpu(env);
786 CPUState *cs;
787 r4k_tlb_t *tlb;
788 target_ulong addr;
789 target_ulong end;
790 uint8_t ASID = env->CP0_EntryHi & 0xFF;
791 target_ulong mask;
792
793 tlb = &env->tlb->mmu.r4k.tlb[idx];
794 /* The qemu TLB is flushed when the ASID changes, so no need to
795 flush these entries again. */
796 if (tlb->G == 0 && tlb->ASID != ASID) {
797 return;
798 }
799
800 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
801 /* For tlbwr, we can shadow the discarded entry into
802 a new (fake) TLB entry, as long as the guest can not
803 tell that it's there. */
804 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
805 env->tlb->tlb_in_use++;
806 return;
807 }
808
809 /* 1k pages are not supported. */
810 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
811 if (tlb->V0) {
812 cs = CPU(cpu);
813 addr = tlb->VPN & ~mask;
814 #if defined(TARGET_MIPS64)
815 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
816 addr |= 0x3FFFFF0000000000ULL;
817 }
818 #endif
819 end = addr | (mask >> 1);
820 while (addr < end) {
821 tlb_flush_page(cs, addr);
822 addr += TARGET_PAGE_SIZE;
823 }
824 }
825 if (tlb->V1) {
826 cs = CPU(cpu);
827 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
828 #if defined(TARGET_MIPS64)
829 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
830 addr |= 0x3FFFFF0000000000ULL;
831 }
832 #endif
833 end = addr | mask;
834 while (addr - 1 < end) {
835 tlb_flush_page(cs, addr);
836 addr += TARGET_PAGE_SIZE;
837 }
838 }
839 }
840 #endif