vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-mips / helper.c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "sysemu/kvm.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/log.h"
26
27 enum {
28 TLBRET_XI = -6,
29 TLBRET_RI = -5,
30 TLBRET_DIRTY = -4,
31 TLBRET_INVALID = -3,
32 TLBRET_NOMATCH = -2,
33 TLBRET_BADADDR = -1,
34 TLBRET_MATCH = 0
35 };
36
37 #if !defined(CONFIG_USER_ONLY)
38
39 /* no MMU emulation */
40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
41 target_ulong address, int rw, int access_type)
42 {
43 *physical = address;
44 *prot = PAGE_READ | PAGE_WRITE;
45 return TLBRET_MATCH;
46 }
47
48 /* fixed mapping MMU emulation */
49 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
50 target_ulong address, int rw, int access_type)
51 {
52 if (address <= (int32_t)0x7FFFFFFFUL) {
53 if (!(env->CP0_Status & (1 << CP0St_ERL)))
54 *physical = address + 0x40000000UL;
55 else
56 *physical = address;
57 } else if (address <= (int32_t)0xBFFFFFFFUL)
58 *physical = address & 0x1FFFFFFF;
59 else
60 *physical = address;
61
62 *prot = PAGE_READ | PAGE_WRITE;
63 return TLBRET_MATCH;
64 }
65
66 /* MIPS32/MIPS64 R4000-style MMU emulation */
67 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
68 target_ulong address, int rw, int access_type)
69 {
70 uint8_t ASID = env->CP0_EntryHi & 0xFF;
71 int i;
72
73 for (i = 0; i < env->tlb->tlb_in_use; i++) {
74 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
75 /* 1k pages are not supported. */
76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 target_ulong tag = address & ~mask;
78 target_ulong VPN = tlb->VPN & ~mask;
79 #if defined(TARGET_MIPS64)
80 tag &= env->SEGMask;
81 #endif
82
83 /* Check ASID, virtual page number & size */
84 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
85 /* TLB match */
86 int n = !!(address & mask & ~(mask >> 1));
87 /* Check access rights */
88 if (!(n ? tlb->V1 : tlb->V0)) {
89 return TLBRET_INVALID;
90 }
91 if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
92 return TLBRET_XI;
93 }
94 if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
95 return TLBRET_RI;
96 }
97 if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
98 *physical = tlb->PFN[n] | (address & (mask >> 1));
99 *prot = PAGE_READ;
100 if (n ? tlb->D1 : tlb->D0)
101 *prot |= PAGE_WRITE;
102 return TLBRET_MATCH;
103 }
104 return TLBRET_DIRTY;
105 }
106 }
107 return TLBRET_NOMATCH;
108 }
109
110 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
111 int *prot, target_ulong real_address,
112 int rw, int access_type)
113 {
114 /* User mode can only access useg/xuseg */
115 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
116 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
117 int kernel_mode = !user_mode && !supervisor_mode;
118 #if defined(TARGET_MIPS64)
119 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
120 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
121 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
122 #endif
123 int ret = TLBRET_MATCH;
124 /* effective address (modified for KVM T&E kernel segments) */
125 target_ulong address = real_address;
126
127 #define USEG_LIMIT 0x7FFFFFFFUL
128 #define KSEG0_BASE 0x80000000UL
129 #define KSEG1_BASE 0xA0000000UL
130 #define KSEG2_BASE 0xC0000000UL
131 #define KSEG3_BASE 0xE0000000UL
132
133 #define KVM_KSEG0_BASE 0x40000000UL
134 #define KVM_KSEG2_BASE 0x60000000UL
135
136 if (kvm_enabled()) {
137 /* KVM T&E adds guest kernel segments in useg */
138 if (real_address >= KVM_KSEG0_BASE) {
139 if (real_address < KVM_KSEG2_BASE) {
140 /* kseg0 */
141 address += KSEG0_BASE - KVM_KSEG0_BASE;
142 } else if (real_address <= USEG_LIMIT) {
143 /* kseg2/3 */
144 address += KSEG2_BASE - KVM_KSEG2_BASE;
145 }
146 }
147 }
148
149 if (address <= USEG_LIMIT) {
150 /* useg */
151 if (env->CP0_Status & (1 << CP0St_ERL)) {
152 *physical = address & 0xFFFFFFFF;
153 *prot = PAGE_READ | PAGE_WRITE;
154 } else {
155 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
156 }
157 #if defined(TARGET_MIPS64)
158 } else if (address < 0x4000000000000000ULL) {
159 /* xuseg */
160 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
161 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
162 } else {
163 ret = TLBRET_BADADDR;
164 }
165 } else if (address < 0x8000000000000000ULL) {
166 /* xsseg */
167 if ((supervisor_mode || kernel_mode) &&
168 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
169 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
170 } else {
171 ret = TLBRET_BADADDR;
172 }
173 } else if (address < 0xC000000000000000ULL) {
174 /* xkphys */
175 if (kernel_mode && KX &&
176 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
177 *physical = address & env->PAMask;
178 *prot = PAGE_READ | PAGE_WRITE;
179 } else {
180 ret = TLBRET_BADADDR;
181 }
182 } else if (address < 0xFFFFFFFF80000000ULL) {
183 /* xkseg */
184 if (kernel_mode && KX &&
185 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
186 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
187 } else {
188 ret = TLBRET_BADADDR;
189 }
190 #endif
191 } else if (address < (int32_t)KSEG1_BASE) {
192 /* kseg0 */
193 if (kernel_mode) {
194 *physical = address - (int32_t)KSEG0_BASE;
195 *prot = PAGE_READ | PAGE_WRITE;
196 } else {
197 ret = TLBRET_BADADDR;
198 }
199 } else if (address < (int32_t)KSEG2_BASE) {
200 /* kseg1 */
201 if (kernel_mode) {
202 *physical = address - (int32_t)KSEG1_BASE;
203 *prot = PAGE_READ | PAGE_WRITE;
204 } else {
205 ret = TLBRET_BADADDR;
206 }
207 } else if (address < (int32_t)KSEG3_BASE) {
208 /* sseg (kseg2) */
209 if (supervisor_mode || kernel_mode) {
210 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
211 } else {
212 ret = TLBRET_BADADDR;
213 }
214 } else {
215 /* kseg3 */
216 /* XXX: debug segment is not emulated */
217 if (kernel_mode) {
218 ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
219 } else {
220 ret = TLBRET_BADADDR;
221 }
222 }
223 return ret;
224 }
225
226 void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
227 {
228 MIPSCPU *cpu = mips_env_get_cpu(env);
229
230 /* Flush qemu's TLB and discard all shadowed entries. */
231 tlb_flush(CPU(cpu), flush_global);
232 env->tlb->tlb_in_use = env->tlb->nb_tlb;
233 }
234
235 /* Called for updates to CP0_Status. */
236 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
237 {
238 int32_t tcstatus, *tcst;
239 uint32_t v = cpu->CP0_Status;
240 uint32_t cu, mx, asid, ksu;
241 uint32_t mask = ((1 << CP0TCSt_TCU3)
242 | (1 << CP0TCSt_TCU2)
243 | (1 << CP0TCSt_TCU1)
244 | (1 << CP0TCSt_TCU0)
245 | (1 << CP0TCSt_TMX)
246 | (3 << CP0TCSt_TKSU)
247 | (0xff << CP0TCSt_TASID));
248
249 cu = (v >> CP0St_CU0) & 0xf;
250 mx = (v >> CP0St_MX) & 0x1;
251 ksu = (v >> CP0St_KSU) & 0x3;
252 asid = env->CP0_EntryHi & 0xff;
253
254 tcstatus = cu << CP0TCSt_TCU0;
255 tcstatus |= mx << CP0TCSt_TMX;
256 tcstatus |= ksu << CP0TCSt_TKSU;
257 tcstatus |= asid;
258
259 if (tc == cpu->current_tc) {
260 tcst = &cpu->active_tc.CP0_TCStatus;
261 } else {
262 tcst = &cpu->tcs[tc].CP0_TCStatus;
263 }
264
265 *tcst &= ~mask;
266 *tcst |= tcstatus;
267 compute_hflags(cpu);
268 }
269
270 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
271 {
272 uint32_t mask = env->CP0_Status_rw_bitmask;
273 target_ulong old = env->CP0_Status;
274
275 if (env->insn_flags & ISA_MIPS32R6) {
276 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
277 #if defined(TARGET_MIPS64)
278 uint32_t ksux = (1 << CP0St_KX) & val;
279 ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
280 ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
281 val = (val & ~(7 << CP0St_UX)) | ksux;
282 #endif
283 if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
284 mask &= ~(3 << CP0St_KSU);
285 }
286 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
287 }
288
289 env->CP0_Status = (old & ~mask) | (val & mask);
290 #if defined(TARGET_MIPS64)
291 if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
292 /* Access to at least one of the 64-bit segments has been disabled */
293 cpu_mips_tlb_flush(env, 1);
294 }
295 #endif
296 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
297 sync_c0_status(env, env, env->current_tc);
298 } else {
299 compute_hflags(env);
300 }
301 }
302
303 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
304 {
305 uint32_t mask = 0x00C00300;
306 uint32_t old = env->CP0_Cause;
307 int i;
308
309 if (env->insn_flags & ISA_MIPS32R2) {
310 mask |= 1 << CP0Ca_DC;
311 }
312 if (env->insn_flags & ISA_MIPS32R6) {
313 mask &= ~((1 << CP0Ca_WP) & val);
314 }
315
316 env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
317
318 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
319 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
320 cpu_mips_stop_count(env);
321 } else {
322 cpu_mips_start_count(env);
323 }
324 }
325
326 /* Set/reset software interrupts */
327 for (i = 0 ; i < 2 ; i++) {
328 if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
329 cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
330 }
331 }
332 }
333 #endif
334
335 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
336 int rw, int tlb_error)
337 {
338 CPUState *cs = CPU(mips_env_get_cpu(env));
339 int exception = 0, error_code = 0;
340
341 if (rw == MMU_INST_FETCH) {
342 error_code |= EXCP_INST_NOTAVAIL;
343 }
344
345 switch (tlb_error) {
346 default:
347 case TLBRET_BADADDR:
348 /* Reference to kernel address from user mode or supervisor mode */
349 /* Reference to supervisor address from user mode */
350 if (rw == MMU_DATA_STORE) {
351 exception = EXCP_AdES;
352 } else {
353 exception = EXCP_AdEL;
354 }
355 break;
356 case TLBRET_NOMATCH:
357 /* No TLB match for a mapped address */
358 if (rw == MMU_DATA_STORE) {
359 exception = EXCP_TLBS;
360 } else {
361 exception = EXCP_TLBL;
362 }
363 error_code |= EXCP_TLB_NOMATCH;
364 break;
365 case TLBRET_INVALID:
366 /* TLB match with no valid bit */
367 if (rw == MMU_DATA_STORE) {
368 exception = EXCP_TLBS;
369 } else {
370 exception = EXCP_TLBL;
371 }
372 break;
373 case TLBRET_DIRTY:
374 /* TLB match but 'D' bit is cleared */
375 exception = EXCP_LTLBL;
376 break;
377 case TLBRET_XI:
378 /* Execute-Inhibit Exception */
379 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
380 exception = EXCP_TLBXI;
381 } else {
382 exception = EXCP_TLBL;
383 }
384 break;
385 case TLBRET_RI:
386 /* Read-Inhibit Exception */
387 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
388 exception = EXCP_TLBRI;
389 } else {
390 exception = EXCP_TLBL;
391 }
392 break;
393 }
394 /* Raise exception */
395 env->CP0_BadVAddr = address;
396 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
397 ((address >> 9) & 0x007ffff0);
398 env->CP0_EntryHi =
399 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
400 #if defined(TARGET_MIPS64)
401 env->CP0_EntryHi &= env->SEGMask;
402 env->CP0_XContext =
403 /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
404 /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
405 /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
406 #endif
407 cs->exception_index = exception;
408 env->error_code = error_code;
409 }
410
411 #if !defined(CONFIG_USER_ONLY)
412 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
413 {
414 MIPSCPU *cpu = MIPS_CPU(cs);
415 hwaddr phys_addr;
416 int prot;
417
418 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
419 ACCESS_INT) != 0) {
420 return -1;
421 }
422 return phys_addr;
423 }
424 #endif
425
426 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
427 int mmu_idx)
428 {
429 MIPSCPU *cpu = MIPS_CPU(cs);
430 CPUMIPSState *env = &cpu->env;
431 #if !defined(CONFIG_USER_ONLY)
432 hwaddr physical;
433 int prot;
434 int access_type;
435 #endif
436 int ret = 0;
437
438 #if 0
439 log_cpu_state(cs, 0);
440 #endif
441 qemu_log_mask(CPU_LOG_MMU,
442 "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
443 __func__, env->active_tc.PC, address, rw, mmu_idx);
444
445 /* data access */
446 #if !defined(CONFIG_USER_ONLY)
447 /* XXX: put correct access by using cpu_restore_state()
448 correctly */
449 access_type = ACCESS_INT;
450 ret = get_physical_address(env, &physical, &prot,
451 address, rw, access_type);
452 qemu_log_mask(CPU_LOG_MMU,
453 "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
454 " prot %d\n",
455 __func__, address, ret, physical, prot);
456 if (ret == TLBRET_MATCH) {
457 tlb_set_page(cs, address & TARGET_PAGE_MASK,
458 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
459 mmu_idx, TARGET_PAGE_SIZE);
460 ret = 0;
461 } else if (ret < 0)
462 #endif
463 {
464 raise_mmu_exception(env, address, rw, ret);
465 ret = 1;
466 }
467
468 return ret;
469 }
470
471 #if !defined(CONFIG_USER_ONLY)
472 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
473 {
474 hwaddr physical;
475 int prot;
476 int access_type;
477 int ret = 0;
478
479 /* data access */
480 access_type = ACCESS_INT;
481 ret = get_physical_address(env, &physical, &prot,
482 address, rw, access_type);
483 if (ret != TLBRET_MATCH) {
484 raise_mmu_exception(env, address, rw, ret);
485 return -1LL;
486 } else {
487 return physical;
488 }
489 }
490
491 static const char * const excp_names[EXCP_LAST + 1] = {
492 [EXCP_RESET] = "reset",
493 [EXCP_SRESET] = "soft reset",
494 [EXCP_DSS] = "debug single step",
495 [EXCP_DINT] = "debug interrupt",
496 [EXCP_NMI] = "non-maskable interrupt",
497 [EXCP_MCHECK] = "machine check",
498 [EXCP_EXT_INTERRUPT] = "interrupt",
499 [EXCP_DFWATCH] = "deferred watchpoint",
500 [EXCP_DIB] = "debug instruction breakpoint",
501 [EXCP_IWATCH] = "instruction fetch watchpoint",
502 [EXCP_AdEL] = "address error load",
503 [EXCP_AdES] = "address error store",
504 [EXCP_TLBF] = "TLB refill",
505 [EXCP_IBE] = "instruction bus error",
506 [EXCP_DBp] = "debug breakpoint",
507 [EXCP_SYSCALL] = "syscall",
508 [EXCP_BREAK] = "break",
509 [EXCP_CpU] = "coprocessor unusable",
510 [EXCP_RI] = "reserved instruction",
511 [EXCP_OVERFLOW] = "arithmetic overflow",
512 [EXCP_TRAP] = "trap",
513 [EXCP_FPE] = "floating point",
514 [EXCP_DDBS] = "debug data break store",
515 [EXCP_DWATCH] = "data watchpoint",
516 [EXCP_LTLBL] = "TLB modify",
517 [EXCP_TLBL] = "TLB load",
518 [EXCP_TLBS] = "TLB store",
519 [EXCP_DBE] = "data bus error",
520 [EXCP_DDBL] = "debug data break load",
521 [EXCP_THREAD] = "thread",
522 [EXCP_MDMX] = "MDMX",
523 [EXCP_C2E] = "precise coprocessor 2",
524 [EXCP_CACHE] = "cache error",
525 [EXCP_TLBXI] = "TLB execute-inhibit",
526 [EXCP_TLBRI] = "TLB read-inhibit",
527 [EXCP_MSADIS] = "MSA disabled",
528 [EXCP_MSAFPE] = "MSA floating point",
529 };
530 #endif
531
532 target_ulong exception_resume_pc (CPUMIPSState *env)
533 {
534 target_ulong bad_pc;
535 target_ulong isa_mode;
536
537 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
538 bad_pc = env->active_tc.PC | isa_mode;
539 if (env->hflags & MIPS_HFLAG_BMASK) {
540 /* If the exception was raised from a delay slot, come back to
541 the jump. */
542 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
543 }
544
545 return bad_pc;
546 }
547
548 #if !defined(CONFIG_USER_ONLY)
549 static void set_hflags_for_handler (CPUMIPSState *env)
550 {
551 /* Exception handlers are entered in 32-bit mode. */
552 env->hflags &= ~(MIPS_HFLAG_M16);
553 /* ...except that microMIPS lets you choose. */
554 if (env->insn_flags & ASE_MICROMIPS) {
555 env->hflags |= (!!(env->CP0_Config3
556 & (1 << CP0C3_ISA_ON_EXC))
557 << MIPS_HFLAG_M16_SHIFT);
558 }
559 }
560
561 static inline void set_badinstr_registers(CPUMIPSState *env)
562 {
563 if (env->hflags & MIPS_HFLAG_M16) {
564 /* TODO: add BadInstr support for microMIPS */
565 return;
566 }
567 if (env->CP0_Config3 & (1 << CP0C3_BI)) {
568 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
569 }
570 if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
571 (env->hflags & MIPS_HFLAG_BMASK)) {
572 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
573 }
574 }
575 #endif
576
577 void mips_cpu_do_interrupt(CPUState *cs)
578 {
579 #if !defined(CONFIG_USER_ONLY)
580 MIPSCPU *cpu = MIPS_CPU(cs);
581 CPUMIPSState *env = &cpu->env;
582 bool update_badinstr = 0;
583 target_ulong offset;
584 int cause = -1;
585 const char *name;
586
587 if (qemu_loglevel_mask(CPU_LOG_INT)
588 && cs->exception_index != EXCP_EXT_INTERRUPT) {
589 if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
590 name = "unknown";
591 } else {
592 name = excp_names[cs->exception_index];
593 }
594
595 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
596 " %s exception\n",
597 __func__, env->active_tc.PC, env->CP0_EPC, name);
598 }
599 if (cs->exception_index == EXCP_EXT_INTERRUPT &&
600 (env->hflags & MIPS_HFLAG_DM)) {
601 cs->exception_index = EXCP_DINT;
602 }
603 offset = 0x180;
604 switch (cs->exception_index) {
605 case EXCP_DSS:
606 env->CP0_Debug |= 1 << CP0DB_DSS;
607 /* Debug single step cannot be raised inside a delay slot and
608 resume will always occur on the next instruction
609 (but we assume the pc has always been updated during
610 code translation). */
611 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
612 goto enter_debug_mode;
613 case EXCP_DINT:
614 env->CP0_Debug |= 1 << CP0DB_DINT;
615 goto set_DEPC;
616 case EXCP_DIB:
617 env->CP0_Debug |= 1 << CP0DB_DIB;
618 goto set_DEPC;
619 case EXCP_DBp:
620 env->CP0_Debug |= 1 << CP0DB_DBp;
621 goto set_DEPC;
622 case EXCP_DDBS:
623 env->CP0_Debug |= 1 << CP0DB_DDBS;
624 goto set_DEPC;
625 case EXCP_DDBL:
626 env->CP0_Debug |= 1 << CP0DB_DDBL;
627 set_DEPC:
628 env->CP0_DEPC = exception_resume_pc(env);
629 env->hflags &= ~MIPS_HFLAG_BMASK;
630 enter_debug_mode:
631 if (env->insn_flags & ISA_MIPS3) {
632 env->hflags |= MIPS_HFLAG_64;
633 if (!(env->insn_flags & ISA_MIPS64R6) ||
634 env->CP0_Status & (1 << CP0St_KX)) {
635 env->hflags &= ~MIPS_HFLAG_AWRAP;
636 }
637 }
638 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
639 env->hflags &= ~(MIPS_HFLAG_KSU);
640 /* EJTAG probe trap enable is not implemented... */
641 if (!(env->CP0_Status & (1 << CP0St_EXL)))
642 env->CP0_Cause &= ~(1U << CP0Ca_BD);
643 env->active_tc.PC = (int32_t)0xBFC00480;
644 set_hflags_for_handler(env);
645 break;
646 case EXCP_RESET:
647 cpu_reset(CPU(cpu));
648 break;
649 case EXCP_SRESET:
650 env->CP0_Status |= (1 << CP0St_SR);
651 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
652 goto set_error_EPC;
653 case EXCP_NMI:
654 env->CP0_Status |= (1 << CP0St_NMI);
655 set_error_EPC:
656 env->CP0_ErrorEPC = exception_resume_pc(env);
657 env->hflags &= ~MIPS_HFLAG_BMASK;
658 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
659 if (env->insn_flags & ISA_MIPS3) {
660 env->hflags |= MIPS_HFLAG_64;
661 if (!(env->insn_flags & ISA_MIPS64R6) ||
662 env->CP0_Status & (1 << CP0St_KX)) {
663 env->hflags &= ~MIPS_HFLAG_AWRAP;
664 }
665 }
666 env->hflags |= MIPS_HFLAG_CP0;
667 env->hflags &= ~(MIPS_HFLAG_KSU);
668 if (!(env->CP0_Status & (1 << CP0St_EXL)))
669 env->CP0_Cause &= ~(1U << CP0Ca_BD);
670 env->active_tc.PC = (int32_t)0xBFC00000;
671 set_hflags_for_handler(env);
672 break;
673 case EXCP_EXT_INTERRUPT:
674 cause = 0;
675 if (env->CP0_Cause & (1 << CP0Ca_IV)) {
676 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
677
678 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
679 offset = 0x200;
680 } else {
681 uint32_t vector = 0;
682 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
683
684 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
685 /* For VEIC mode, the external interrupt controller feeds
686 * the vector through the CP0Cause IP lines. */
687 vector = pending;
688 } else {
689 /* Vectored Interrupts
690 * Mask with Status.IM7-IM0 to get enabled interrupts. */
691 pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
692 /* Find the highest-priority interrupt. */
693 while (pending >>= 1) {
694 vector++;
695 }
696 }
697 offset = 0x200 + (vector * (spacing << 5));
698 }
699 }
700 goto set_EPC;
701 case EXCP_LTLBL:
702 cause = 1;
703 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
704 goto set_EPC;
705 case EXCP_TLBL:
706 cause = 2;
707 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
708 if ((env->error_code & EXCP_TLB_NOMATCH) &&
709 !(env->CP0_Status & (1 << CP0St_EXL))) {
710 #if defined(TARGET_MIPS64)
711 int R = env->CP0_BadVAddr >> 62;
712 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
713 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
714 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
715
716 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
717 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
718 offset = 0x080;
719 else
720 #endif
721 offset = 0x000;
722 }
723 goto set_EPC;
724 case EXCP_TLBS:
725 cause = 3;
726 update_badinstr = 1;
727 if ((env->error_code & EXCP_TLB_NOMATCH) &&
728 !(env->CP0_Status & (1 << CP0St_EXL))) {
729 #if defined(TARGET_MIPS64)
730 int R = env->CP0_BadVAddr >> 62;
731 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
732 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
733 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
734
735 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
736 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
737 offset = 0x080;
738 else
739 #endif
740 offset = 0x000;
741 }
742 goto set_EPC;
743 case EXCP_AdEL:
744 cause = 4;
745 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
746 goto set_EPC;
747 case EXCP_AdES:
748 cause = 5;
749 update_badinstr = 1;
750 goto set_EPC;
751 case EXCP_IBE:
752 cause = 6;
753 goto set_EPC;
754 case EXCP_DBE:
755 cause = 7;
756 goto set_EPC;
757 case EXCP_SYSCALL:
758 cause = 8;
759 update_badinstr = 1;
760 goto set_EPC;
761 case EXCP_BREAK:
762 cause = 9;
763 update_badinstr = 1;
764 goto set_EPC;
765 case EXCP_RI:
766 cause = 10;
767 update_badinstr = 1;
768 goto set_EPC;
769 case EXCP_CpU:
770 cause = 11;
771 update_badinstr = 1;
772 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
773 (env->error_code << CP0Ca_CE);
774 goto set_EPC;
775 case EXCP_OVERFLOW:
776 cause = 12;
777 update_badinstr = 1;
778 goto set_EPC;
779 case EXCP_TRAP:
780 cause = 13;
781 update_badinstr = 1;
782 goto set_EPC;
783 case EXCP_MSAFPE:
784 cause = 14;
785 update_badinstr = 1;
786 goto set_EPC;
787 case EXCP_FPE:
788 cause = 15;
789 update_badinstr = 1;
790 goto set_EPC;
791 case EXCP_C2E:
792 cause = 18;
793 goto set_EPC;
794 case EXCP_TLBRI:
795 cause = 19;
796 update_badinstr = 1;
797 goto set_EPC;
798 case EXCP_TLBXI:
799 cause = 20;
800 goto set_EPC;
801 case EXCP_MSADIS:
802 cause = 21;
803 update_badinstr = 1;
804 goto set_EPC;
805 case EXCP_MDMX:
806 cause = 22;
807 goto set_EPC;
808 case EXCP_DWATCH:
809 cause = 23;
810 /* XXX: TODO: manage deferred watch exceptions */
811 goto set_EPC;
812 case EXCP_MCHECK:
813 cause = 24;
814 goto set_EPC;
815 case EXCP_THREAD:
816 cause = 25;
817 goto set_EPC;
818 case EXCP_DSPDIS:
819 cause = 26;
820 goto set_EPC;
821 case EXCP_CACHE:
822 cause = 30;
823 if (env->CP0_Status & (1 << CP0St_BEV)) {
824 offset = 0x100;
825 } else {
826 offset = 0x20000100;
827 }
828 set_EPC:
829 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
830 env->CP0_EPC = exception_resume_pc(env);
831 if (update_badinstr) {
832 set_badinstr_registers(env);
833 }
834 if (env->hflags & MIPS_HFLAG_BMASK) {
835 env->CP0_Cause |= (1U << CP0Ca_BD);
836 } else {
837 env->CP0_Cause &= ~(1U << CP0Ca_BD);
838 }
839 env->CP0_Status |= (1 << CP0St_EXL);
840 if (env->insn_flags & ISA_MIPS3) {
841 env->hflags |= MIPS_HFLAG_64;
842 if (!(env->insn_flags & ISA_MIPS64R6) ||
843 env->CP0_Status & (1 << CP0St_KX)) {
844 env->hflags &= ~MIPS_HFLAG_AWRAP;
845 }
846 }
847 env->hflags |= MIPS_HFLAG_CP0;
848 env->hflags &= ~(MIPS_HFLAG_KSU);
849 }
850 env->hflags &= ~MIPS_HFLAG_BMASK;
851 if (env->CP0_Status & (1 << CP0St_BEV)) {
852 env->active_tc.PC = (int32_t)0xBFC00200;
853 } else {
854 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
855 }
856 env->active_tc.PC += offset;
857 set_hflags_for_handler(env);
858 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
859 break;
860 default:
861 abort();
862 }
863 if (qemu_loglevel_mask(CPU_LOG_INT)
864 && cs->exception_index != EXCP_EXT_INTERRUPT) {
865 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
866 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
867 __func__, env->active_tc.PC, env->CP0_EPC, cause,
868 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
869 env->CP0_DEPC);
870 }
871 #endif
872 cs->exception_index = EXCP_NONE;
873 }
874
875 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
876 {
877 if (interrupt_request & CPU_INTERRUPT_HARD) {
878 MIPSCPU *cpu = MIPS_CPU(cs);
879 CPUMIPSState *env = &cpu->env;
880
881 if (cpu_mips_hw_interrupts_enabled(env) &&
882 cpu_mips_hw_interrupts_pending(env)) {
883 /* Raise it */
884 cs->exception_index = EXCP_EXT_INTERRUPT;
885 env->error_code = 0;
886 mips_cpu_do_interrupt(cs);
887 return true;
888 }
889 }
890 return false;
891 }
892
893 #if !defined(CONFIG_USER_ONLY)
894 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
895 {
896 MIPSCPU *cpu = mips_env_get_cpu(env);
897 CPUState *cs;
898 r4k_tlb_t *tlb;
899 target_ulong addr;
900 target_ulong end;
901 uint8_t ASID = env->CP0_EntryHi & 0xFF;
902 target_ulong mask;
903
904 tlb = &env->tlb->mmu.r4k.tlb[idx];
905 /* The qemu TLB is flushed when the ASID changes, so no need to
906 flush these entries again. */
907 if (tlb->G == 0 && tlb->ASID != ASID) {
908 return;
909 }
910
911 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
912 /* For tlbwr, we can shadow the discarded entry into
913 a new (fake) TLB entry, as long as the guest can not
914 tell that it's there. */
915 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
916 env->tlb->tlb_in_use++;
917 return;
918 }
919
920 /* 1k pages are not supported. */
921 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
922 if (tlb->V0) {
923 cs = CPU(cpu);
924 addr = tlb->VPN & ~mask;
925 #if defined(TARGET_MIPS64)
926 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
927 addr |= 0x3FFFFF0000000000ULL;
928 }
929 #endif
930 end = addr | (mask >> 1);
931 while (addr < end) {
932 tlb_flush_page(cs, addr);
933 addr += TARGET_PAGE_SIZE;
934 }
935 }
936 if (tlb->V1) {
937 cs = CPU(cpu);
938 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
939 #if defined(TARGET_MIPS64)
940 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
941 addr |= 0x3FFFFF0000000000ULL;
942 }
943 #endif
944 end = addr | mask;
945 while (addr - 1 < end) {
946 tlb_flush_page(cs, addr);
947 addr += TARGET_PAGE_SIZE;
948 }
949 }
950 }
951 #endif
952
953 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
954 uint32_t exception,
955 int error_code,
956 uintptr_t pc)
957 {
958 CPUState *cs = CPU(mips_env_get_cpu(env));
959
960 if (exception < EXCP_SC) {
961 qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
962 __func__, exception, error_code);
963 }
964 cs->exception_index = exception;
965 env->error_code = error_code;
966
967 cpu_loop_exit_restore(cs, pc);
968 }