vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-mips / machine.c
1 #include "qemu/osdep.h"
2 #include "qemu-common.h"
3 #include "cpu.h"
4 #include "hw/hw.h"
5 #include "cpu.h"
6 #include "migration/cpu.h"
7
8 static int cpu_post_load(void *opaque, int version_id)
9 {
10 MIPSCPU *cpu = opaque;
11 CPUMIPSState *env = &cpu->env;
12
13 restore_fp_status(env);
14 restore_msa_fp_status(env);
15 compute_hflags(env);
16 restore_pamask(env);
17
18 return 0;
19 }
20
21 /* FPU state */
22
23 static int get_fpr(QEMUFile *f, void *pv, size_t size)
24 {
25 int i;
26 fpr_t *v = pv;
27 /* Restore entire MSA vector register */
28 for (i = 0; i < MSA_WRLEN/64; i++) {
29 qemu_get_sbe64s(f, &v->wr.d[i]);
30 }
31 return 0;
32 }
33
34 static void put_fpr(QEMUFile *f, void *pv, size_t size)
35 {
36 int i;
37 fpr_t *v = pv;
38 /* Save entire MSA vector register */
39 for (i = 0; i < MSA_WRLEN/64; i++) {
40 qemu_put_sbe64s(f, &v->wr.d[i]);
41 }
42 }
43
44 const VMStateInfo vmstate_info_fpr = {
45 .name = "fpr",
46 .get = get_fpr,
47 .put = put_fpr,
48 };
49
50 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
51 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
52
53 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \
54 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
55
56 static VMStateField vmstate_fpu_fields[] = {
57 VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
58 VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
59 VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
60 VMSTATE_END_OF_LIST()
61 };
62
63 const VMStateDescription vmstate_fpu = {
64 .name = "cpu/fpu",
65 .version_id = 1,
66 .minimum_version_id = 1,
67 .fields = vmstate_fpu_fields
68 };
69
70 const VMStateDescription vmstate_inactive_fpu = {
71 .name = "cpu/inactive_fpu",
72 .version_id = 1,
73 .minimum_version_id = 1,
74 .fields = vmstate_fpu_fields
75 };
76
77 /* TC state */
78
79 static VMStateField vmstate_tc_fields[] = {
80 VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
81 VMSTATE_UINTTL(PC, TCState),
82 VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
83 VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
84 VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
85 VMSTATE_UINTTL(DSPControl, TCState),
86 VMSTATE_INT32(CP0_TCStatus, TCState),
87 VMSTATE_INT32(CP0_TCBind, TCState),
88 VMSTATE_UINTTL(CP0_TCHalt, TCState),
89 VMSTATE_UINTTL(CP0_TCContext, TCState),
90 VMSTATE_UINTTL(CP0_TCSchedule, TCState),
91 VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
92 VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
93 VMSTATE_UINTTL(CP0_UserLocal, TCState),
94 VMSTATE_INT32(msacsr, TCState),
95 VMSTATE_END_OF_LIST()
96 };
97
98 const VMStateDescription vmstate_tc = {
99 .name = "cpu/tc",
100 .version_id = 1,
101 .minimum_version_id = 1,
102 .fields = vmstate_tc_fields
103 };
104
105 const VMStateDescription vmstate_inactive_tc = {
106 .name = "cpu/inactive_tc",
107 .version_id = 1,
108 .minimum_version_id = 1,
109 .fields = vmstate_tc_fields
110 };
111
112 /* MVP state */
113
114 const VMStateDescription vmstate_mvp = {
115 .name = "cpu/mvp",
116 .version_id = 1,
117 .minimum_version_id = 1,
118 .fields = (VMStateField[]) {
119 VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
120 VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
121 VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
122 VMSTATE_END_OF_LIST()
123 }
124 };
125
126 /* TLB state */
127
128 static int get_tlb(QEMUFile *f, void *pv, size_t size)
129 {
130 r4k_tlb_t *v = pv;
131 uint16_t flags;
132
133 qemu_get_betls(f, &v->VPN);
134 qemu_get_be32s(f, &v->PageMask);
135 qemu_get_8s(f, &v->ASID);
136 qemu_get_be16s(f, &flags);
137 v->G = (flags >> 10) & 1;
138 v->C0 = (flags >> 7) & 3;
139 v->C1 = (flags >> 4) & 3;
140 v->V0 = (flags >> 3) & 1;
141 v->V1 = (flags >> 2) & 1;
142 v->D0 = (flags >> 1) & 1;
143 v->D1 = (flags >> 0) & 1;
144 v->EHINV = (flags >> 15) & 1;
145 v->RI1 = (flags >> 14) & 1;
146 v->RI0 = (flags >> 13) & 1;
147 v->XI1 = (flags >> 12) & 1;
148 v->XI0 = (flags >> 11) & 1;
149 qemu_get_be64s(f, &v->PFN[0]);
150 qemu_get_be64s(f, &v->PFN[1]);
151
152 return 0;
153 }
154
155 static void put_tlb(QEMUFile *f, void *pv, size_t size)
156 {
157 r4k_tlb_t *v = pv;
158
159 uint8_t asid = v->ASID;
160 uint16_t flags = ((v->EHINV << 15) |
161 (v->RI1 << 14) |
162 (v->RI0 << 13) |
163 (v->XI1 << 12) |
164 (v->XI0 << 11) |
165 (v->G << 10) |
166 (v->C0 << 7) |
167 (v->C1 << 4) |
168 (v->V0 << 3) |
169 (v->V1 << 2) |
170 (v->D0 << 1) |
171 (v->D1 << 0));
172
173 qemu_put_betls(f, &v->VPN);
174 qemu_put_be32s(f, &v->PageMask);
175 qemu_put_8s(f, &asid);
176 qemu_put_be16s(f, &flags);
177 qemu_put_be64s(f, &v->PFN[0]);
178 qemu_put_be64s(f, &v->PFN[1]);
179 }
180
181 const VMStateInfo vmstate_info_tlb = {
182 .name = "tlb_entry",
183 .get = get_tlb,
184 .put = put_tlb,
185 };
186
187 #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
188 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
189
190 #define VMSTATE_TLB_ARRAY(_f, _s, _n) \
191 VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
192
193 const VMStateDescription vmstate_tlb = {
194 .name = "cpu/tlb",
195 .version_id = 1,
196 .minimum_version_id = 1,
197 .fields = (VMStateField[]) {
198 VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
199 VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
200 VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
201 VMSTATE_END_OF_LIST()
202 }
203 };
204
205 /* MIPS CPU state */
206
207 const VMStateDescription vmstate_mips_cpu = {
208 .name = "cpu",
209 .version_id = 8,
210 .minimum_version_id = 8,
211 .post_load = cpu_post_load,
212 .fields = (VMStateField[]) {
213 /* Active TC */
214 VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
215
216 /* Active FPU */
217 VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
218 CPUMIPSFPUContext),
219
220 /* MVP */
221 VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
222 CPUMIPSMVPContext),
223
224 /* TLB */
225 VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
226 CPUMIPSTLBContext),
227
228 /* CPU metastate */
229 VMSTATE_UINT32(env.current_tc, MIPSCPU),
230 VMSTATE_UINT32(env.current_fpu, MIPSCPU),
231 VMSTATE_INT32(env.error_code, MIPSCPU),
232 VMSTATE_UINTTL(env.btarget, MIPSCPU),
233 VMSTATE_UINTTL(env.bcond, MIPSCPU),
234
235 /* Remaining CP0 registers */
236 VMSTATE_INT32(env.CP0_Index, MIPSCPU),
237 VMSTATE_INT32(env.CP0_Random, MIPSCPU),
238 VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
239 VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
240 VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
241 VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
242 VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
243 VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
244 VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
245 VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
246 VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
247 VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
248 VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
249 VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
250 VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
251 VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
252 VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
253 VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
254 VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
255 VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
256 VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
257 VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
258 VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
259 VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
260 VMSTATE_INT32(env.CP0_Count, MIPSCPU),
261 VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
262 VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
263 VMSTATE_INT32(env.CP0_Status, MIPSCPU),
264 VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
265 VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
266 VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
267 VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
268 VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
269 VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
270 VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
271 VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
272 VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
273 VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
274 VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
275 VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
276 VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
277 VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
278 VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
279 VMSTATE_UINT64(env.lladdr, MIPSCPU),
280 VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
281 VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
282 VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
283 VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
284 VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
285 VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
286 VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
287 VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
288 VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
289 VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
290 VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
291 VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
292 VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
293 VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
294
295 /* Inactive TC */
296 VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
297 vmstate_inactive_tc, TCState),
298 VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
299 vmstate_inactive_fpu, CPUMIPSFPUContext),
300
301 VMSTATE_END_OF_LIST()
302 },
303 };