target-mips: fix passing incompatible pointer type in machine.c
[qemu.git] / target-mips / machine.c
1 #include "hw/hw.h"
2
3 #include "cpu.h"
4
5 static int cpu_post_load(void *opaque, int version_id)
6 {
7 MIPSCPU *cpu = opaque;
8 CPUMIPSState *env = &cpu->env;
9
10 restore_fp_status(env);
11 restore_msa_fp_status(env);
12 compute_hflags(env);
13 restore_pamask(env);
14
15 return 0;
16 }
17
18 /* FPU state */
19
20 static int get_fpr(QEMUFile *f, void *pv, size_t size)
21 {
22 int i;
23 fpr_t *v = pv;
24 /* Restore entire MSA vector register */
25 for (i = 0; i < MSA_WRLEN/64; i++) {
26 qemu_get_sbe64s(f, &v->wr.d[i]);
27 }
28 return 0;
29 }
30
31 static void put_fpr(QEMUFile *f, void *pv, size_t size)
32 {
33 int i;
34 fpr_t *v = pv;
35 /* Save entire MSA vector register */
36 for (i = 0; i < MSA_WRLEN/64; i++) {
37 qemu_put_sbe64s(f, &v->wr.d[i]);
38 }
39 }
40
41 const VMStateInfo vmstate_info_fpr = {
42 .name = "fpr",
43 .get = get_fpr,
44 .put = put_fpr,
45 };
46
47 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
48 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
49
50 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \
51 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
52
53 static VMStateField vmstate_fpu_fields[] = {
54 VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
55 VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
56 VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
57 VMSTATE_END_OF_LIST()
58 };
59
60 const VMStateDescription vmstate_fpu = {
61 .name = "cpu/fpu",
62 .version_id = 1,
63 .minimum_version_id = 1,
64 .fields = vmstate_fpu_fields
65 };
66
67 const VMStateDescription vmstate_inactive_fpu = {
68 .name = "cpu/inactive_fpu",
69 .version_id = 1,
70 .minimum_version_id = 1,
71 .fields = vmstate_fpu_fields
72 };
73
74 /* TC state */
75
76 static VMStateField vmstate_tc_fields[] = {
77 VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
78 VMSTATE_UINTTL(PC, TCState),
79 VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
80 VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
81 VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
82 VMSTATE_UINTTL(DSPControl, TCState),
83 VMSTATE_INT32(CP0_TCStatus, TCState),
84 VMSTATE_INT32(CP0_TCBind, TCState),
85 VMSTATE_UINTTL(CP0_TCHalt, TCState),
86 VMSTATE_UINTTL(CP0_TCContext, TCState),
87 VMSTATE_UINTTL(CP0_TCSchedule, TCState),
88 VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
89 VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
90 VMSTATE_UINTTL(CP0_UserLocal, TCState),
91 VMSTATE_INT32(msacsr, TCState),
92 VMSTATE_END_OF_LIST()
93 };
94
95 const VMStateDescription vmstate_tc = {
96 .name = "cpu/tc",
97 .version_id = 1,
98 .minimum_version_id = 1,
99 .fields = vmstate_tc_fields
100 };
101
102 const VMStateDescription vmstate_inactive_tc = {
103 .name = "cpu/inactive_tc",
104 .version_id = 1,
105 .minimum_version_id = 1,
106 .fields = vmstate_tc_fields
107 };
108
109 /* MVP state */
110
111 const VMStateDescription vmstate_mvp = {
112 .name = "cpu/mvp",
113 .version_id = 1,
114 .minimum_version_id = 1,
115 .fields = (VMStateField[]) {
116 VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
117 VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
118 VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
119 VMSTATE_END_OF_LIST()
120 }
121 };
122
123 /* TLB state */
124
125 static int get_tlb(QEMUFile *f, void *pv, size_t size)
126 {
127 r4k_tlb_t *v = pv;
128 uint16_t flags;
129
130 qemu_get_betls(f, &v->VPN);
131 qemu_get_be32s(f, &v->PageMask);
132 qemu_get_8s(f, &v->ASID);
133 qemu_get_be16s(f, &flags);
134 v->G = (flags >> 10) & 1;
135 v->C0 = (flags >> 7) & 3;
136 v->C1 = (flags >> 4) & 3;
137 v->V0 = (flags >> 3) & 1;
138 v->V1 = (flags >> 2) & 1;
139 v->D0 = (flags >> 1) & 1;
140 v->D1 = (flags >> 0) & 1;
141 v->EHINV = (flags >> 15) & 1;
142 v->RI1 = (flags >> 14) & 1;
143 v->RI0 = (flags >> 13) & 1;
144 v->XI1 = (flags >> 12) & 1;
145 v->XI0 = (flags >> 11) & 1;
146 qemu_get_be64s(f, &v->PFN[0]);
147 qemu_get_be64s(f, &v->PFN[1]);
148
149 return 0;
150 }
151
152 static void put_tlb(QEMUFile *f, void *pv, size_t size)
153 {
154 r4k_tlb_t *v = pv;
155
156 uint8_t asid = v->ASID;
157 uint16_t flags = ((v->EHINV << 15) |
158 (v->RI1 << 14) |
159 (v->RI0 << 13) |
160 (v->XI1 << 12) |
161 (v->XI0 << 11) |
162 (v->G << 10) |
163 (v->C0 << 7) |
164 (v->C1 << 4) |
165 (v->V0 << 3) |
166 (v->V1 << 2) |
167 (v->D0 << 1) |
168 (v->D1 << 0));
169
170 qemu_put_betls(f, &v->VPN);
171 qemu_put_be32s(f, &v->PageMask);
172 qemu_put_8s(f, &asid);
173 qemu_put_be16s(f, &flags);
174 qemu_put_be64s(f, &v->PFN[0]);
175 qemu_put_be64s(f, &v->PFN[1]);
176 }
177
178 const VMStateInfo vmstate_info_tlb = {
179 .name = "tlb_entry",
180 .get = get_tlb,
181 .put = put_tlb,
182 };
183
184 #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
185 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
186
187 #define VMSTATE_TLB_ARRAY(_f, _s, _n) \
188 VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
189
190 const VMStateDescription vmstate_tlb = {
191 .name = "cpu/tlb",
192 .version_id = 1,
193 .minimum_version_id = 1,
194 .fields = (VMStateField[]) {
195 VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
196 VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
197 VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
198 VMSTATE_END_OF_LIST()
199 }
200 };
201
202 /* MIPS CPU state */
203
204 const VMStateDescription vmstate_mips_cpu = {
205 .name = "cpu",
206 .version_id = 7,
207 .minimum_version_id = 7,
208 .post_load = cpu_post_load,
209 .fields = (VMStateField[]) {
210 /* Active TC */
211 VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
212
213 /* Active FPU */
214 VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
215 CPUMIPSFPUContext),
216
217 /* MVP */
218 VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
219 CPUMIPSMVPContext),
220
221 /* TLB */
222 VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
223 CPUMIPSTLBContext),
224
225 /* CPU metastate */
226 VMSTATE_UINT32(env.current_tc, MIPSCPU),
227 VMSTATE_UINT32(env.current_fpu, MIPSCPU),
228 VMSTATE_INT32(env.error_code, MIPSCPU),
229 VMSTATE_UINTTL(env.btarget, MIPSCPU),
230 VMSTATE_UINTTL(env.bcond, MIPSCPU),
231
232 /* Remaining CP0 registers */
233 VMSTATE_INT32(env.CP0_Index, MIPSCPU),
234 VMSTATE_INT32(env.CP0_Random, MIPSCPU),
235 VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
236 VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
237 VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
238 VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
239 VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
240 VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
241 VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
242 VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
243 VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
244 VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
245 VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
246 VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
247 VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
248 VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
249 VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
250 VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
251 VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
252 VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
253 VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
254 VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
255 VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
256 VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
257 VMSTATE_INT32(env.CP0_Count, MIPSCPU),
258 VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
259 VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
260 VMSTATE_INT32(env.CP0_Status, MIPSCPU),
261 VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
262 VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
263 VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
264 VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
265 VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
266 VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
267 VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
268 VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
269 VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
270 VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
271 VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
272 VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
273 VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
274 VMSTATE_UINT64(env.lladdr, MIPSCPU),
275 VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
276 VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
277 VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
278 VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
279 VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
280 VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
281 VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
282 VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
283 VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
284 VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
285 VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
286 VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
287 VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
288 VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
289
290 /* Inactive TC */
291 VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
292 vmstate_inactive_tc, TCState),
293 VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
294 vmstate_inactive_fpu, CPUMIPSFPUContext),
295
296 VMSTATE_END_OF_LIST()
297 },
298 };