scsi: pvscsi: check command descriptor ring buffer size (CVE-2016-4952)
[qemu.git] / target-mips / op_helper.c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "sysemu/kvm.h"
26
27 /*****************************************************************************/
28 /* Exceptions processing helpers */
29
30 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
31 int error_code)
32 {
33 do_raise_exception_err(env, exception, error_code, 0);
34 }
35
36 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
37 {
38 do_raise_exception(env, exception, GETPC());
39 }
40
41 void helper_raise_exception_debug(CPUMIPSState *env)
42 {
43 do_raise_exception(env, EXCP_DEBUG, 0);
44 }
45
46 static void raise_exception(CPUMIPSState *env, uint32_t exception)
47 {
48 do_raise_exception(env, exception, 0);
49 }
50
51 #if defined(CONFIG_USER_ONLY)
52 #define HELPER_LD(name, insn, type) \
53 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
54 int mem_idx, uintptr_t retaddr) \
55 { \
56 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
57 }
58 #else
59 #define HELPER_LD(name, insn, type) \
60 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
61 int mem_idx, uintptr_t retaddr) \
62 { \
63 switch (mem_idx) \
64 { \
65 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
66 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
67 default: \
68 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
69 } \
70 }
71 #endif
72 HELPER_LD(lw, ldl, int32_t)
73 #if defined(TARGET_MIPS64)
74 HELPER_LD(ld, ldq, int64_t)
75 #endif
76 #undef HELPER_LD
77
78 #if defined(CONFIG_USER_ONLY)
79 #define HELPER_ST(name, insn, type) \
80 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
81 type val, int mem_idx, uintptr_t retaddr) \
82 { \
83 cpu_##insn##_data_ra(env, addr, val, retaddr); \
84 }
85 #else
86 #define HELPER_ST(name, insn, type) \
87 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
88 type val, int mem_idx, uintptr_t retaddr) \
89 { \
90 switch (mem_idx) \
91 { \
92 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
93 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
94 default: \
95 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
96 } \
97 }
98 #endif
99 HELPER_ST(sb, stb, uint8_t)
100 HELPER_ST(sw, stl, uint32_t)
101 #if defined(TARGET_MIPS64)
102 HELPER_ST(sd, stq, uint64_t)
103 #endif
104 #undef HELPER_ST
105
106 target_ulong helper_clo (target_ulong arg1)
107 {
108 return clo32(arg1);
109 }
110
111 target_ulong helper_clz (target_ulong arg1)
112 {
113 return clz32(arg1);
114 }
115
116 #if defined(TARGET_MIPS64)
117 target_ulong helper_dclo (target_ulong arg1)
118 {
119 return clo64(arg1);
120 }
121
122 target_ulong helper_dclz (target_ulong arg1)
123 {
124 return clz64(arg1);
125 }
126 #endif /* TARGET_MIPS64 */
127
128 /* 64 bits arithmetic for 32 bits hosts */
129 static inline uint64_t get_HILO(CPUMIPSState *env)
130 {
131 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
132 }
133
134 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
135 {
136 target_ulong tmp;
137 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
138 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
139 return tmp;
140 }
141
142 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
143 {
144 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
145 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
146 return tmp;
147 }
148
149 /* Multiplication variants of the vr54xx. */
150 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
151 target_ulong arg2)
152 {
153 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
154 (int64_t)(int32_t)arg2));
155 }
156
157 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
158 target_ulong arg2)
159 {
160 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
161 (uint64_t)(uint32_t)arg2);
162 }
163
164 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
165 target_ulong arg2)
166 {
167 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
168 (int64_t)(int32_t)arg2);
169 }
170
171 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
172 target_ulong arg2)
173 {
174 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
175 (int64_t)(int32_t)arg2);
176 }
177
178 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
179 target_ulong arg2)
180 {
181 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
182 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
183 }
184
185 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
186 target_ulong arg2)
187 {
188 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
189 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
190 }
191
192 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
193 target_ulong arg2)
194 {
195 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
196 (int64_t)(int32_t)arg2);
197 }
198
199 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
200 target_ulong arg2)
201 {
202 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
203 (int64_t)(int32_t)arg2);
204 }
205
206 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
207 target_ulong arg2)
208 {
209 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
210 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
211 }
212
213 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
214 target_ulong arg2)
215 {
216 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
217 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
218 }
219
220 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
221 target_ulong arg2)
222 {
223 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
224 }
225
226 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
227 target_ulong arg2)
228 {
229 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
230 (uint64_t)(uint32_t)arg2);
231 }
232
233 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
234 target_ulong arg2)
235 {
236 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
237 (int64_t)(int32_t)arg2);
238 }
239
240 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
241 target_ulong arg2)
242 {
243 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
244 (uint64_t)(uint32_t)arg2);
245 }
246
247 static inline target_ulong bitswap(target_ulong v)
248 {
249 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
250 ((v & (target_ulong)0x5555555555555555ULL) << 1);
251 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
252 ((v & (target_ulong)0x3333333333333333ULL) << 2);
253 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
254 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
255 return v;
256 }
257
258 #ifdef TARGET_MIPS64
259 target_ulong helper_dbitswap(target_ulong rt)
260 {
261 return bitswap(rt);
262 }
263 #endif
264
265 target_ulong helper_bitswap(target_ulong rt)
266 {
267 return (int32_t)bitswap(rt);
268 }
269
270 #ifndef CONFIG_USER_ONLY
271
272 static inline hwaddr do_translate_address(CPUMIPSState *env,
273 target_ulong address,
274 int rw, uintptr_t retaddr)
275 {
276 hwaddr lladdr;
277 CPUState *cs = CPU(mips_env_get_cpu(env));
278
279 lladdr = cpu_mips_translate_address(env, address, rw);
280
281 if (lladdr == -1LL) {
282 cpu_loop_exit_restore(cs, retaddr);
283 } else {
284 return lladdr;
285 }
286 }
287
288 #define HELPER_LD_ATOMIC(name, insn, almask) \
289 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
290 { \
291 if (arg & almask) { \
292 env->CP0_BadVAddr = arg; \
293 do_raise_exception(env, EXCP_AdEL, GETPC()); \
294 } \
295 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
296 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
297 return env->llval; \
298 }
299 HELPER_LD_ATOMIC(ll, lw, 0x3)
300 #ifdef TARGET_MIPS64
301 HELPER_LD_ATOMIC(lld, ld, 0x7)
302 #endif
303 #undef HELPER_LD_ATOMIC
304
305 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
306 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
307 target_ulong arg2, int mem_idx) \
308 { \
309 target_long tmp; \
310 \
311 if (arg2 & almask) { \
312 env->CP0_BadVAddr = arg2; \
313 do_raise_exception(env, EXCP_AdES, GETPC()); \
314 } \
315 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
316 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
317 if (tmp == env->llval) { \
318 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
319 return 1; \
320 } \
321 } \
322 return 0; \
323 }
324 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
325 #ifdef TARGET_MIPS64
326 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
327 #endif
328 #undef HELPER_ST_ATOMIC
329 #endif
330
331 #ifdef TARGET_WORDS_BIGENDIAN
332 #define GET_LMASK(v) ((v) & 3)
333 #define GET_OFFSET(addr, offset) (addr + (offset))
334 #else
335 #define GET_LMASK(v) (((v) & 3) ^ 3)
336 #define GET_OFFSET(addr, offset) (addr - (offset))
337 #endif
338
339 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
340 int mem_idx)
341 {
342 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
343
344 if (GET_LMASK(arg2) <= 2) {
345 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
346 GETPC());
347 }
348
349 if (GET_LMASK(arg2) <= 1) {
350 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
351 GETPC());
352 }
353
354 if (GET_LMASK(arg2) == 0) {
355 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
356 GETPC());
357 }
358 }
359
360 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
361 int mem_idx)
362 {
363 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
364
365 if (GET_LMASK(arg2) >= 1) {
366 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
367 GETPC());
368 }
369
370 if (GET_LMASK(arg2) >= 2) {
371 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
372 GETPC());
373 }
374
375 if (GET_LMASK(arg2) == 3) {
376 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
377 GETPC());
378 }
379 }
380
381 #if defined(TARGET_MIPS64)
382 /* "half" load and stores. We must do the memory access inline,
383 or fault handling won't work. */
384
385 #ifdef TARGET_WORDS_BIGENDIAN
386 #define GET_LMASK64(v) ((v) & 7)
387 #else
388 #define GET_LMASK64(v) (((v) & 7) ^ 7)
389 #endif
390
391 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
392 int mem_idx)
393 {
394 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
395
396 if (GET_LMASK64(arg2) <= 6) {
397 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
398 GETPC());
399 }
400
401 if (GET_LMASK64(arg2) <= 5) {
402 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
403 GETPC());
404 }
405
406 if (GET_LMASK64(arg2) <= 4) {
407 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
408 GETPC());
409 }
410
411 if (GET_LMASK64(arg2) <= 3) {
412 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
413 GETPC());
414 }
415
416 if (GET_LMASK64(arg2) <= 2) {
417 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
418 GETPC());
419 }
420
421 if (GET_LMASK64(arg2) <= 1) {
422 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
423 GETPC());
424 }
425
426 if (GET_LMASK64(arg2) <= 0) {
427 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
428 GETPC());
429 }
430 }
431
432 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
433 int mem_idx)
434 {
435 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
436
437 if (GET_LMASK64(arg2) >= 1) {
438 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
439 GETPC());
440 }
441
442 if (GET_LMASK64(arg2) >= 2) {
443 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
444 GETPC());
445 }
446
447 if (GET_LMASK64(arg2) >= 3) {
448 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
449 GETPC());
450 }
451
452 if (GET_LMASK64(arg2) >= 4) {
453 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
454 GETPC());
455 }
456
457 if (GET_LMASK64(arg2) >= 5) {
458 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
459 GETPC());
460 }
461
462 if (GET_LMASK64(arg2) >= 6) {
463 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
464 GETPC());
465 }
466
467 if (GET_LMASK64(arg2) == 7) {
468 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
469 GETPC());
470 }
471 }
472 #endif /* TARGET_MIPS64 */
473
474 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
475
476 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
477 uint32_t mem_idx)
478 {
479 target_ulong base_reglist = reglist & 0xf;
480 target_ulong do_r31 = reglist & 0x10;
481
482 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
483 target_ulong i;
484
485 for (i = 0; i < base_reglist; i++) {
486 env->active_tc.gpr[multiple_regs[i]] =
487 (target_long)do_lw(env, addr, mem_idx, GETPC());
488 addr += 4;
489 }
490 }
491
492 if (do_r31) {
493 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
494 GETPC());
495 }
496 }
497
498 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
499 uint32_t mem_idx)
500 {
501 target_ulong base_reglist = reglist & 0xf;
502 target_ulong do_r31 = reglist & 0x10;
503
504 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
505 target_ulong i;
506
507 for (i = 0; i < base_reglist; i++) {
508 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
509 GETPC());
510 addr += 4;
511 }
512 }
513
514 if (do_r31) {
515 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
516 }
517 }
518
519 #if defined(TARGET_MIPS64)
520 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
521 uint32_t mem_idx)
522 {
523 target_ulong base_reglist = reglist & 0xf;
524 target_ulong do_r31 = reglist & 0x10;
525
526 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
527 target_ulong i;
528
529 for (i = 0; i < base_reglist; i++) {
530 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
531 GETPC());
532 addr += 8;
533 }
534 }
535
536 if (do_r31) {
537 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
538 }
539 }
540
541 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
542 uint32_t mem_idx)
543 {
544 target_ulong base_reglist = reglist & 0xf;
545 target_ulong do_r31 = reglist & 0x10;
546
547 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
548 target_ulong i;
549
550 for (i = 0; i < base_reglist; i++) {
551 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
552 GETPC());
553 addr += 8;
554 }
555 }
556
557 if (do_r31) {
558 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
559 }
560 }
561 #endif
562
563 #ifndef CONFIG_USER_ONLY
564 /* SMP helpers. */
565 static bool mips_vpe_is_wfi(MIPSCPU *c)
566 {
567 CPUState *cpu = CPU(c);
568 CPUMIPSState *env = &c->env;
569
570 /* If the VPE is halted but otherwise active, it means it's waiting for
571 an interrupt. */
572 return cpu->halted && mips_vpe_active(env);
573 }
574
575 static bool mips_vp_is_wfi(MIPSCPU *c)
576 {
577 CPUState *cpu = CPU(c);
578 CPUMIPSState *env = &c->env;
579
580 return cpu->halted && mips_vp_active(env);
581 }
582
583 static inline void mips_vpe_wake(MIPSCPU *c)
584 {
585 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
586 because there might be other conditions that state that c should
587 be sleeping. */
588 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
589 }
590
591 static inline void mips_vpe_sleep(MIPSCPU *cpu)
592 {
593 CPUState *cs = CPU(cpu);
594
595 /* The VPE was shut off, really go to bed.
596 Reset any old _WAKE requests. */
597 cs->halted = 1;
598 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
599 }
600
601 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
602 {
603 CPUMIPSState *c = &cpu->env;
604
605 /* FIXME: TC reschedule. */
606 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
607 mips_vpe_wake(cpu);
608 }
609 }
610
611 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
612 {
613 CPUMIPSState *c = &cpu->env;
614
615 /* FIXME: TC reschedule. */
616 if (!mips_vpe_active(c)) {
617 mips_vpe_sleep(cpu);
618 }
619 }
620
621 /**
622 * mips_cpu_map_tc:
623 * @env: CPU from which mapping is performed.
624 * @tc: Should point to an int with the value of the global TC index.
625 *
626 * This function will transform @tc into a local index within the
627 * returned #CPUMIPSState.
628 */
629 /* FIXME: This code assumes that all VPEs have the same number of TCs,
630 which depends on runtime setup. Can probably be fixed by
631 walking the list of CPUMIPSStates. */
632 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
633 {
634 MIPSCPU *cpu;
635 CPUState *cs;
636 CPUState *other_cs;
637 int vpe_idx;
638 int tc_idx = *tc;
639
640 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
641 /* Not allowed to address other CPUs. */
642 *tc = env->current_tc;
643 return env;
644 }
645
646 cs = CPU(mips_env_get_cpu(env));
647 vpe_idx = tc_idx / cs->nr_threads;
648 *tc = tc_idx % cs->nr_threads;
649 other_cs = qemu_get_cpu(vpe_idx);
650 if (other_cs == NULL) {
651 return env;
652 }
653 cpu = MIPS_CPU(other_cs);
654 return &cpu->env;
655 }
656
657 /* The per VPE CP0_Status register shares some fields with the per TC
658 CP0_TCStatus registers. These fields are wired to the same registers,
659 so changes to either of them should be reflected on both registers.
660
661 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
662
663 These helper call synchronizes the regs for a given cpu. */
664
665 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
666 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
667 int tc); */
668
669 /* Called for updates to CP0_TCStatus. */
670 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
671 target_ulong v)
672 {
673 uint32_t status;
674 uint32_t tcu, tmx, tasid, tksu;
675 uint32_t mask = ((1U << CP0St_CU3)
676 | (1 << CP0St_CU2)
677 | (1 << CP0St_CU1)
678 | (1 << CP0St_CU0)
679 | (1 << CP0St_MX)
680 | (3 << CP0St_KSU));
681
682 tcu = (v >> CP0TCSt_TCU0) & 0xf;
683 tmx = (v >> CP0TCSt_TMX) & 0x1;
684 tasid = v & 0xff;
685 tksu = (v >> CP0TCSt_TKSU) & 0x3;
686
687 status = tcu << CP0St_CU0;
688 status |= tmx << CP0St_MX;
689 status |= tksu << CP0St_KSU;
690
691 cpu->CP0_Status &= ~mask;
692 cpu->CP0_Status |= status;
693
694 /* Sync the TASID with EntryHi. */
695 cpu->CP0_EntryHi &= ~0xff;
696 cpu->CP0_EntryHi |= tasid;
697
698 compute_hflags(cpu);
699 }
700
701 /* Called for updates to CP0_EntryHi. */
702 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
703 {
704 int32_t *tcst;
705 uint32_t asid, v = cpu->CP0_EntryHi;
706
707 asid = v & 0xff;
708
709 if (tc == cpu->current_tc) {
710 tcst = &cpu->active_tc.CP0_TCStatus;
711 } else {
712 tcst = &cpu->tcs[tc].CP0_TCStatus;
713 }
714
715 *tcst &= ~0xff;
716 *tcst |= asid;
717 }
718
719 /* CP0 helpers */
720 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
721 {
722 return env->mvp->CP0_MVPControl;
723 }
724
725 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
726 {
727 return env->mvp->CP0_MVPConf0;
728 }
729
730 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
731 {
732 return env->mvp->CP0_MVPConf1;
733 }
734
735 target_ulong helper_mfc0_random(CPUMIPSState *env)
736 {
737 return (int32_t)cpu_mips_get_random(env);
738 }
739
740 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
741 {
742 return env->active_tc.CP0_TCStatus;
743 }
744
745 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
746 {
747 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
748 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
749
750 if (other_tc == other->current_tc)
751 return other->active_tc.CP0_TCStatus;
752 else
753 return other->tcs[other_tc].CP0_TCStatus;
754 }
755
756 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
757 {
758 return env->active_tc.CP0_TCBind;
759 }
760
761 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
762 {
763 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
764 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
765
766 if (other_tc == other->current_tc)
767 return other->active_tc.CP0_TCBind;
768 else
769 return other->tcs[other_tc].CP0_TCBind;
770 }
771
772 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
773 {
774 return env->active_tc.PC;
775 }
776
777 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
778 {
779 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
780 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
781
782 if (other_tc == other->current_tc)
783 return other->active_tc.PC;
784 else
785 return other->tcs[other_tc].PC;
786 }
787
788 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
789 {
790 return env->active_tc.CP0_TCHalt;
791 }
792
793 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
794 {
795 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
796 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
797
798 if (other_tc == other->current_tc)
799 return other->active_tc.CP0_TCHalt;
800 else
801 return other->tcs[other_tc].CP0_TCHalt;
802 }
803
804 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
805 {
806 return env->active_tc.CP0_TCContext;
807 }
808
809 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
810 {
811 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
812 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
813
814 if (other_tc == other->current_tc)
815 return other->active_tc.CP0_TCContext;
816 else
817 return other->tcs[other_tc].CP0_TCContext;
818 }
819
820 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
821 {
822 return env->active_tc.CP0_TCSchedule;
823 }
824
825 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
826 {
827 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
828 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
829
830 if (other_tc == other->current_tc)
831 return other->active_tc.CP0_TCSchedule;
832 else
833 return other->tcs[other_tc].CP0_TCSchedule;
834 }
835
836 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
837 {
838 return env->active_tc.CP0_TCScheFBack;
839 }
840
841 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
842 {
843 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
844 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
845
846 if (other_tc == other->current_tc)
847 return other->active_tc.CP0_TCScheFBack;
848 else
849 return other->tcs[other_tc].CP0_TCScheFBack;
850 }
851
852 target_ulong helper_mfc0_count(CPUMIPSState *env)
853 {
854 return (int32_t)cpu_mips_get_count(env);
855 }
856
857 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
858 {
859 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
860 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
861
862 return other->CP0_EntryHi;
863 }
864
865 target_ulong helper_mftc0_cause(CPUMIPSState *env)
866 {
867 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
868 int32_t tccause;
869 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
870
871 if (other_tc == other->current_tc) {
872 tccause = other->CP0_Cause;
873 } else {
874 tccause = other->CP0_Cause;
875 }
876
877 return tccause;
878 }
879
880 target_ulong helper_mftc0_status(CPUMIPSState *env)
881 {
882 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
883 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
884
885 return other->CP0_Status;
886 }
887
888 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
889 {
890 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
891 }
892
893 target_ulong helper_mfc0_maar(CPUMIPSState *env)
894 {
895 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
896 }
897
898 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
899 {
900 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
901 }
902
903 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
904 {
905 return (int32_t)env->CP0_WatchLo[sel];
906 }
907
908 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
909 {
910 return env->CP0_WatchHi[sel];
911 }
912
913 target_ulong helper_mfc0_debug(CPUMIPSState *env)
914 {
915 target_ulong t0 = env->CP0_Debug;
916 if (env->hflags & MIPS_HFLAG_DM)
917 t0 |= 1 << CP0DB_DM;
918
919 return t0;
920 }
921
922 target_ulong helper_mftc0_debug(CPUMIPSState *env)
923 {
924 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
925 int32_t tcstatus;
926 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
927
928 if (other_tc == other->current_tc)
929 tcstatus = other->active_tc.CP0_Debug_tcstatus;
930 else
931 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
932
933 /* XXX: Might be wrong, check with EJTAG spec. */
934 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
935 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
936 }
937
938 #if defined(TARGET_MIPS64)
939 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
940 {
941 return env->active_tc.PC;
942 }
943
944 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
945 {
946 return env->active_tc.CP0_TCHalt;
947 }
948
949 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
950 {
951 return env->active_tc.CP0_TCContext;
952 }
953
954 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
955 {
956 return env->active_tc.CP0_TCSchedule;
957 }
958
959 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
960 {
961 return env->active_tc.CP0_TCScheFBack;
962 }
963
964 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
965 {
966 return env->lladdr >> env->CP0_LLAddr_shift;
967 }
968
969 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
970 {
971 return env->CP0_MAAR[env->CP0_MAARI];
972 }
973
974 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
975 {
976 return env->CP0_WatchLo[sel];
977 }
978 #endif /* TARGET_MIPS64 */
979
980 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
981 {
982 uint32_t index_p = env->CP0_Index & 0x80000000;
983 uint32_t tlb_index = arg1 & 0x7fffffff;
984 if (tlb_index < env->tlb->nb_tlb) {
985 if (env->insn_flags & ISA_MIPS32R6) {
986 index_p |= arg1 & 0x80000000;
987 }
988 env->CP0_Index = index_p | tlb_index;
989 }
990 }
991
992 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
993 {
994 uint32_t mask = 0;
995 uint32_t newval;
996
997 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
998 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
999 (1 << CP0MVPCo_EVP);
1000 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1001 mask |= (1 << CP0MVPCo_STLB);
1002 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1003
1004 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1005
1006 env->mvp->CP0_MVPControl = newval;
1007 }
1008
1009 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1010 {
1011 uint32_t mask;
1012 uint32_t newval;
1013
1014 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1015 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1016 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1017
1018 /* Yield scheduler intercept not implemented. */
1019 /* Gating storage scheduler intercept not implemented. */
1020
1021 // TODO: Enable/disable TCs.
1022
1023 env->CP0_VPEControl = newval;
1024 }
1025
1026 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1027 {
1028 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1029 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1030 uint32_t mask;
1031 uint32_t newval;
1032
1033 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1034 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1035 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1036
1037 /* TODO: Enable/disable TCs. */
1038
1039 other->CP0_VPEControl = newval;
1040 }
1041
1042 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1043 {
1044 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1045 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1046 /* FIXME: Mask away return zero on read bits. */
1047 return other->CP0_VPEControl;
1048 }
1049
1050 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1051 {
1052 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1053 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1054
1055 return other->CP0_VPEConf0;
1056 }
1057
1058 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1059 {
1060 uint32_t mask = 0;
1061 uint32_t newval;
1062
1063 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1064 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1065 mask |= (0xff << CP0VPEC0_XTC);
1066 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1067 }
1068 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1069
1070 // TODO: TC exclusive handling due to ERL/EXL.
1071
1072 env->CP0_VPEConf0 = newval;
1073 }
1074
1075 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1076 {
1077 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1078 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1079 uint32_t mask = 0;
1080 uint32_t newval;
1081
1082 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1083 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1084
1085 /* TODO: TC exclusive handling due to ERL/EXL. */
1086 other->CP0_VPEConf0 = newval;
1087 }
1088
1089 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1090 {
1091 uint32_t mask = 0;
1092 uint32_t newval;
1093
1094 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1095 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1096 (0xff << CP0VPEC1_NCP1);
1097 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1098
1099 /* UDI not implemented. */
1100 /* CP2 not implemented. */
1101
1102 // TODO: Handle FPU (CP1) binding.
1103
1104 env->CP0_VPEConf1 = newval;
1105 }
1106
1107 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1108 {
1109 /* Yield qualifier inputs not implemented. */
1110 env->CP0_YQMask = 0x00000000;
1111 }
1112
1113 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1114 {
1115 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1116 }
1117
1118 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1119
1120 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1121 {
1122 /* 1k pages not implemented */
1123 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1124 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1125 | (rxi << (CP0EnLo_XI - 30));
1126 }
1127
1128 #if defined(TARGET_MIPS64)
1129 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1130
1131 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1132 {
1133 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1134 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1135 }
1136 #endif
1137
1138 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1139 {
1140 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1141 uint32_t newval;
1142
1143 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1144
1145 env->active_tc.CP0_TCStatus = newval;
1146 sync_c0_tcstatus(env, env->current_tc, newval);
1147 }
1148
1149 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1150 {
1151 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1152 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1153
1154 if (other_tc == other->current_tc)
1155 other->active_tc.CP0_TCStatus = arg1;
1156 else
1157 other->tcs[other_tc].CP0_TCStatus = arg1;
1158 sync_c0_tcstatus(other, other_tc, arg1);
1159 }
1160
1161 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1162 {
1163 uint32_t mask = (1 << CP0TCBd_TBE);
1164 uint32_t newval;
1165
1166 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1167 mask |= (1 << CP0TCBd_CurVPE);
1168 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1169 env->active_tc.CP0_TCBind = newval;
1170 }
1171
1172 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1173 {
1174 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1175 uint32_t mask = (1 << CP0TCBd_TBE);
1176 uint32_t newval;
1177 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1178
1179 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1180 mask |= (1 << CP0TCBd_CurVPE);
1181 if (other_tc == other->current_tc) {
1182 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1183 other->active_tc.CP0_TCBind = newval;
1184 } else {
1185 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1186 other->tcs[other_tc].CP0_TCBind = newval;
1187 }
1188 }
1189
1190 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1191 {
1192 env->active_tc.PC = arg1;
1193 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1194 env->lladdr = 0ULL;
1195 /* MIPS16 not implemented. */
1196 }
1197
1198 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1199 {
1200 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1201 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1202
1203 if (other_tc == other->current_tc) {
1204 other->active_tc.PC = arg1;
1205 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1206 other->lladdr = 0ULL;
1207 /* MIPS16 not implemented. */
1208 } else {
1209 other->tcs[other_tc].PC = arg1;
1210 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1211 other->lladdr = 0ULL;
1212 /* MIPS16 not implemented. */
1213 }
1214 }
1215
1216 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1217 {
1218 MIPSCPU *cpu = mips_env_get_cpu(env);
1219
1220 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1221
1222 // TODO: Halt TC / Restart (if allocated+active) TC.
1223 if (env->active_tc.CP0_TCHalt & 1) {
1224 mips_tc_sleep(cpu, env->current_tc);
1225 } else {
1226 mips_tc_wake(cpu, env->current_tc);
1227 }
1228 }
1229
1230 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1231 {
1232 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1233 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1234 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1235
1236 // TODO: Halt TC / Restart (if allocated+active) TC.
1237
1238 if (other_tc == other->current_tc)
1239 other->active_tc.CP0_TCHalt = arg1;
1240 else
1241 other->tcs[other_tc].CP0_TCHalt = arg1;
1242
1243 if (arg1 & 1) {
1244 mips_tc_sleep(other_cpu, other_tc);
1245 } else {
1246 mips_tc_wake(other_cpu, other_tc);
1247 }
1248 }
1249
1250 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1251 {
1252 env->active_tc.CP0_TCContext = arg1;
1253 }
1254
1255 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1256 {
1257 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1258 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1259
1260 if (other_tc == other->current_tc)
1261 other->active_tc.CP0_TCContext = arg1;
1262 else
1263 other->tcs[other_tc].CP0_TCContext = arg1;
1264 }
1265
1266 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1267 {
1268 env->active_tc.CP0_TCSchedule = arg1;
1269 }
1270
1271 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1272 {
1273 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1274 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1275
1276 if (other_tc == other->current_tc)
1277 other->active_tc.CP0_TCSchedule = arg1;
1278 else
1279 other->tcs[other_tc].CP0_TCSchedule = arg1;
1280 }
1281
1282 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1283 {
1284 env->active_tc.CP0_TCScheFBack = arg1;
1285 }
1286
1287 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1288 {
1289 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1290 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1291
1292 if (other_tc == other->current_tc)
1293 other->active_tc.CP0_TCScheFBack = arg1;
1294 else
1295 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1296 }
1297
1298 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1299 {
1300 /* 1k pages not implemented */
1301 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1302 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1303 | (rxi << (CP0EnLo_XI - 30));
1304 }
1305
1306 #if defined(TARGET_MIPS64)
1307 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1308 {
1309 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1310 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1311 }
1312 #endif
1313
1314 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1315 {
1316 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1317 }
1318
1319 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1320 {
1321 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1322 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1323 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1324 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1325 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1326 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1327 }
1328 }
1329
1330 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1331 {
1332 /* SmartMIPS not implemented */
1333 /* 1k pages not implemented */
1334 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1335 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1336 compute_hflags(env);
1337 restore_pamask(env);
1338 }
1339
1340 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1341 {
1342 if (env->insn_flags & ISA_MIPS32R6) {
1343 if (arg1 < env->tlb->nb_tlb) {
1344 env->CP0_Wired = arg1;
1345 }
1346 } else {
1347 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1348 }
1349 }
1350
1351 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1352 {
1353 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1354 }
1355
1356 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1357 {
1358 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1359 }
1360
1361 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1362 {
1363 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1364 }
1365
1366 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1367 {
1368 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1369 }
1370
1371 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1372 {
1373 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1374 }
1375
1376 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1377 {
1378 uint32_t mask = 0x0000000F;
1379
1380 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1381 (env->insn_flags & ISA_MIPS32R6)) {
1382 mask |= (1 << 4);
1383 }
1384 if (env->insn_flags & ISA_MIPS32R6) {
1385 mask |= (1 << 5);
1386 }
1387 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1388 mask |= (1 << 29);
1389
1390 if (arg1 & (1 << 29)) {
1391 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1392 } else {
1393 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1394 }
1395 }
1396
1397 env->CP0_HWREna = arg1 & mask;
1398 }
1399
1400 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1401 {
1402 cpu_mips_store_count(env, arg1);
1403 }
1404
1405 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1406 {
1407 target_ulong old, val, mask;
1408 mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1409 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1410 mask |= 1 << CP0EnHi_EHINV;
1411 }
1412
1413 /* 1k pages not implemented */
1414 #if defined(TARGET_MIPS64)
1415 if (env->insn_flags & ISA_MIPS32R6) {
1416 int entryhi_r = extract64(arg1, 62, 2);
1417 int config0_at = extract32(env->CP0_Config0, 13, 2);
1418 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1419 if ((entryhi_r == 2) ||
1420 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1421 /* skip EntryHi.R field if new value is reserved */
1422 mask &= ~(0x3ull << 62);
1423 }
1424 }
1425 mask &= env->SEGMask;
1426 #endif
1427 old = env->CP0_EntryHi;
1428 val = (arg1 & mask) | (old & ~mask);
1429 env->CP0_EntryHi = val;
1430 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1431 sync_c0_entryhi(env, env->current_tc);
1432 }
1433 /* If the ASID changes, flush qemu's TLB. */
1434 if ((old & 0xFF) != (val & 0xFF))
1435 cpu_mips_tlb_flush(env, 1);
1436 }
1437
1438 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1439 {
1440 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1441 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1442
1443 other->CP0_EntryHi = arg1;
1444 sync_c0_entryhi(other, other_tc);
1445 }
1446
1447 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1448 {
1449 cpu_mips_store_compare(env, arg1);
1450 }
1451
1452 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1453 {
1454 MIPSCPU *cpu = mips_env_get_cpu(env);
1455 uint32_t val, old;
1456
1457 old = env->CP0_Status;
1458 cpu_mips_store_status(env, arg1);
1459 val = env->CP0_Status;
1460
1461 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1462 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1463 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1464 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1465 env->CP0_Cause);
1466 switch (env->hflags & MIPS_HFLAG_KSU) {
1467 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1468 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1469 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1470 default:
1471 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1472 break;
1473 }
1474 }
1475 }
1476
1477 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1478 {
1479 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1480 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1481 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1482
1483 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1484 sync_c0_status(env, other, other_tc);
1485 }
1486
1487 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1488 {
1489 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1490 }
1491
1492 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1493 {
1494 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1495 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1496 }
1497
1498 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1499 {
1500 cpu_mips_store_cause(env, arg1);
1501 }
1502
1503 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1504 {
1505 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1506 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1507
1508 cpu_mips_store_cause(other, arg1);
1509 }
1510
1511 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1512 {
1513 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1514 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1515
1516 return other->CP0_EPC;
1517 }
1518
1519 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1520 {
1521 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1522 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1523
1524 return other->CP0_EBase;
1525 }
1526
1527 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1528 {
1529 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1530 }
1531
1532 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1533 {
1534 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1535 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1536 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1537 }
1538
1539 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1540 {
1541 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1542 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1543
1544 switch (idx) {
1545 case 0: return other->CP0_Config0;
1546 case 1: return other->CP0_Config1;
1547 case 2: return other->CP0_Config2;
1548 case 3: return other->CP0_Config3;
1549 /* 4 and 5 are reserved. */
1550 case 6: return other->CP0_Config6;
1551 case 7: return other->CP0_Config7;
1552 default:
1553 break;
1554 }
1555 return 0;
1556 }
1557
1558 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1559 {
1560 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1561 }
1562
1563 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1564 {
1565 /* tertiary/secondary caches not implemented */
1566 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1567 }
1568
1569 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1570 {
1571 if (env->insn_flags & ASE_MICROMIPS) {
1572 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1573 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1574 }
1575 }
1576
1577 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1578 {
1579 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1580 (arg1 & env->CP0_Config4_rw_bitmask);
1581 }
1582
1583 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1584 {
1585 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1586 (arg1 & env->CP0_Config5_rw_bitmask);
1587 compute_hflags(env);
1588 }
1589
1590 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1591 {
1592 target_long mask = env->CP0_LLAddr_rw_bitmask;
1593 arg1 = arg1 << env->CP0_LLAddr_shift;
1594 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1595 }
1596
1597 #define MTC0_MAAR_MASK(env) \
1598 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1599
1600 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1601 {
1602 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1603 }
1604
1605 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1606 {
1607 env->CP0_MAAR[env->CP0_MAARI] =
1608 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1609 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1610 }
1611
1612 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1613 {
1614 int index = arg1 & 0x3f;
1615 if (index == 0x3f) {
1616 /* Software may write all ones to INDEX to determine the
1617 maximum value supported. */
1618 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1619 } else if (index < MIPS_MAAR_MAX) {
1620 env->CP0_MAARI = index;
1621 }
1622 /* Other than the all ones, if the
1623 value written is not supported, then INDEX is unchanged
1624 from its previous value. */
1625 }
1626
1627 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1628 {
1629 /* Watch exceptions for instructions, data loads, data stores
1630 not implemented. */
1631 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1632 }
1633
1634 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1635 {
1636 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1637 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1638 }
1639
1640 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1641 {
1642 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1643 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1644 }
1645
1646 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1647 {
1648 env->CP0_Framemask = arg1; /* XXX */
1649 }
1650
1651 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1652 {
1653 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1654 if (arg1 & (1 << CP0DB_DM))
1655 env->hflags |= MIPS_HFLAG_DM;
1656 else
1657 env->hflags &= ~MIPS_HFLAG_DM;
1658 }
1659
1660 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1661 {
1662 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1663 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1664 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1665
1666 /* XXX: Might be wrong, check with EJTAG spec. */
1667 if (other_tc == other->current_tc)
1668 other->active_tc.CP0_Debug_tcstatus = val;
1669 else
1670 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1671 other->CP0_Debug = (other->CP0_Debug &
1672 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1673 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1674 }
1675
1676 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1677 {
1678 env->CP0_Performance0 = arg1 & 0x000007ff;
1679 }
1680
1681 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1682 {
1683 int32_t wst = arg1 & (1 << CP0EC_WST);
1684 int32_t spr = arg1 & (1 << CP0EC_SPR);
1685 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1686
1687 env->CP0_ErrCtl = wst | spr | itc;
1688
1689 if (itc && !wst && !spr) {
1690 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1691 } else {
1692 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1693 }
1694 }
1695
1696 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1697 {
1698 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1699 /* If CACHE instruction is configured for ITC tags then make all
1700 CP0.TagLo bits writable. The actual write to ITC Configuration
1701 Tag will take care of the read-only bits. */
1702 env->CP0_TagLo = arg1;
1703 } else {
1704 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1705 }
1706 }
1707
1708 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1709 {
1710 env->CP0_DataLo = arg1; /* XXX */
1711 }
1712
1713 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1714 {
1715 env->CP0_TagHi = arg1; /* XXX */
1716 }
1717
1718 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1719 {
1720 env->CP0_DataHi = arg1; /* XXX */
1721 }
1722
1723 /* MIPS MT functions */
1724 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1725 {
1726 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1727 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1728
1729 if (other_tc == other->current_tc)
1730 return other->active_tc.gpr[sel];
1731 else
1732 return other->tcs[other_tc].gpr[sel];
1733 }
1734
1735 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1736 {
1737 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1738 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1739
1740 if (other_tc == other->current_tc)
1741 return other->active_tc.LO[sel];
1742 else
1743 return other->tcs[other_tc].LO[sel];
1744 }
1745
1746 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1747 {
1748 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1749 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1750
1751 if (other_tc == other->current_tc)
1752 return other->active_tc.HI[sel];
1753 else
1754 return other->tcs[other_tc].HI[sel];
1755 }
1756
1757 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1758 {
1759 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1760 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1761
1762 if (other_tc == other->current_tc)
1763 return other->active_tc.ACX[sel];
1764 else
1765 return other->tcs[other_tc].ACX[sel];
1766 }
1767
1768 target_ulong helper_mftdsp(CPUMIPSState *env)
1769 {
1770 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1771 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1772
1773 if (other_tc == other->current_tc)
1774 return other->active_tc.DSPControl;
1775 else
1776 return other->tcs[other_tc].DSPControl;
1777 }
1778
1779 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1780 {
1781 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1782 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1783
1784 if (other_tc == other->current_tc)
1785 other->active_tc.gpr[sel] = arg1;
1786 else
1787 other->tcs[other_tc].gpr[sel] = arg1;
1788 }
1789
1790 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1791 {
1792 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1793 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1794
1795 if (other_tc == other->current_tc)
1796 other->active_tc.LO[sel] = arg1;
1797 else
1798 other->tcs[other_tc].LO[sel] = arg1;
1799 }
1800
1801 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1802 {
1803 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1804 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1805
1806 if (other_tc == other->current_tc)
1807 other->active_tc.HI[sel] = arg1;
1808 else
1809 other->tcs[other_tc].HI[sel] = arg1;
1810 }
1811
1812 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1813 {
1814 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1815 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1816
1817 if (other_tc == other->current_tc)
1818 other->active_tc.ACX[sel] = arg1;
1819 else
1820 other->tcs[other_tc].ACX[sel] = arg1;
1821 }
1822
1823 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1824 {
1825 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1826 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1827
1828 if (other_tc == other->current_tc)
1829 other->active_tc.DSPControl = arg1;
1830 else
1831 other->tcs[other_tc].DSPControl = arg1;
1832 }
1833
1834 /* MIPS MT functions */
1835 target_ulong helper_dmt(void)
1836 {
1837 // TODO
1838 return 0;
1839 }
1840
1841 target_ulong helper_emt(void)
1842 {
1843 // TODO
1844 return 0;
1845 }
1846
1847 target_ulong helper_dvpe(CPUMIPSState *env)
1848 {
1849 CPUState *other_cs = first_cpu;
1850 target_ulong prev = env->mvp->CP0_MVPControl;
1851
1852 CPU_FOREACH(other_cs) {
1853 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1854 /* Turn off all VPEs except the one executing the dvpe. */
1855 if (&other_cpu->env != env) {
1856 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1857 mips_vpe_sleep(other_cpu);
1858 }
1859 }
1860 return prev;
1861 }
1862
1863 target_ulong helper_evpe(CPUMIPSState *env)
1864 {
1865 CPUState *other_cs = first_cpu;
1866 target_ulong prev = env->mvp->CP0_MVPControl;
1867
1868 CPU_FOREACH(other_cs) {
1869 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1870
1871 if (&other_cpu->env != env
1872 /* If the VPE is WFI, don't disturb its sleep. */
1873 && !mips_vpe_is_wfi(other_cpu)) {
1874 /* Enable the VPE. */
1875 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1876 mips_vpe_wake(other_cpu); /* And wake it up. */
1877 }
1878 }
1879 return prev;
1880 }
1881 #endif /* !CONFIG_USER_ONLY */
1882
1883 void helper_fork(target_ulong arg1, target_ulong arg2)
1884 {
1885 // arg1 = rt, arg2 = rs
1886 // TODO: store to TC register
1887 }
1888
1889 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1890 {
1891 target_long arg1 = arg;
1892
1893 if (arg1 < 0) {
1894 /* No scheduling policy implemented. */
1895 if (arg1 != -2) {
1896 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1897 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1898 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1899 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1900 do_raise_exception(env, EXCP_THREAD, GETPC());
1901 }
1902 }
1903 } else if (arg1 == 0) {
1904 if (0 /* TODO: TC underflow */) {
1905 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1906 do_raise_exception(env, EXCP_THREAD, GETPC());
1907 } else {
1908 // TODO: Deallocate TC
1909 }
1910 } else if (arg1 > 0) {
1911 /* Yield qualifier inputs not implemented. */
1912 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1913 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1914 do_raise_exception(env, EXCP_THREAD, GETPC());
1915 }
1916 return env->CP0_YQMask;
1917 }
1918
1919 /* R6 Multi-threading */
1920 #ifndef CONFIG_USER_ONLY
1921 target_ulong helper_dvp(CPUMIPSState *env)
1922 {
1923 CPUState *other_cs = first_cpu;
1924 target_ulong prev = env->CP0_VPControl;
1925
1926 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1927 CPU_FOREACH(other_cs) {
1928 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1929 /* Turn off all VPs except the one executing the dvp. */
1930 if (&other_cpu->env != env) {
1931 mips_vpe_sleep(other_cpu);
1932 }
1933 }
1934 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1935 }
1936 return prev;
1937 }
1938
1939 target_ulong helper_evp(CPUMIPSState *env)
1940 {
1941 CPUState *other_cs = first_cpu;
1942 target_ulong prev = env->CP0_VPControl;
1943
1944 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1945 CPU_FOREACH(other_cs) {
1946 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1947 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1948 /* If the VP is WFI, don't disturb its sleep.
1949 * Otherwise, wake it up. */
1950 mips_vpe_wake(other_cpu);
1951 }
1952 }
1953 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1954 }
1955 return prev;
1956 }
1957 #endif /* !CONFIG_USER_ONLY */
1958
1959 #ifndef CONFIG_USER_ONLY
1960 /* TLB management */
1961 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1962 {
1963 /* Discard entries from env->tlb[first] onwards. */
1964 while (env->tlb->tlb_in_use > first) {
1965 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1966 }
1967 }
1968
1969 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1970 {
1971 #if defined(TARGET_MIPS64)
1972 return extract64(entrylo, 6, 54);
1973 #else
1974 return extract64(entrylo, 6, 24) | /* PFN */
1975 (extract64(entrylo, 32, 32) << 24); /* PFNX */
1976 #endif
1977 }
1978
1979 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1980 {
1981 r4k_tlb_t *tlb;
1982
1983 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1984 tlb = &env->tlb->mmu.r4k.tlb[idx];
1985 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1986 tlb->EHINV = 1;
1987 return;
1988 }
1989 tlb->EHINV = 0;
1990 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1991 #if defined(TARGET_MIPS64)
1992 tlb->VPN &= env->SEGMask;
1993 #endif
1994 tlb->ASID = env->CP0_EntryHi & 0xFF;
1995 tlb->PageMask = env->CP0_PageMask;
1996 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1997 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1998 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1999 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2000 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2001 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2002 tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
2003 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2004 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2005 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2006 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2007 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2008 tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
2009 }
2010
2011 void r4k_helper_tlbinv(CPUMIPSState *env)
2012 {
2013 int idx;
2014 r4k_tlb_t *tlb;
2015 uint8_t ASID = env->CP0_EntryHi & 0xFF;
2016
2017 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2018 tlb = &env->tlb->mmu.r4k.tlb[idx];
2019 if (!tlb->G && tlb->ASID == ASID) {
2020 tlb->EHINV = 1;
2021 }
2022 }
2023 cpu_mips_tlb_flush(env, 1);
2024 }
2025
2026 void r4k_helper_tlbinvf(CPUMIPSState *env)
2027 {
2028 int idx;
2029
2030 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2031 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2032 }
2033 cpu_mips_tlb_flush(env, 1);
2034 }
2035
2036 void r4k_helper_tlbwi(CPUMIPSState *env)
2037 {
2038 r4k_tlb_t *tlb;
2039 int idx;
2040 target_ulong VPN;
2041 uint8_t ASID;
2042 bool G, V0, D0, V1, D1;
2043
2044 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2045 tlb = &env->tlb->mmu.r4k.tlb[idx];
2046 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2047 #if defined(TARGET_MIPS64)
2048 VPN &= env->SEGMask;
2049 #endif
2050 ASID = env->CP0_EntryHi & 0xff;
2051 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2052 V0 = (env->CP0_EntryLo0 & 2) != 0;
2053 D0 = (env->CP0_EntryLo0 & 4) != 0;
2054 V1 = (env->CP0_EntryLo1 & 2) != 0;
2055 D1 = (env->CP0_EntryLo1 & 4) != 0;
2056
2057 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2058 permissions on the current entry. */
2059 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2060 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2061 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
2062 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2063 }
2064
2065 r4k_invalidate_tlb(env, idx, 0);
2066 r4k_fill_tlb(env, idx);
2067 }
2068
2069 void r4k_helper_tlbwr(CPUMIPSState *env)
2070 {
2071 int r = cpu_mips_get_random(env);
2072
2073 r4k_invalidate_tlb(env, r, 1);
2074 r4k_fill_tlb(env, r);
2075 }
2076
2077 void r4k_helper_tlbp(CPUMIPSState *env)
2078 {
2079 r4k_tlb_t *tlb;
2080 target_ulong mask;
2081 target_ulong tag;
2082 target_ulong VPN;
2083 uint8_t ASID;
2084 int i;
2085
2086 ASID = env->CP0_EntryHi & 0xFF;
2087 for (i = 0; i < env->tlb->nb_tlb; i++) {
2088 tlb = &env->tlb->mmu.r4k.tlb[i];
2089 /* 1k pages are not supported. */
2090 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2091 tag = env->CP0_EntryHi & ~mask;
2092 VPN = tlb->VPN & ~mask;
2093 #if defined(TARGET_MIPS64)
2094 tag &= env->SEGMask;
2095 #endif
2096 /* Check ASID, virtual page number & size */
2097 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2098 /* TLB match */
2099 env->CP0_Index = i;
2100 break;
2101 }
2102 }
2103 if (i == env->tlb->nb_tlb) {
2104 /* No match. Discard any shadow entries, if any of them match. */
2105 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2106 tlb = &env->tlb->mmu.r4k.tlb[i];
2107 /* 1k pages are not supported. */
2108 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2109 tag = env->CP0_EntryHi & ~mask;
2110 VPN = tlb->VPN & ~mask;
2111 #if defined(TARGET_MIPS64)
2112 tag &= env->SEGMask;
2113 #endif
2114 /* Check ASID, virtual page number & size */
2115 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2116 r4k_mips_tlb_flush_extra (env, i);
2117 break;
2118 }
2119 }
2120
2121 env->CP0_Index |= 0x80000000;
2122 }
2123 }
2124
2125 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2126 {
2127 #if defined(TARGET_MIPS64)
2128 return tlb_pfn << 6;
2129 #else
2130 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2131 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2132 #endif
2133 }
2134
2135 void r4k_helper_tlbr(CPUMIPSState *env)
2136 {
2137 r4k_tlb_t *tlb;
2138 uint8_t ASID;
2139 int idx;
2140
2141 ASID = env->CP0_EntryHi & 0xFF;
2142 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2143 tlb = &env->tlb->mmu.r4k.tlb[idx];
2144
2145 /* If this will change the current ASID, flush qemu's TLB. */
2146 if (ASID != tlb->ASID)
2147 cpu_mips_tlb_flush (env, 1);
2148
2149 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2150
2151 if (tlb->EHINV) {
2152 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2153 env->CP0_PageMask = 0;
2154 env->CP0_EntryLo0 = 0;
2155 env->CP0_EntryLo1 = 0;
2156 } else {
2157 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2158 env->CP0_PageMask = tlb->PageMask;
2159 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2160 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2161 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2162 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2163 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2164 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2165 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2166 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2167 }
2168 }
2169
2170 void helper_tlbwi(CPUMIPSState *env)
2171 {
2172 env->tlb->helper_tlbwi(env);
2173 }
2174
2175 void helper_tlbwr(CPUMIPSState *env)
2176 {
2177 env->tlb->helper_tlbwr(env);
2178 }
2179
2180 void helper_tlbp(CPUMIPSState *env)
2181 {
2182 env->tlb->helper_tlbp(env);
2183 }
2184
2185 void helper_tlbr(CPUMIPSState *env)
2186 {
2187 env->tlb->helper_tlbr(env);
2188 }
2189
2190 void helper_tlbinv(CPUMIPSState *env)
2191 {
2192 env->tlb->helper_tlbinv(env);
2193 }
2194
2195 void helper_tlbinvf(CPUMIPSState *env)
2196 {
2197 env->tlb->helper_tlbinvf(env);
2198 }
2199
2200 /* Specials */
2201 target_ulong helper_di(CPUMIPSState *env)
2202 {
2203 target_ulong t0 = env->CP0_Status;
2204
2205 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2206 return t0;
2207 }
2208
2209 target_ulong helper_ei(CPUMIPSState *env)
2210 {
2211 target_ulong t0 = env->CP0_Status;
2212
2213 env->CP0_Status = t0 | (1 << CP0St_IE);
2214 return t0;
2215 }
2216
2217 static void debug_pre_eret(CPUMIPSState *env)
2218 {
2219 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2220 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2221 env->active_tc.PC, env->CP0_EPC);
2222 if (env->CP0_Status & (1 << CP0St_ERL))
2223 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2224 if (env->hflags & MIPS_HFLAG_DM)
2225 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2226 qemu_log("\n");
2227 }
2228 }
2229
2230 static void debug_post_eret(CPUMIPSState *env)
2231 {
2232 MIPSCPU *cpu = mips_env_get_cpu(env);
2233
2234 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2235 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2236 env->active_tc.PC, env->CP0_EPC);
2237 if (env->CP0_Status & (1 << CP0St_ERL))
2238 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2239 if (env->hflags & MIPS_HFLAG_DM)
2240 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2241 switch (env->hflags & MIPS_HFLAG_KSU) {
2242 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2243 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2244 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2245 default:
2246 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2247 break;
2248 }
2249 }
2250 }
2251
2252 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2253 {
2254 env->active_tc.PC = error_pc & ~(target_ulong)1;
2255 if (error_pc & 1) {
2256 env->hflags |= MIPS_HFLAG_M16;
2257 } else {
2258 env->hflags &= ~(MIPS_HFLAG_M16);
2259 }
2260 }
2261
2262 static inline void exception_return(CPUMIPSState *env)
2263 {
2264 debug_pre_eret(env);
2265 if (env->CP0_Status & (1 << CP0St_ERL)) {
2266 set_pc(env, env->CP0_ErrorEPC);
2267 env->CP0_Status &= ~(1 << CP0St_ERL);
2268 } else {
2269 set_pc(env, env->CP0_EPC);
2270 env->CP0_Status &= ~(1 << CP0St_EXL);
2271 }
2272 compute_hflags(env);
2273 debug_post_eret(env);
2274 }
2275
2276 void helper_eret(CPUMIPSState *env)
2277 {
2278 exception_return(env);
2279 env->lladdr = 1;
2280 }
2281
2282 void helper_eretnc(CPUMIPSState *env)
2283 {
2284 exception_return(env);
2285 }
2286
2287 void helper_deret(CPUMIPSState *env)
2288 {
2289 debug_pre_eret(env);
2290 set_pc(env, env->CP0_DEPC);
2291
2292 env->hflags &= ~MIPS_HFLAG_DM;
2293 compute_hflags(env);
2294 debug_post_eret(env);
2295 }
2296 #endif /* !CONFIG_USER_ONLY */
2297
2298 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2299 {
2300 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2301 return;
2302 }
2303 do_raise_exception(env, EXCP_RI, pc);
2304 }
2305
2306 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2307 {
2308 check_hwrena(env, 0, GETPC());
2309 return env->CP0_EBase & 0x3ff;
2310 }
2311
2312 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2313 {
2314 check_hwrena(env, 1, GETPC());
2315 return env->SYNCI_Step;
2316 }
2317
2318 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2319 {
2320 check_hwrena(env, 2, GETPC());
2321 #ifdef CONFIG_USER_ONLY
2322 return env->CP0_Count;
2323 #else
2324 return (int32_t)cpu_mips_get_count(env);
2325 #endif
2326 }
2327
2328 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2329 {
2330 check_hwrena(env, 3, GETPC());
2331 return env->CCRes;
2332 }
2333
2334 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2335 {
2336 check_hwrena(env, 4, GETPC());
2337 return env->CP0_Performance0;
2338 }
2339
2340 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2341 {
2342 check_hwrena(env, 5, GETPC());
2343 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2344 }
2345
2346 void helper_pmon(CPUMIPSState *env, int function)
2347 {
2348 function /= 2;
2349 switch (function) {
2350 case 2: /* TODO: char inbyte(int waitflag); */
2351 if (env->active_tc.gpr[4] == 0)
2352 env->active_tc.gpr[2] = -1;
2353 /* Fall through */
2354 case 11: /* TODO: char inbyte (void); */
2355 env->active_tc.gpr[2] = -1;
2356 break;
2357 case 3:
2358 case 12:
2359 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2360 break;
2361 case 17:
2362 break;
2363 case 158:
2364 {
2365 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2366 printf("%s", fmt);
2367 }
2368 break;
2369 }
2370 }
2371
2372 void helper_wait(CPUMIPSState *env)
2373 {
2374 CPUState *cs = CPU(mips_env_get_cpu(env));
2375
2376 cs->halted = 1;
2377 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2378 /* Last instruction in the block, PC was updated before
2379 - no need to recover PC and icount */
2380 raise_exception(env, EXCP_HLT);
2381 }
2382
2383 #if !defined(CONFIG_USER_ONLY)
2384
2385 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2386 int access_type, int is_user,
2387 uintptr_t retaddr)
2388 {
2389 MIPSCPU *cpu = MIPS_CPU(cs);
2390 CPUMIPSState *env = &cpu->env;
2391 int error_code = 0;
2392 int excp;
2393
2394 env->CP0_BadVAddr = addr;
2395
2396 if (access_type == MMU_DATA_STORE) {
2397 excp = EXCP_AdES;
2398 } else {
2399 excp = EXCP_AdEL;
2400 if (access_type == MMU_INST_FETCH) {
2401 error_code |= EXCP_INST_NOTAVAIL;
2402 }
2403 }
2404
2405 do_raise_exception_err(env, excp, error_code, retaddr);
2406 }
2407
2408 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2409 uintptr_t retaddr)
2410 {
2411 int ret;
2412
2413 ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2414 if (ret) {
2415 MIPSCPU *cpu = MIPS_CPU(cs);
2416 CPUMIPSState *env = &cpu->env;
2417
2418 do_raise_exception_err(env, cs->exception_index,
2419 env->error_code, retaddr);
2420 }
2421 }
2422
2423 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2424 bool is_write, bool is_exec, int unused,
2425 unsigned size)
2426 {
2427 MIPSCPU *cpu = MIPS_CPU(cs);
2428 CPUMIPSState *env = &cpu->env;
2429
2430 /*
2431 * Raising an exception with KVM enabled will crash because it won't be from
2432 * the main execution loop so the longjmp won't have a matching setjmp.
2433 * Until we can trigger a bus error exception through KVM lets just ignore
2434 * the access.
2435 */
2436 if (kvm_enabled()) {
2437 return;
2438 }
2439
2440 if (is_exec) {
2441 raise_exception(env, EXCP_IBE);
2442 } else {
2443 raise_exception(env, EXCP_DBE);
2444 }
2445 }
2446 #endif /* !CONFIG_USER_ONLY */
2447
2448 /* Complex FPU operations which may need stack space. */
2449
2450 #define FLOAT_TWO32 make_float32(1 << 30)
2451 #define FLOAT_TWO64 make_float64(1ULL << 62)
2452 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2453 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2454
2455 /* convert MIPS rounding mode in FCR31 to IEEE library */
2456 unsigned int ieee_rm[] = {
2457 float_round_nearest_even,
2458 float_round_to_zero,
2459 float_round_up,
2460 float_round_down
2461 };
2462
2463 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2464 {
2465 target_ulong arg1 = 0;
2466
2467 switch (reg) {
2468 case 0:
2469 arg1 = (int32_t)env->active_fpu.fcr0;
2470 break;
2471 case 1:
2472 /* UFR Support - Read Status FR */
2473 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2474 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2475 arg1 = (int32_t)
2476 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2477 } else {
2478 do_raise_exception(env, EXCP_RI, GETPC());
2479 }
2480 }
2481 break;
2482 case 5:
2483 /* FRE Support - read Config5.FRE bit */
2484 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2485 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2486 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2487 } else {
2488 helper_raise_exception(env, EXCP_RI);
2489 }
2490 }
2491 break;
2492 case 25:
2493 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2494 break;
2495 case 26:
2496 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2497 break;
2498 case 28:
2499 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2500 break;
2501 default:
2502 arg1 = (int32_t)env->active_fpu.fcr31;
2503 break;
2504 }
2505
2506 return arg1;
2507 }
2508
2509 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2510 {
2511 switch (fs) {
2512 case 1:
2513 /* UFR Alias - Reset Status FR */
2514 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2515 return;
2516 }
2517 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2518 env->CP0_Status &= ~(1 << CP0St_FR);
2519 compute_hflags(env);
2520 } else {
2521 do_raise_exception(env, EXCP_RI, GETPC());
2522 }
2523 break;
2524 case 4:
2525 /* UNFR Alias - Set Status FR */
2526 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2527 return;
2528 }
2529 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2530 env->CP0_Status |= (1 << CP0St_FR);
2531 compute_hflags(env);
2532 } else {
2533 do_raise_exception(env, EXCP_RI, GETPC());
2534 }
2535 break;
2536 case 5:
2537 /* FRE Support - clear Config5.FRE bit */
2538 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2539 return;
2540 }
2541 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2542 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2543 compute_hflags(env);
2544 } else {
2545 helper_raise_exception(env, EXCP_RI);
2546 }
2547 break;
2548 case 6:
2549 /* FRE Support - set Config5.FRE bit */
2550 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2551 return;
2552 }
2553 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2554 env->CP0_Config5 |= (1 << CP0C5_FRE);
2555 compute_hflags(env);
2556 } else {
2557 helper_raise_exception(env, EXCP_RI);
2558 }
2559 break;
2560 case 25:
2561 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2562 return;
2563 }
2564 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2565 ((arg1 & 0x1) << 23);
2566 break;
2567 case 26:
2568 if (arg1 & 0x007c0000)
2569 return;
2570 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2571 break;
2572 case 28:
2573 if (arg1 & 0x007c0000)
2574 return;
2575 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2576 ((arg1 & 0x4) << 22);
2577 break;
2578 case 31:
2579 if (env->insn_flags & ISA_MIPS32R6) {
2580 uint32_t mask = 0xfefc0000;
2581 env->active_fpu.fcr31 = (arg1 & ~mask) |
2582 (env->active_fpu.fcr31 & mask);
2583 } else if (!(arg1 & 0x007c0000)) {
2584 env->active_fpu.fcr31 = arg1;
2585 }
2586 break;
2587 default:
2588 return;
2589 }
2590 /* set rounding mode */
2591 restore_rounding_mode(env);
2592 /* set flush-to-zero mode */
2593 restore_flush_mode(env);
2594 set_float_exception_flags(0, &env->active_fpu.fp_status);
2595 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2596 do_raise_exception(env, EXCP_FPE, GETPC());
2597 }
2598
2599 int ieee_ex_to_mips(int xcpt)
2600 {
2601 int ret = 0;
2602 if (xcpt) {
2603 if (xcpt & float_flag_invalid) {
2604 ret |= FP_INVALID;
2605 }
2606 if (xcpt & float_flag_overflow) {
2607 ret |= FP_OVERFLOW;
2608 }
2609 if (xcpt & float_flag_underflow) {
2610 ret |= FP_UNDERFLOW;
2611 }
2612 if (xcpt & float_flag_divbyzero) {
2613 ret |= FP_DIV0;
2614 }
2615 if (xcpt & float_flag_inexact) {
2616 ret |= FP_INEXACT;
2617 }
2618 }
2619 return ret;
2620 }
2621
2622 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2623 {
2624 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2625
2626 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2627
2628 if (tmp) {
2629 set_float_exception_flags(0, &env->active_fpu.fp_status);
2630
2631 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2632 do_raise_exception(env, EXCP_FPE, pc);
2633 } else {
2634 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2635 }
2636 }
2637 }
2638
2639 /* Float support.
2640 Single precition routines have a "s" suffix, double precision a
2641 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2642 paired single lower "pl", paired single upper "pu". */
2643
2644 /* unary operations, modifying fp status */
2645 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2646 {
2647 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2648 update_fcr31(env, GETPC());
2649 return fdt0;
2650 }
2651
2652 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2653 {
2654 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2655 update_fcr31(env, GETPC());
2656 return fst0;
2657 }
2658
2659 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2660 {
2661 uint64_t fdt2;
2662
2663 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2664 fdt2 = float64_maybe_silence_nan(fdt2);
2665 update_fcr31(env, GETPC());
2666 return fdt2;
2667 }
2668
2669 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2670 {
2671 uint64_t fdt2;
2672
2673 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2674 update_fcr31(env, GETPC());
2675 return fdt2;
2676 }
2677
2678 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2679 {
2680 uint64_t fdt2;
2681
2682 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2683 update_fcr31(env, GETPC());
2684 return fdt2;
2685 }
2686
2687 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2688 {
2689 uint64_t dt2;
2690
2691 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2692 if (get_float_exception_flags(&env->active_fpu.fp_status)
2693 & (float_flag_invalid | float_flag_overflow)) {
2694 dt2 = FP_TO_INT64_OVERFLOW;
2695 }
2696 update_fcr31(env, GETPC());
2697 return dt2;
2698 }
2699
2700 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2701 {
2702 uint64_t dt2;
2703
2704 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2705 if (get_float_exception_flags(&env->active_fpu.fp_status)
2706 & (float_flag_invalid | float_flag_overflow)) {
2707 dt2 = FP_TO_INT64_OVERFLOW;
2708 }
2709 update_fcr31(env, GETPC());
2710 return dt2;
2711 }
2712
2713 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2714 {
2715 uint32_t fst2;
2716 uint32_t fsth2;
2717
2718 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2719 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2720 update_fcr31(env, GETPC());
2721 return ((uint64_t)fsth2 << 32) | fst2;
2722 }
2723
2724 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2725 {
2726 uint32_t wt2;
2727 uint32_t wth2;
2728 int excp, excph;
2729
2730 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2731 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2732 if (excp & (float_flag_overflow | float_flag_invalid)) {
2733 wt2 = FP_TO_INT32_OVERFLOW;
2734 }
2735
2736 set_float_exception_flags(0, &env->active_fpu.fp_status);
2737 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2738 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2739 if (excph & (float_flag_overflow | float_flag_invalid)) {
2740 wth2 = FP_TO_INT32_OVERFLOW;
2741 }
2742
2743 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2744 update_fcr31(env, GETPC());
2745
2746 return ((uint64_t)wth2 << 32) | wt2;
2747 }
2748
2749 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2750 {
2751 uint32_t fst2;
2752
2753 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2754 fst2 = float32_maybe_silence_nan(fst2);
2755 update_fcr31(env, GETPC());
2756 return fst2;
2757 }
2758
2759 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2760 {
2761 uint32_t fst2;
2762
2763 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2764 update_fcr31(env, GETPC());
2765 return fst2;
2766 }
2767
2768 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2769 {
2770 uint32_t fst2;
2771
2772 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2773 update_fcr31(env, GETPC());
2774 return fst2;
2775 }
2776
2777 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2778 {
2779 uint32_t wt2;
2780
2781 wt2 = wt0;
2782 update_fcr31(env, GETPC());
2783 return wt2;
2784 }
2785
2786 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2787 {
2788 uint32_t wt2;
2789
2790 wt2 = wth0;
2791 update_fcr31(env, GETPC());
2792 return wt2;
2793 }
2794
2795 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2796 {
2797 uint32_t wt2;
2798
2799 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2800 if (get_float_exception_flags(&env->active_fpu.fp_status)
2801 & (float_flag_invalid | float_flag_overflow)) {
2802 wt2 = FP_TO_INT32_OVERFLOW;
2803 }
2804 update_fcr31(env, GETPC());
2805 return wt2;
2806 }
2807
2808 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2809 {
2810 uint32_t wt2;
2811
2812 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2813 if (get_float_exception_flags(&env->active_fpu.fp_status)
2814 & (float_flag_invalid | float_flag_overflow)) {
2815 wt2 = FP_TO_INT32_OVERFLOW;
2816 }
2817 update_fcr31(env, GETPC());
2818 return wt2;
2819 }
2820
2821 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2822 {
2823 uint64_t dt2;
2824
2825 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2826 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2827 restore_rounding_mode(env);
2828 if (get_float_exception_flags(&env->active_fpu.fp_status)
2829 & (float_flag_invalid | float_flag_overflow)) {
2830 dt2 = FP_TO_INT64_OVERFLOW;
2831 }
2832 update_fcr31(env, GETPC());
2833 return dt2;
2834 }
2835
2836 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2837 {
2838 uint64_t dt2;
2839
2840 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2841 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2842 restore_rounding_mode(env);
2843 if (get_float_exception_flags(&env->active_fpu.fp_status)
2844 & (float_flag_invalid | float_flag_overflow)) {
2845 dt2 = FP_TO_INT64_OVERFLOW;
2846 }
2847 update_fcr31(env, GETPC());
2848 return dt2;
2849 }
2850
2851 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2852 {
2853 uint32_t wt2;
2854
2855 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2856 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2857 restore_rounding_mode(env);
2858 if (get_float_exception_flags(&env->active_fpu.fp_status)
2859 & (float_flag_invalid | float_flag_overflow)) {
2860 wt2 = FP_TO_INT32_OVERFLOW;
2861 }
2862 update_fcr31(env, GETPC());
2863 return wt2;
2864 }
2865
2866 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2867 {
2868 uint32_t wt2;
2869
2870 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2871 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2872 restore_rounding_mode(env);
2873 if (get_float_exception_flags(&env->active_fpu.fp_status)
2874 & (float_flag_invalid | float_flag_overflow)) {
2875 wt2 = FP_TO_INT32_OVERFLOW;
2876 }
2877 update_fcr31(env, GETPC());
2878 return wt2;
2879 }
2880
2881 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2882 {
2883 uint64_t dt2;
2884
2885 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2886 if (get_float_exception_flags(&env->active_fpu.fp_status)
2887 & (float_flag_invalid | float_flag_overflow)) {
2888 dt2 = FP_TO_INT64_OVERFLOW;
2889 }
2890 update_fcr31(env, GETPC());
2891 return dt2;
2892 }
2893
2894 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2895 {
2896 uint64_t dt2;
2897
2898 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2899 if (get_float_exception_flags(&env->active_fpu.fp_status)
2900 & (float_flag_invalid | float_flag_overflow)) {
2901 dt2 = FP_TO_INT64_OVERFLOW;
2902 }
2903 update_fcr31(env, GETPC());
2904 return dt2;
2905 }
2906
2907 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2908 {
2909 uint32_t wt2;
2910
2911 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2912 if (get_float_exception_flags(&env->active_fpu.fp_status)
2913 & (float_flag_invalid | float_flag_overflow)) {
2914 wt2 = FP_TO_INT32_OVERFLOW;
2915 }
2916 update_fcr31(env, GETPC());
2917 return wt2;
2918 }
2919
2920 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2921 {
2922 uint32_t wt2;
2923
2924 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2925 if (get_float_exception_flags(&env->active_fpu.fp_status)
2926 & (float_flag_invalid | float_flag_overflow)) {
2927 wt2 = FP_TO_INT32_OVERFLOW;
2928 }
2929 update_fcr31(env, GETPC());
2930 return wt2;
2931 }
2932
2933 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2934 {
2935 uint64_t dt2;
2936
2937 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2938 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2939 restore_rounding_mode(env);
2940 if (get_float_exception_flags(&env->active_fpu.fp_status)
2941 & (float_flag_invalid | float_flag_overflow)) {
2942 dt2 = FP_TO_INT64_OVERFLOW;
2943 }
2944 update_fcr31(env, GETPC());
2945 return dt2;
2946 }
2947
2948 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2949 {
2950 uint64_t dt2;
2951
2952 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2953 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2954 restore_rounding_mode(env);
2955 if (get_float_exception_flags(&env->active_fpu.fp_status)
2956 & (float_flag_invalid | float_flag_overflow)) {
2957 dt2 = FP_TO_INT64_OVERFLOW;
2958 }
2959 update_fcr31(env, GETPC());
2960 return dt2;
2961 }
2962
2963 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2964 {
2965 uint32_t wt2;
2966
2967 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2968 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2969 restore_rounding_mode(env);
2970 if (get_float_exception_flags(&env->active_fpu.fp_status)
2971 & (float_flag_invalid | float_flag_overflow)) {
2972 wt2 = FP_TO_INT32_OVERFLOW;
2973 }
2974 update_fcr31(env, GETPC());
2975 return wt2;
2976 }
2977
2978 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2979 {
2980 uint32_t wt2;
2981
2982 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2983 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2984 restore_rounding_mode(env);
2985 if (get_float_exception_flags(&env->active_fpu.fp_status)
2986 & (float_flag_invalid | float_flag_overflow)) {
2987 wt2 = FP_TO_INT32_OVERFLOW;
2988 }
2989 update_fcr31(env, GETPC());
2990 return wt2;
2991 }
2992
2993 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2994 {
2995 uint64_t dt2;
2996
2997 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2998 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2999 restore_rounding_mode(env);
3000 if (get_float_exception_flags(&env->active_fpu.fp_status)
3001 & (float_flag_invalid | float_flag_overflow)) {
3002 dt2 = FP_TO_INT64_OVERFLOW;
3003 }
3004 update_fcr31(env, GETPC());
3005 return dt2;
3006 }
3007
3008 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
3009 {
3010 uint64_t dt2;
3011
3012 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3013 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3014 restore_rounding_mode(env);
3015 if (get_float_exception_flags(&env->active_fpu.fp_status)
3016 & (float_flag_invalid | float_flag_overflow)) {
3017 dt2 = FP_TO_INT64_OVERFLOW;
3018 }
3019 update_fcr31(env, GETPC());
3020 return dt2;
3021 }
3022
3023 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
3024 {
3025 uint32_t wt2;
3026
3027 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3028 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3029 restore_rounding_mode(env);
3030 if (get_float_exception_flags(&env->active_fpu.fp_status)
3031 & (float_flag_invalid | float_flag_overflow)) {
3032 wt2 = FP_TO_INT32_OVERFLOW;
3033 }
3034 update_fcr31(env, GETPC());
3035 return wt2;
3036 }
3037
3038 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
3039 {
3040 uint32_t wt2;
3041
3042 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3043 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3044 restore_rounding_mode(env);
3045 if (get_float_exception_flags(&env->active_fpu.fp_status)
3046 & (float_flag_invalid | float_flag_overflow)) {
3047 wt2 = FP_TO_INT32_OVERFLOW;
3048 }
3049 update_fcr31(env, GETPC());
3050 return wt2;
3051 }
3052
3053 /* unary operations, not modifying fp status */
3054 #define FLOAT_UNOP(name) \
3055 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3056 { \
3057 return float64_ ## name(fdt0); \
3058 } \
3059 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3060 { \
3061 return float32_ ## name(fst0); \
3062 } \
3063 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3064 { \
3065 uint32_t wt0; \
3066 uint32_t wth0; \
3067 \
3068 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3069 wth0 = float32_ ## name(fdt0 >> 32); \
3070 return ((uint64_t)wth0 << 32) | wt0; \
3071 }
3072 FLOAT_UNOP(abs)
3073 FLOAT_UNOP(chs)
3074 #undef FLOAT_UNOP
3075
3076 /* MIPS specific unary operations */
3077 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3078 {
3079 uint64_t fdt2;
3080
3081 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3082 update_fcr31(env, GETPC());
3083 return fdt2;
3084 }
3085
3086 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3087 {
3088 uint32_t fst2;
3089
3090 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3091 update_fcr31(env, GETPC());
3092 return fst2;
3093 }
3094
3095 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3096 {
3097 uint64_t fdt2;
3098
3099 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3100 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3101 update_fcr31(env, GETPC());
3102 return fdt2;
3103 }
3104
3105 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3106 {
3107 uint32_t fst2;
3108
3109 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3110 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3111 update_fcr31(env, GETPC());
3112 return fst2;
3113 }
3114
3115 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3116 {
3117 uint64_t fdt2;
3118
3119 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3120 update_fcr31(env, GETPC());
3121 return fdt2;
3122 }
3123
3124 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3125 {
3126 uint32_t fst2;
3127
3128 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3129 update_fcr31(env, GETPC());
3130 return fst2;
3131 }
3132
3133 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3134 {
3135 uint32_t fst2;
3136 uint32_t fsth2;
3137
3138 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3139 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3140 update_fcr31(env, GETPC());
3141 return ((uint64_t)fsth2 << 32) | fst2;
3142 }
3143
3144 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3145 {
3146 uint64_t fdt2;
3147
3148 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3149 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3150 update_fcr31(env, GETPC());
3151 return fdt2;
3152 }
3153
3154 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3155 {
3156 uint32_t fst2;
3157
3158 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3159 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3160 update_fcr31(env, GETPC());
3161 return fst2;
3162 }
3163
3164 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3165 {
3166 uint32_t fst2;
3167 uint32_t fsth2;
3168
3169 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3170 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3171 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3172 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3173 update_fcr31(env, GETPC());
3174 return ((uint64_t)fsth2 << 32) | fst2;
3175 }
3176
3177 #define FLOAT_RINT(name, bits) \
3178 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3179 uint ## bits ## _t fs) \
3180 { \
3181 uint ## bits ## _t fdret; \
3182 \
3183 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3184 update_fcr31(env, GETPC()); \
3185 return fdret; \
3186 }
3187
3188 FLOAT_RINT(rint_s, 32)
3189 FLOAT_RINT(rint_d, 64)
3190 #undef FLOAT_RINT
3191
3192 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3193 #define FLOAT_CLASS_QUIET_NAN 0x002
3194 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3195 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3196 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3197 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3198 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3199 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3200 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3201 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3202
3203 #define FLOAT_CLASS(name, bits) \
3204 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
3205 { \
3206 if (float ## bits ## _is_signaling_nan(arg)) { \
3207 return FLOAT_CLASS_SIGNALING_NAN; \
3208 } else if (float ## bits ## _is_quiet_nan(arg)) { \
3209 return FLOAT_CLASS_QUIET_NAN; \
3210 } else if (float ## bits ## _is_neg(arg)) { \
3211 if (float ## bits ## _is_infinity(arg)) { \
3212 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3213 } else if (float ## bits ## _is_zero(arg)) { \
3214 return FLOAT_CLASS_NEGATIVE_ZERO; \
3215 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3216 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3217 } else { \
3218 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3219 } \
3220 } else { \
3221 if (float ## bits ## _is_infinity(arg)) { \
3222 return FLOAT_CLASS_POSITIVE_INFINITY; \
3223 } else if (float ## bits ## _is_zero(arg)) { \
3224 return FLOAT_CLASS_POSITIVE_ZERO; \
3225 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3226 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3227 } else { \
3228 return FLOAT_CLASS_POSITIVE_NORMAL; \
3229 } \
3230 } \
3231 }
3232