cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / target-mips / op_helper.c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22
23 #include "helper.h"
24
25 #if !defined(CONFIG_USER_ONLY)
26 #include "exec/softmmu_exec.h"
27 #endif /* !defined(CONFIG_USER_ONLY) */
28
29 #ifndef CONFIG_USER_ONLY
30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
31 #endif
32
33 /*****************************************************************************/
34 /* Exceptions processing helpers */
35
36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
37 uint32_t exception,
38 int error_code,
39 uintptr_t pc)
40 {
41 CPUState *cs = CPU(mips_env_get_cpu(env));
42
43 if (exception < EXCP_SC) {
44 qemu_log("%s: %d %d\n", __func__, exception, error_code);
45 }
46 cs->exception_index = exception;
47 env->error_code = error_code;
48
49 if (pc) {
50 /* now we have a real cpu fault */
51 cpu_restore_state(cs, pc);
52 }
53
54 cpu_loop_exit(cs);
55 }
56
57 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
58 uint32_t exception,
59 uintptr_t pc)
60 {
61 do_raise_exception_err(env, exception, 0, pc);
62 }
63
64 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
65 int error_code)
66 {
67 do_raise_exception_err(env, exception, error_code, 0);
68 }
69
70 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
71 {
72 do_raise_exception(env, exception, 0);
73 }
74
75 #if defined(CONFIG_USER_ONLY)
76 #define HELPER_LD(name, insn, type) \
77 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
78 int mem_idx) \
79 { \
80 return (type) insn##_raw(addr); \
81 }
82 #else
83 #define HELPER_LD(name, insn, type) \
84 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
85 int mem_idx) \
86 { \
87 switch (mem_idx) \
88 { \
89 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
90 case 1: return (type) cpu_##insn##_super(env, addr); break; \
91 default: \
92 case 2: return (type) cpu_##insn##_user(env, addr); break; \
93 } \
94 }
95 #endif
96 HELPER_LD(lbu, ldub, uint8_t)
97 HELPER_LD(lw, ldl, int32_t)
98 #ifdef TARGET_MIPS64
99 HELPER_LD(ld, ldq, int64_t)
100 #endif
101 #undef HELPER_LD
102
103 #if defined(CONFIG_USER_ONLY)
104 #define HELPER_ST(name, insn, type) \
105 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
106 type val, int mem_idx) \
107 { \
108 insn##_raw(addr, val); \
109 }
110 #else
111 #define HELPER_ST(name, insn, type) \
112 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
113 type val, int mem_idx) \
114 { \
115 switch (mem_idx) \
116 { \
117 case 0: cpu_##insn##_kernel(env, addr, val); break; \
118 case 1: cpu_##insn##_super(env, addr, val); break; \
119 default: \
120 case 2: cpu_##insn##_user(env, addr, val); break; \
121 } \
122 }
123 #endif
124 HELPER_ST(sb, stb, uint8_t)
125 HELPER_ST(sw, stl, uint32_t)
126 #ifdef TARGET_MIPS64
127 HELPER_ST(sd, stq, uint64_t)
128 #endif
129 #undef HELPER_ST
130
131 target_ulong helper_clo (target_ulong arg1)
132 {
133 return clo32(arg1);
134 }
135
136 target_ulong helper_clz (target_ulong arg1)
137 {
138 return clz32(arg1);
139 }
140
141 #if defined(TARGET_MIPS64)
142 target_ulong helper_dclo (target_ulong arg1)
143 {
144 return clo64(arg1);
145 }
146
147 target_ulong helper_dclz (target_ulong arg1)
148 {
149 return clz64(arg1);
150 }
151 #endif /* TARGET_MIPS64 */
152
153 /* 64 bits arithmetic for 32 bits hosts */
154 static inline uint64_t get_HILO(CPUMIPSState *env)
155 {
156 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
157 }
158
159 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
160 {
161 target_ulong tmp;
162 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
163 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
164 return tmp;
165 }
166
167 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
168 {
169 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
170 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
171 return tmp;
172 }
173
174 /* Multiplication variants of the vr54xx. */
175 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
176 target_ulong arg2)
177 {
178 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
179 (int64_t)(int32_t)arg2));
180 }
181
182 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
183 target_ulong arg2)
184 {
185 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
186 (uint64_t)(uint32_t)arg2);
187 }
188
189 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
190 target_ulong arg2)
191 {
192 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
193 (int64_t)(int32_t)arg2);
194 }
195
196 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
197 target_ulong arg2)
198 {
199 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
200 (int64_t)(int32_t)arg2);
201 }
202
203 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
204 target_ulong arg2)
205 {
206 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
207 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
208 }
209
210 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
211 target_ulong arg2)
212 {
213 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
214 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
215 }
216
217 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
218 target_ulong arg2)
219 {
220 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
221 (int64_t)(int32_t)arg2);
222 }
223
224 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
225 target_ulong arg2)
226 {
227 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
228 (int64_t)(int32_t)arg2);
229 }
230
231 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
232 target_ulong arg2)
233 {
234 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
235 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
236 }
237
238 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
239 target_ulong arg2)
240 {
241 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
242 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
243 }
244
245 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
246 target_ulong arg2)
247 {
248 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
249 }
250
251 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
252 target_ulong arg2)
253 {
254 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
255 (uint64_t)(uint32_t)arg2);
256 }
257
258 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
259 target_ulong arg2)
260 {
261 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
262 (int64_t)(int32_t)arg2);
263 }
264
265 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
266 target_ulong arg2)
267 {
268 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
269 (uint64_t)(uint32_t)arg2);
270 }
271
272 #ifndef CONFIG_USER_ONLY
273
274 static inline hwaddr do_translate_address(CPUMIPSState *env,
275 target_ulong address,
276 int rw)
277 {
278 hwaddr lladdr;
279
280 lladdr = cpu_mips_translate_address(env, address, rw);
281
282 if (lladdr == -1LL) {
283 cpu_loop_exit(CPU(mips_env_get_cpu(env)));
284 } else {
285 return lladdr;
286 }
287 }
288
289 #define HELPER_LD_ATOMIC(name, insn) \
290 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
291 { \
292 env->lladdr = do_translate_address(env, arg, 0); \
293 env->llval = do_##insn(env, arg, mem_idx); \
294 return env->llval; \
295 }
296 HELPER_LD_ATOMIC(ll, lw)
297 #ifdef TARGET_MIPS64
298 HELPER_LD_ATOMIC(lld, ld)
299 #endif
300 #undef HELPER_LD_ATOMIC
301
302 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
303 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
304 target_ulong arg2, int mem_idx) \
305 { \
306 target_long tmp; \
307 \
308 if (arg2 & almask) { \
309 env->CP0_BadVAddr = arg2; \
310 helper_raise_exception(env, EXCP_AdES); \
311 } \
312 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
313 tmp = do_##ld_insn(env, arg2, mem_idx); \
314 if (tmp == env->llval) { \
315 do_##st_insn(env, arg2, arg1, mem_idx); \
316 return 1; \
317 } \
318 } \
319 return 0; \
320 }
321 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
322 #ifdef TARGET_MIPS64
323 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
324 #endif
325 #undef HELPER_ST_ATOMIC
326 #endif
327
328 #ifdef TARGET_WORDS_BIGENDIAN
329 #define GET_LMASK(v) ((v) & 3)
330 #define GET_OFFSET(addr, offset) (addr + (offset))
331 #else
332 #define GET_LMASK(v) (((v) & 3) ^ 3)
333 #define GET_OFFSET(addr, offset) (addr - (offset))
334 #endif
335
336 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
337 int mem_idx)
338 {
339 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
340
341 if (GET_LMASK(arg2) <= 2)
342 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
343
344 if (GET_LMASK(arg2) <= 1)
345 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
346
347 if (GET_LMASK(arg2) == 0)
348 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
349 }
350
351 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
352 int mem_idx)
353 {
354 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
355
356 if (GET_LMASK(arg2) >= 1)
357 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
358
359 if (GET_LMASK(arg2) >= 2)
360 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
361
362 if (GET_LMASK(arg2) == 3)
363 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
364 }
365
366 #if defined(TARGET_MIPS64)
367 /* "half" load and stores. We must do the memory access inline,
368 or fault handling won't work. */
369
370 #ifdef TARGET_WORDS_BIGENDIAN
371 #define GET_LMASK64(v) ((v) & 7)
372 #else
373 #define GET_LMASK64(v) (((v) & 7) ^ 7)
374 #endif
375
376 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
377 int mem_idx)
378 {
379 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
380
381 if (GET_LMASK64(arg2) <= 6)
382 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
383
384 if (GET_LMASK64(arg2) <= 5)
385 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
386
387 if (GET_LMASK64(arg2) <= 4)
388 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
389
390 if (GET_LMASK64(arg2) <= 3)
391 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
392
393 if (GET_LMASK64(arg2) <= 2)
394 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
395
396 if (GET_LMASK64(arg2) <= 1)
397 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
398
399 if (GET_LMASK64(arg2) <= 0)
400 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
401 }
402
403 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
404 int mem_idx)
405 {
406 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
407
408 if (GET_LMASK64(arg2) >= 1)
409 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
410
411 if (GET_LMASK64(arg2) >= 2)
412 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
413
414 if (GET_LMASK64(arg2) >= 3)
415 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
416
417 if (GET_LMASK64(arg2) >= 4)
418 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
419
420 if (GET_LMASK64(arg2) >= 5)
421 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
422
423 if (GET_LMASK64(arg2) >= 6)
424 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
425
426 if (GET_LMASK64(arg2) == 7)
427 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
428 }
429 #endif /* TARGET_MIPS64 */
430
431 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
432
433 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
434 uint32_t mem_idx)
435 {
436 target_ulong base_reglist = reglist & 0xf;
437 target_ulong do_r31 = reglist & 0x10;
438
439 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
440 target_ulong i;
441
442 for (i = 0; i < base_reglist; i++) {
443 env->active_tc.gpr[multiple_regs[i]] =
444 (target_long)do_lw(env, addr, mem_idx);
445 addr += 4;
446 }
447 }
448
449 if (do_r31) {
450 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
451 }
452 }
453
454 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
455 uint32_t mem_idx)
456 {
457 target_ulong base_reglist = reglist & 0xf;
458 target_ulong do_r31 = reglist & 0x10;
459
460 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
461 target_ulong i;
462
463 for (i = 0; i < base_reglist; i++) {
464 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
465 addr += 4;
466 }
467 }
468
469 if (do_r31) {
470 do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
471 }
472 }
473
474 #if defined(TARGET_MIPS64)
475 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
476 uint32_t mem_idx)
477 {
478 target_ulong base_reglist = reglist & 0xf;
479 target_ulong do_r31 = reglist & 0x10;
480
481 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
482 target_ulong i;
483
484 for (i = 0; i < base_reglist; i++) {
485 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
486 addr += 8;
487 }
488 }
489
490 if (do_r31) {
491 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
492 }
493 }
494
495 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
496 uint32_t mem_idx)
497 {
498 target_ulong base_reglist = reglist & 0xf;
499 target_ulong do_r31 = reglist & 0x10;
500
501 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
502 target_ulong i;
503
504 for (i = 0; i < base_reglist; i++) {
505 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
506 addr += 8;
507 }
508 }
509
510 if (do_r31) {
511 do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
512 }
513 }
514 #endif
515
516 #ifndef CONFIG_USER_ONLY
517 /* SMP helpers. */
518 static bool mips_vpe_is_wfi(MIPSCPU *c)
519 {
520 CPUState *cpu = CPU(c);
521 CPUMIPSState *env = &c->env;
522
523 /* If the VPE is halted but otherwise active, it means it's waiting for
524 an interrupt. */
525 return cpu->halted && mips_vpe_active(env);
526 }
527
528 static inline void mips_vpe_wake(MIPSCPU *c)
529 {
530 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
531 because there might be other conditions that state that c should
532 be sleeping. */
533 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
534 }
535
536 static inline void mips_vpe_sleep(MIPSCPU *cpu)
537 {
538 CPUState *cs = CPU(cpu);
539
540 /* The VPE was shut off, really go to bed.
541 Reset any old _WAKE requests. */
542 cs->halted = 1;
543 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
544 }
545
546 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
547 {
548 CPUMIPSState *c = &cpu->env;
549
550 /* FIXME: TC reschedule. */
551 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
552 mips_vpe_wake(cpu);
553 }
554 }
555
556 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
557 {
558 CPUMIPSState *c = &cpu->env;
559
560 /* FIXME: TC reschedule. */
561 if (!mips_vpe_active(c)) {
562 mips_vpe_sleep(cpu);
563 }
564 }
565
566 /**
567 * mips_cpu_map_tc:
568 * @env: CPU from which mapping is performed.
569 * @tc: Should point to an int with the value of the global TC index.
570 *
571 * This function will transform @tc into a local index within the
572 * returned #CPUMIPSState.
573 */
574 /* FIXME: This code assumes that all VPEs have the same number of TCs,
575 which depends on runtime setup. Can probably be fixed by
576 walking the list of CPUMIPSStates. */
577 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
578 {
579 MIPSCPU *cpu;
580 CPUState *cs;
581 CPUState *other_cs;
582 int vpe_idx;
583 int tc_idx = *tc;
584
585 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
586 /* Not allowed to address other CPUs. */
587 *tc = env->current_tc;
588 return env;
589 }
590
591 cs = CPU(mips_env_get_cpu(env));
592 vpe_idx = tc_idx / cs->nr_threads;
593 *tc = tc_idx % cs->nr_threads;
594 other_cs = qemu_get_cpu(vpe_idx);
595 if (other_cs == NULL) {
596 return env;
597 }
598 cpu = MIPS_CPU(other_cs);
599 return &cpu->env;
600 }
601
602 /* The per VPE CP0_Status register shares some fields with the per TC
603 CP0_TCStatus registers. These fields are wired to the same registers,
604 so changes to either of them should be reflected on both registers.
605
606 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
607
608 These helper call synchronizes the regs for a given cpu. */
609
610 /* Called for updates to CP0_Status. */
611 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
612 {
613 int32_t tcstatus, *tcst;
614 uint32_t v = cpu->CP0_Status;
615 uint32_t cu, mx, asid, ksu;
616 uint32_t mask = ((1 << CP0TCSt_TCU3)
617 | (1 << CP0TCSt_TCU2)
618 | (1 << CP0TCSt_TCU1)
619 | (1 << CP0TCSt_TCU0)
620 | (1 << CP0TCSt_TMX)
621 | (3 << CP0TCSt_TKSU)
622 | (0xff << CP0TCSt_TASID));
623
624 cu = (v >> CP0St_CU0) & 0xf;
625 mx = (v >> CP0St_MX) & 0x1;
626 ksu = (v >> CP0St_KSU) & 0x3;
627 asid = env->CP0_EntryHi & 0xff;
628
629 tcstatus = cu << CP0TCSt_TCU0;
630 tcstatus |= mx << CP0TCSt_TMX;
631 tcstatus |= ksu << CP0TCSt_TKSU;
632 tcstatus |= asid;
633
634 if (tc == cpu->current_tc) {
635 tcst = &cpu->active_tc.CP0_TCStatus;
636 } else {
637 tcst = &cpu->tcs[tc].CP0_TCStatus;
638 }
639
640 *tcst &= ~mask;
641 *tcst |= tcstatus;
642 compute_hflags(cpu);
643 }
644
645 /* Called for updates to CP0_TCStatus. */
646 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
647 target_ulong v)
648 {
649 uint32_t status;
650 uint32_t tcu, tmx, tasid, tksu;
651 uint32_t mask = ((1 << CP0St_CU3)
652 | (1 << CP0St_CU2)
653 | (1 << CP0St_CU1)
654 | (1 << CP0St_CU0)
655 | (1 << CP0St_MX)
656 | (3 << CP0St_KSU));
657
658 tcu = (v >> CP0TCSt_TCU0) & 0xf;
659 tmx = (v >> CP0TCSt_TMX) & 0x1;
660 tasid = v & 0xff;
661 tksu = (v >> CP0TCSt_TKSU) & 0x3;
662
663 status = tcu << CP0St_CU0;
664 status |= tmx << CP0St_MX;
665 status |= tksu << CP0St_KSU;
666
667 cpu->CP0_Status &= ~mask;
668 cpu->CP0_Status |= status;
669
670 /* Sync the TASID with EntryHi. */
671 cpu->CP0_EntryHi &= ~0xff;
672 cpu->CP0_EntryHi = tasid;
673
674 compute_hflags(cpu);
675 }
676
677 /* Called for updates to CP0_EntryHi. */
678 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
679 {
680 int32_t *tcst;
681 uint32_t asid, v = cpu->CP0_EntryHi;
682
683 asid = v & 0xff;
684
685 if (tc == cpu->current_tc) {
686 tcst = &cpu->active_tc.CP0_TCStatus;
687 } else {
688 tcst = &cpu->tcs[tc].CP0_TCStatus;
689 }
690
691 *tcst &= ~0xff;
692 *tcst |= asid;
693 }
694
695 /* CP0 helpers */
696 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
697 {
698 return env->mvp->CP0_MVPControl;
699 }
700
701 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
702 {
703 return env->mvp->CP0_MVPConf0;
704 }
705
706 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
707 {
708 return env->mvp->CP0_MVPConf1;
709 }
710
711 target_ulong helper_mfc0_random(CPUMIPSState *env)
712 {
713 return (int32_t)cpu_mips_get_random(env);
714 }
715
716 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
717 {
718 return env->active_tc.CP0_TCStatus;
719 }
720
721 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
722 {
723 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
724 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
725
726 if (other_tc == other->current_tc)
727 return other->active_tc.CP0_TCStatus;
728 else
729 return other->tcs[other_tc].CP0_TCStatus;
730 }
731
732 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
733 {
734 return env->active_tc.CP0_TCBind;
735 }
736
737 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
738 {
739 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
740 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
741
742 if (other_tc == other->current_tc)
743 return other->active_tc.CP0_TCBind;
744 else
745 return other->tcs[other_tc].CP0_TCBind;
746 }
747
748 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
749 {
750 return env->active_tc.PC;
751 }
752
753 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
754 {
755 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
756 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
757
758 if (other_tc == other->current_tc)
759 return other->active_tc.PC;
760 else
761 return other->tcs[other_tc].PC;
762 }
763
764 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
765 {
766 return env->active_tc.CP0_TCHalt;
767 }
768
769 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
770 {
771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
772 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
773
774 if (other_tc == other->current_tc)
775 return other->active_tc.CP0_TCHalt;
776 else
777 return other->tcs[other_tc].CP0_TCHalt;
778 }
779
780 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
781 {
782 return env->active_tc.CP0_TCContext;
783 }
784
785 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
786 {
787 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
788 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
789
790 if (other_tc == other->current_tc)
791 return other->active_tc.CP0_TCContext;
792 else
793 return other->tcs[other_tc].CP0_TCContext;
794 }
795
796 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
797 {
798 return env->active_tc.CP0_TCSchedule;
799 }
800
801 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
802 {
803 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
804 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
805
806 if (other_tc == other->current_tc)
807 return other->active_tc.CP0_TCSchedule;
808 else
809 return other->tcs[other_tc].CP0_TCSchedule;
810 }
811
812 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
813 {
814 return env->active_tc.CP0_TCScheFBack;
815 }
816
817 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
818 {
819 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
820 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
821
822 if (other_tc == other->current_tc)
823 return other->active_tc.CP0_TCScheFBack;
824 else
825 return other->tcs[other_tc].CP0_TCScheFBack;
826 }
827
828 target_ulong helper_mfc0_count(CPUMIPSState *env)
829 {
830 return (int32_t)cpu_mips_get_count(env);
831 }
832
833 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
834 {
835 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
836 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
837
838 return other->CP0_EntryHi;
839 }
840
841 target_ulong helper_mftc0_cause(CPUMIPSState *env)
842 {
843 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
844 int32_t tccause;
845 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
846
847 if (other_tc == other->current_tc) {
848 tccause = other->CP0_Cause;
849 } else {
850 tccause = other->CP0_Cause;
851 }
852
853 return tccause;
854 }
855
856 target_ulong helper_mftc0_status(CPUMIPSState *env)
857 {
858 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
859 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
860
861 return other->CP0_Status;
862 }
863
864 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
865 {
866 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
867 }
868
869 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
870 {
871 return (int32_t)env->CP0_WatchLo[sel];
872 }
873
874 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
875 {
876 return env->CP0_WatchHi[sel];
877 }
878
879 target_ulong helper_mfc0_debug(CPUMIPSState *env)
880 {
881 target_ulong t0 = env->CP0_Debug;
882 if (env->hflags & MIPS_HFLAG_DM)
883 t0 |= 1 << CP0DB_DM;
884
885 return t0;
886 }
887
888 target_ulong helper_mftc0_debug(CPUMIPSState *env)
889 {
890 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
891 int32_t tcstatus;
892 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
893
894 if (other_tc == other->current_tc)
895 tcstatus = other->active_tc.CP0_Debug_tcstatus;
896 else
897 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
898
899 /* XXX: Might be wrong, check with EJTAG spec. */
900 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
901 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
902 }
903
904 #if defined(TARGET_MIPS64)
905 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
906 {
907 return env->active_tc.PC;
908 }
909
910 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
911 {
912 return env->active_tc.CP0_TCHalt;
913 }
914
915 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
916 {
917 return env->active_tc.CP0_TCContext;
918 }
919
920 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
921 {
922 return env->active_tc.CP0_TCSchedule;
923 }
924
925 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
926 {
927 return env->active_tc.CP0_TCScheFBack;
928 }
929
930 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
931 {
932 return env->lladdr >> env->CP0_LLAddr_shift;
933 }
934
935 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
936 {
937 return env->CP0_WatchLo[sel];
938 }
939 #endif /* TARGET_MIPS64 */
940
941 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
942 {
943 int num = 1;
944 unsigned int tmp = env->tlb->nb_tlb;
945
946 do {
947 tmp >>= 1;
948 num <<= 1;
949 } while (tmp);
950 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
951 }
952
953 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
954 {
955 uint32_t mask = 0;
956 uint32_t newval;
957
958 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
959 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
960 (1 << CP0MVPCo_EVP);
961 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
962 mask |= (1 << CP0MVPCo_STLB);
963 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
964
965 // TODO: Enable/disable shared TLB, enable/disable VPEs.
966
967 env->mvp->CP0_MVPControl = newval;
968 }
969
970 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
971 {
972 uint32_t mask;
973 uint32_t newval;
974
975 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
976 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
977 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
978
979 /* Yield scheduler intercept not implemented. */
980 /* Gating storage scheduler intercept not implemented. */
981
982 // TODO: Enable/disable TCs.
983
984 env->CP0_VPEControl = newval;
985 }
986
987 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
988 {
989 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
990 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
991 uint32_t mask;
992 uint32_t newval;
993
994 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
995 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
996 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
997
998 /* TODO: Enable/disable TCs. */
999
1000 other->CP0_VPEControl = newval;
1001 }
1002
1003 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1004 {
1005 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1006 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1007 /* FIXME: Mask away return zero on read bits. */
1008 return other->CP0_VPEControl;
1009 }
1010
1011 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1012 {
1013 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1014 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1015
1016 return other->CP0_VPEConf0;
1017 }
1018
1019 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1020 {
1021 uint32_t mask = 0;
1022 uint32_t newval;
1023
1024 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1025 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1026 mask |= (0xff << CP0VPEC0_XTC);
1027 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1028 }
1029 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1030
1031 // TODO: TC exclusive handling due to ERL/EXL.
1032
1033 env->CP0_VPEConf0 = newval;
1034 }
1035
1036 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1037 {
1038 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1039 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1040 uint32_t mask = 0;
1041 uint32_t newval;
1042
1043 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1044 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1045
1046 /* TODO: TC exclusive handling due to ERL/EXL. */
1047 other->CP0_VPEConf0 = newval;
1048 }
1049
1050 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1051 {
1052 uint32_t mask = 0;
1053 uint32_t newval;
1054
1055 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1056 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1057 (0xff << CP0VPEC1_NCP1);
1058 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1059
1060 /* UDI not implemented. */
1061 /* CP2 not implemented. */
1062
1063 // TODO: Handle FPU (CP1) binding.
1064
1065 env->CP0_VPEConf1 = newval;
1066 }
1067
1068 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1069 {
1070 /* Yield qualifier inputs not implemented. */
1071 env->CP0_YQMask = 0x00000000;
1072 }
1073
1074 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1075 {
1076 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1077 }
1078
1079 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1080 {
1081 /* Large physaddr (PABITS) not implemented */
1082 /* 1k pages not implemented */
1083 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1084 }
1085
1086 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1087 {
1088 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1089 uint32_t newval;
1090
1091 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1092
1093 env->active_tc.CP0_TCStatus = newval;
1094 sync_c0_tcstatus(env, env->current_tc, newval);
1095 }
1096
1097 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1098 {
1099 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1100 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1101
1102 if (other_tc == other->current_tc)
1103 other->active_tc.CP0_TCStatus = arg1;
1104 else
1105 other->tcs[other_tc].CP0_TCStatus = arg1;
1106 sync_c0_tcstatus(other, other_tc, arg1);
1107 }
1108
1109 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1110 {
1111 uint32_t mask = (1 << CP0TCBd_TBE);
1112 uint32_t newval;
1113
1114 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1115 mask |= (1 << CP0TCBd_CurVPE);
1116 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1117 env->active_tc.CP0_TCBind = newval;
1118 }
1119
1120 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1121 {
1122 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1123 uint32_t mask = (1 << CP0TCBd_TBE);
1124 uint32_t newval;
1125 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1126
1127 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1128 mask |= (1 << CP0TCBd_CurVPE);
1129 if (other_tc == other->current_tc) {
1130 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1131 other->active_tc.CP0_TCBind = newval;
1132 } else {
1133 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1134 other->tcs[other_tc].CP0_TCBind = newval;
1135 }
1136 }
1137
1138 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1139 {
1140 env->active_tc.PC = arg1;
1141 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1142 env->lladdr = 0ULL;
1143 /* MIPS16 not implemented. */
1144 }
1145
1146 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1147 {
1148 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1149 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1150
1151 if (other_tc == other->current_tc) {
1152 other->active_tc.PC = arg1;
1153 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1154 other->lladdr = 0ULL;
1155 /* MIPS16 not implemented. */
1156 } else {
1157 other->tcs[other_tc].PC = arg1;
1158 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159 other->lladdr = 0ULL;
1160 /* MIPS16 not implemented. */
1161 }
1162 }
1163
1164 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1165 {
1166 MIPSCPU *cpu = mips_env_get_cpu(env);
1167
1168 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1169
1170 // TODO: Halt TC / Restart (if allocated+active) TC.
1171 if (env->active_tc.CP0_TCHalt & 1) {
1172 mips_tc_sleep(cpu, env->current_tc);
1173 } else {
1174 mips_tc_wake(cpu, env->current_tc);
1175 }
1176 }
1177
1178 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1179 {
1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1182 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1183
1184 // TODO: Halt TC / Restart (if allocated+active) TC.
1185
1186 if (other_tc == other->current_tc)
1187 other->active_tc.CP0_TCHalt = arg1;
1188 else
1189 other->tcs[other_tc].CP0_TCHalt = arg1;
1190
1191 if (arg1 & 1) {
1192 mips_tc_sleep(other_cpu, other_tc);
1193 } else {
1194 mips_tc_wake(other_cpu, other_tc);
1195 }
1196 }
1197
1198 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1199 {
1200 env->active_tc.CP0_TCContext = arg1;
1201 }
1202
1203 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1204 {
1205 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1206 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1207
1208 if (other_tc == other->current_tc)
1209 other->active_tc.CP0_TCContext = arg1;
1210 else
1211 other->tcs[other_tc].CP0_TCContext = arg1;
1212 }
1213
1214 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1215 {
1216 env->active_tc.CP0_TCSchedule = arg1;
1217 }
1218
1219 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1220 {
1221 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1222 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1223
1224 if (other_tc == other->current_tc)
1225 other->active_tc.CP0_TCSchedule = arg1;
1226 else
1227 other->tcs[other_tc].CP0_TCSchedule = arg1;
1228 }
1229
1230 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1231 {
1232 env->active_tc.CP0_TCScheFBack = arg1;
1233 }
1234
1235 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1236 {
1237 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1238 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1239
1240 if (other_tc == other->current_tc)
1241 other->active_tc.CP0_TCScheFBack = arg1;
1242 else
1243 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1244 }
1245
1246 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1247 {
1248 /* Large physaddr (PABITS) not implemented */
1249 /* 1k pages not implemented */
1250 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1251 }
1252
1253 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1254 {
1255 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1256 }
1257
1258 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1259 {
1260 /* 1k pages not implemented */
1261 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1262 }
1263
1264 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1265 {
1266 /* SmartMIPS not implemented */
1267 /* Large physaddr (PABITS) not implemented */
1268 /* 1k pages not implemented */
1269 env->CP0_PageGrain = 0;
1270 }
1271
1272 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1273 {
1274 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1275 }
1276
1277 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1278 {
1279 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1280 }
1281
1282 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1283 {
1284 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1285 }
1286
1287 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1288 {
1289 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1290 }
1291
1292 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1293 {
1294 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1295 }
1296
1297 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1298 {
1299 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1300 }
1301
1302 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1303 {
1304 env->CP0_HWREna = arg1 & 0x0000000F;
1305 }
1306
1307 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1308 {
1309 cpu_mips_store_count(env, arg1);
1310 }
1311
1312 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1313 {
1314 target_ulong old, val;
1315
1316 /* 1k pages not implemented */
1317 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1318 #if defined(TARGET_MIPS64)
1319 val &= env->SEGMask;
1320 #endif
1321 old = env->CP0_EntryHi;
1322 env->CP0_EntryHi = val;
1323 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1324 sync_c0_entryhi(env, env->current_tc);
1325 }
1326 /* If the ASID changes, flush qemu's TLB. */
1327 if ((old & 0xFF) != (val & 0xFF))
1328 cpu_mips_tlb_flush(env, 1);
1329 }
1330
1331 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1332 {
1333 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1334 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1335
1336 other->CP0_EntryHi = arg1;
1337 sync_c0_entryhi(other, other_tc);
1338 }
1339
1340 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1341 {
1342 cpu_mips_store_compare(env, arg1);
1343 }
1344
1345 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1346 {
1347 MIPSCPU *cpu = mips_env_get_cpu(env);
1348 uint32_t val, old;
1349 uint32_t mask = env->CP0_Status_rw_bitmask;
1350
1351 val = arg1 & mask;
1352 old = env->CP0_Status;
1353 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1354 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1355 sync_c0_status(env, env, env->current_tc);
1356 } else {
1357 compute_hflags(env);
1358 }
1359
1360 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1361 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1362 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1363 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1364 env->CP0_Cause);
1365 switch (env->hflags & MIPS_HFLAG_KSU) {
1366 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1367 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1368 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1369 default:
1370 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1371 break;
1372 }
1373 }
1374 }
1375
1376 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1377 {
1378 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1379 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1380
1381 other->CP0_Status = arg1 & ~0xf1000018;
1382 sync_c0_status(env, other, other_tc);
1383 }
1384
1385 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1386 {
1387 /* vectored interrupts not implemented, no performance counters. */
1388 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1389 }
1390
1391 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1392 {
1393 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1394 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1395 }
1396
1397 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1398 {
1399 uint32_t mask = 0x00C00300;
1400 uint32_t old = cpu->CP0_Cause;
1401 int i;
1402
1403 if (cpu->insn_flags & ISA_MIPS32R2) {
1404 mask |= 1 << CP0Ca_DC;
1405 }
1406
1407 cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1408
1409 if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1410 if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1411 cpu_mips_stop_count(cpu);
1412 } else {
1413 cpu_mips_start_count(cpu);
1414 }
1415 }
1416
1417 /* Set/reset software interrupts */
1418 for (i = 0 ; i < 2 ; i++) {
1419 if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1420 cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1421 }
1422 }
1423 }
1424
1425 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1426 {
1427 mtc0_cause(env, arg1);
1428 }
1429
1430 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1431 {
1432 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1433 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1434
1435 mtc0_cause(other, arg1);
1436 }
1437
1438 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1439 {
1440 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1441 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1442
1443 return other->CP0_EPC;
1444 }
1445
1446 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1447 {
1448 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1449 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1450
1451 return other->CP0_EBase;
1452 }
1453
1454 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1455 {
1456 /* vectored interrupts not implemented */
1457 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1458 }
1459
1460 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1461 {
1462 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1463 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1464 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1465 }
1466
1467 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1468 {
1469 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1470 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1471
1472 switch (idx) {
1473 case 0: return other->CP0_Config0;
1474 case 1: return other->CP0_Config1;
1475 case 2: return other->CP0_Config2;
1476 case 3: return other->CP0_Config3;
1477 /* 4 and 5 are reserved. */
1478 case 6: return other->CP0_Config6;
1479 case 7: return other->CP0_Config7;
1480 default:
1481 break;
1482 }
1483 return 0;
1484 }
1485
1486 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1487 {
1488 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1489 }
1490
1491 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1492 {
1493 /* tertiary/secondary caches not implemented */
1494 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1495 }
1496
1497 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1498 {
1499 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1500 (arg1 & env->CP0_Config4_rw_bitmask);
1501 }
1502
1503 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1504 {
1505 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1506 (arg1 & env->CP0_Config5_rw_bitmask);
1507 }
1508
1509 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1510 {
1511 target_long mask = env->CP0_LLAddr_rw_bitmask;
1512 arg1 = arg1 << env->CP0_LLAddr_shift;
1513 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1514 }
1515
1516 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1517 {
1518 /* Watch exceptions for instructions, data loads, data stores
1519 not implemented. */
1520 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1521 }
1522
1523 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1524 {
1525 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1526 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1527 }
1528
1529 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1530 {
1531 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1532 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1533 }
1534
1535 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1536 {
1537 env->CP0_Framemask = arg1; /* XXX */
1538 }
1539
1540 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1541 {
1542 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1543 if (arg1 & (1 << CP0DB_DM))
1544 env->hflags |= MIPS_HFLAG_DM;
1545 else
1546 env->hflags &= ~MIPS_HFLAG_DM;
1547 }
1548
1549 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1550 {
1551 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1552 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1553 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1554
1555 /* XXX: Might be wrong, check with EJTAG spec. */
1556 if (other_tc == other->current_tc)
1557 other->active_tc.CP0_Debug_tcstatus = val;
1558 else
1559 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1560 other->CP0_Debug = (other->CP0_Debug &
1561 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1562 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1563 }
1564
1565 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1566 {
1567 env->CP0_Performance0 = arg1 & 0x000007ff;
1568 }
1569
1570 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1571 {
1572 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1573 }
1574
1575 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1576 {
1577 env->CP0_DataLo = arg1; /* XXX */
1578 }
1579
1580 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1581 {
1582 env->CP0_TagHi = arg1; /* XXX */
1583 }
1584
1585 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1586 {
1587 env->CP0_DataHi = arg1; /* XXX */
1588 }
1589
1590 /* MIPS MT functions */
1591 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1592 {
1593 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1594 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1595
1596 if (other_tc == other->current_tc)
1597 return other->active_tc.gpr[sel];
1598 else
1599 return other->tcs[other_tc].gpr[sel];
1600 }
1601
1602 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1603 {
1604 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1605 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1606
1607 if (other_tc == other->current_tc)
1608 return other->active_tc.LO[sel];
1609 else
1610 return other->tcs[other_tc].LO[sel];
1611 }
1612
1613 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1614 {
1615 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1616 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1617
1618 if (other_tc == other->current_tc)
1619 return other->active_tc.HI[sel];
1620 else
1621 return other->tcs[other_tc].HI[sel];
1622 }
1623
1624 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1625 {
1626 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1627 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1628
1629 if (other_tc == other->current_tc)
1630 return other->active_tc.ACX[sel];
1631 else
1632 return other->tcs[other_tc].ACX[sel];
1633 }
1634
1635 target_ulong helper_mftdsp(CPUMIPSState *env)
1636 {
1637 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1638 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1639
1640 if (other_tc == other->current_tc)
1641 return other->active_tc.DSPControl;
1642 else
1643 return other->tcs[other_tc].DSPControl;
1644 }
1645
1646 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1647 {
1648 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1649 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1650
1651 if (other_tc == other->current_tc)
1652 other->active_tc.gpr[sel] = arg1;
1653 else
1654 other->tcs[other_tc].gpr[sel] = arg1;
1655 }
1656
1657 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1658 {
1659 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1660 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1661
1662 if (other_tc == other->current_tc)
1663 other->active_tc.LO[sel] = arg1;
1664 else
1665 other->tcs[other_tc].LO[sel] = arg1;
1666 }
1667
1668 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1669 {
1670 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1671 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1672
1673 if (other_tc == other->current_tc)
1674 other->active_tc.HI[sel] = arg1;
1675 else
1676 other->tcs[other_tc].HI[sel] = arg1;
1677 }
1678
1679 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1680 {
1681 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1682 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1683
1684 if (other_tc == other->current_tc)
1685 other->active_tc.ACX[sel] = arg1;
1686 else
1687 other->tcs[other_tc].ACX[sel] = arg1;
1688 }
1689
1690 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1691 {
1692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1693 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1694
1695 if (other_tc == other->current_tc)
1696 other->active_tc.DSPControl = arg1;
1697 else
1698 other->tcs[other_tc].DSPControl = arg1;
1699 }
1700
1701 /* MIPS MT functions */
1702 target_ulong helper_dmt(void)
1703 {
1704 // TODO
1705 return 0;
1706 }
1707
1708 target_ulong helper_emt(void)
1709 {
1710 // TODO
1711 return 0;
1712 }
1713
1714 target_ulong helper_dvpe(CPUMIPSState *env)
1715 {
1716 CPUState *other_cs = first_cpu;
1717 target_ulong prev = env->mvp->CP0_MVPControl;
1718
1719 CPU_FOREACH(other_cs) {
1720 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1721 /* Turn off all VPEs except the one executing the dvpe. */
1722 if (&other_cpu->env != env) {
1723 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1724 mips_vpe_sleep(other_cpu);
1725 }
1726 }
1727 return prev;
1728 }
1729
1730 target_ulong helper_evpe(CPUMIPSState *env)
1731 {
1732 CPUState *other_cs = first_cpu;
1733 target_ulong prev = env->mvp->CP0_MVPControl;
1734
1735 CPU_FOREACH(other_cs) {
1736 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1737
1738 if (&other_cpu->env != env
1739 /* If the VPE is WFI, don't disturb its sleep. */
1740 && !mips_vpe_is_wfi(other_cpu)) {
1741 /* Enable the VPE. */
1742 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1743 mips_vpe_wake(other_cpu); /* And wake it up. */
1744 }
1745 }
1746 return prev;
1747 }
1748 #endif /* !CONFIG_USER_ONLY */
1749
1750 void helper_fork(target_ulong arg1, target_ulong arg2)
1751 {
1752 // arg1 = rt, arg2 = rs
1753 // TODO: store to TC register
1754 }
1755
1756 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1757 {
1758 target_long arg1 = arg;
1759
1760 if (arg1 < 0) {
1761 /* No scheduling policy implemented. */
1762 if (arg1 != -2) {
1763 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1764 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1765 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1766 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1767 helper_raise_exception(env, EXCP_THREAD);
1768 }
1769 }
1770 } else if (arg1 == 0) {
1771 if (0 /* TODO: TC underflow */) {
1772 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1773 helper_raise_exception(env, EXCP_THREAD);
1774 } else {
1775 // TODO: Deallocate TC
1776 }
1777 } else if (arg1 > 0) {
1778 /* Yield qualifier inputs not implemented. */
1779 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1780 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1781 helper_raise_exception(env, EXCP_THREAD);
1782 }
1783 return env->CP0_YQMask;
1784 }
1785
1786 #ifndef CONFIG_USER_ONLY
1787 /* TLB management */
1788 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1789 {
1790 MIPSCPU *cpu = mips_env_get_cpu(env);
1791
1792 /* Flush qemu's TLB and discard all shadowed entries. */
1793 tlb_flush(CPU(cpu), flush_global);
1794 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1795 }
1796
1797 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1798 {
1799 /* Discard entries from env->tlb[first] onwards. */
1800 while (env->tlb->tlb_in_use > first) {
1801 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1802 }
1803 }
1804
1805 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1806 {
1807 r4k_tlb_t *tlb;
1808
1809 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1810 tlb = &env->tlb->mmu.r4k.tlb[idx];
1811 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1812 #if defined(TARGET_MIPS64)
1813 tlb->VPN &= env->SEGMask;
1814 #endif
1815 tlb->ASID = env->CP0_EntryHi & 0xFF;
1816 tlb->PageMask = env->CP0_PageMask;
1817 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1818 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1819 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1820 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1821 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1822 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1823 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1824 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1825 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1826 }
1827
1828 void r4k_helper_tlbwi(CPUMIPSState *env)
1829 {
1830 r4k_tlb_t *tlb;
1831 int idx;
1832 target_ulong VPN;
1833 uint8_t ASID;
1834 bool G, V0, D0, V1, D1;
1835
1836 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1837 tlb = &env->tlb->mmu.r4k.tlb[idx];
1838 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1839 #if defined(TARGET_MIPS64)
1840 VPN &= env->SEGMask;
1841 #endif
1842 ASID = env->CP0_EntryHi & 0xff;
1843 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1844 V0 = (env->CP0_EntryLo0 & 2) != 0;
1845 D0 = (env->CP0_EntryLo0 & 4) != 0;
1846 V1 = (env->CP0_EntryLo1 & 2) != 0;
1847 D1 = (env->CP0_EntryLo1 & 4) != 0;
1848
1849 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1850 permissions on the current entry. */
1851 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1852 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1853 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1854 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1855 }
1856
1857 r4k_invalidate_tlb(env, idx, 0);
1858 r4k_fill_tlb(env, idx);
1859 }
1860
1861 void r4k_helper_tlbwr(CPUMIPSState *env)
1862 {
1863 int r = cpu_mips_get_random(env);
1864
1865 r4k_invalidate_tlb(env, r, 1);
1866 r4k_fill_tlb(env, r);
1867 }
1868
1869 void r4k_helper_tlbp(CPUMIPSState *env)
1870 {
1871 r4k_tlb_t *tlb;
1872 target_ulong mask;
1873 target_ulong tag;
1874 target_ulong VPN;
1875 uint8_t ASID;
1876 int i;
1877
1878 ASID = env->CP0_EntryHi & 0xFF;
1879 for (i = 0; i < env->tlb->nb_tlb; i++) {
1880 tlb = &env->tlb->mmu.r4k.tlb[i];
1881 /* 1k pages are not supported. */
1882 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1883 tag = env->CP0_EntryHi & ~mask;
1884 VPN = tlb->VPN & ~mask;
1885 #if defined(TARGET_MIPS64)
1886 tag &= env->SEGMask;
1887 #endif
1888 /* Check ASID, virtual page number & size */
1889 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1890 /* TLB match */
1891 env->CP0_Index = i;
1892 break;
1893 }
1894 }
1895 if (i == env->tlb->nb_tlb) {
1896 /* No match. Discard any shadow entries, if any of them match. */
1897 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1898 tlb = &env->tlb->mmu.r4k.tlb[i];
1899 /* 1k pages are not supported. */
1900 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1901 tag = env->CP0_EntryHi & ~mask;
1902 VPN = tlb->VPN & ~mask;
1903 #if defined(TARGET_MIPS64)
1904 tag &= env->SEGMask;
1905 #endif
1906 /* Check ASID, virtual page number & size */
1907 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1908 r4k_mips_tlb_flush_extra (env, i);
1909 break;
1910 }
1911 }
1912
1913 env->CP0_Index |= 0x80000000;
1914 }
1915 }
1916
1917 void r4k_helper_tlbr(CPUMIPSState *env)
1918 {
1919 r4k_tlb_t *tlb;
1920 uint8_t ASID;
1921 int idx;
1922
1923 ASID = env->CP0_EntryHi & 0xFF;
1924 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1925 tlb = &env->tlb->mmu.r4k.tlb[idx];
1926
1927 /* If this will change the current ASID, flush qemu's TLB. */
1928 if (ASID != tlb->ASID)
1929 cpu_mips_tlb_flush (env, 1);
1930
1931 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1932
1933 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1934 env->CP0_PageMask = tlb->PageMask;
1935 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1936 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1937 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1938 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1939 }
1940
1941 void helper_tlbwi(CPUMIPSState *env)
1942 {
1943 env->tlb->helper_tlbwi(env);
1944 }
1945
1946 void helper_tlbwr(CPUMIPSState *env)
1947 {
1948 env->tlb->helper_tlbwr(env);
1949 }
1950
1951 void helper_tlbp(CPUMIPSState *env)
1952 {
1953 env->tlb->helper_tlbp(env);
1954 }
1955
1956 void helper_tlbr(CPUMIPSState *env)
1957 {
1958 env->tlb->helper_tlbr(env);
1959 }
1960
1961 /* Specials */
1962 target_ulong helper_di(CPUMIPSState *env)
1963 {
1964 target_ulong t0 = env->CP0_Status;
1965
1966 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1967 return t0;
1968 }
1969
1970 target_ulong helper_ei(CPUMIPSState *env)
1971 {
1972 target_ulong t0 = env->CP0_Status;
1973
1974 env->CP0_Status = t0 | (1 << CP0St_IE);
1975 return t0;
1976 }
1977
1978 static void debug_pre_eret(CPUMIPSState *env)
1979 {
1980 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1981 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1982 env->active_tc.PC, env->CP0_EPC);
1983 if (env->CP0_Status & (1 << CP0St_ERL))
1984 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1985 if (env->hflags & MIPS_HFLAG_DM)
1986 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1987 qemu_log("\n");
1988 }
1989 }
1990
1991 static void debug_post_eret(CPUMIPSState *env)
1992 {
1993 MIPSCPU *cpu = mips_env_get_cpu(env);
1994
1995 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1996 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1997 env->active_tc.PC, env->CP0_EPC);
1998 if (env->CP0_Status & (1 << CP0St_ERL))
1999 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2000 if (env->hflags & MIPS_HFLAG_DM)
2001 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2002 switch (env->hflags & MIPS_HFLAG_KSU) {
2003 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2004 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2005 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2006 default:
2007 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2008 break;
2009 }
2010 }
2011 }
2012
2013 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2014 {
2015 env->active_tc.PC = error_pc & ~(target_ulong)1;
2016 if (error_pc & 1) {
2017 env->hflags |= MIPS_HFLAG_M16;
2018 } else {
2019 env->hflags &= ~(MIPS_HFLAG_M16);
2020 }
2021 }
2022
2023 void helper_eret(CPUMIPSState *env)
2024 {
2025 debug_pre_eret(env);
2026 if (env->CP0_Status & (1 << CP0St_ERL)) {
2027 set_pc(env, env->CP0_ErrorEPC);
2028 env->CP0_Status &= ~(1 << CP0St_ERL);
2029 } else {
2030 set_pc(env, env->CP0_EPC);
2031 env->CP0_Status &= ~(1 << CP0St_EXL);
2032 }
2033 compute_hflags(env);
2034 debug_post_eret(env);
2035 env->lladdr = 1;
2036 }
2037
2038 void helper_deret(CPUMIPSState *env)
2039 {
2040 debug_pre_eret(env);
2041 set_pc(env, env->CP0_DEPC);
2042
2043 env->hflags &= MIPS_HFLAG_DM;
2044 compute_hflags(env);
2045 debug_post_eret(env);
2046 env->lladdr = 1;
2047 }
2048 #endif /* !CONFIG_USER_ONLY */
2049
2050 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2051 {
2052 if ((env->hflags & MIPS_HFLAG_CP0) ||
2053 (env->CP0_HWREna & (1 << 0)))
2054 return env->CP0_EBase & 0x3ff;
2055 else
2056 helper_raise_exception(env, EXCP_RI);
2057
2058 return 0;
2059 }
2060
2061 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2062 {
2063 if ((env->hflags & MIPS_HFLAG_CP0) ||
2064 (env->CP0_HWREna & (1 << 1)))
2065 return env->SYNCI_Step;
2066 else
2067 helper_raise_exception(env, EXCP_RI);
2068
2069 return 0;
2070 }
2071
2072 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2073 {
2074 if ((env->hflags & MIPS_HFLAG_CP0) ||
2075 (env->CP0_HWREna & (1 << 2)))
2076 return env->CP0_Count;
2077 else
2078 helper_raise_exception(env, EXCP_RI);
2079
2080 return 0;
2081 }
2082
2083 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2084 {
2085 if ((env->hflags & MIPS_HFLAG_CP0) ||
2086 (env->CP0_HWREna & (1 << 3)))
2087 return env->CCRes;
2088 else
2089 helper_raise_exception(env, EXCP_RI);
2090
2091 return 0;
2092 }
2093
2094 void helper_pmon(CPUMIPSState *env, int function)
2095 {
2096 function /= 2;
2097 switch (function) {
2098 case 2: /* TODO: char inbyte(int waitflag); */
2099 if (env->active_tc.gpr[4] == 0)
2100 env->active_tc.gpr[2] = -1;
2101 /* Fall through */
2102 case 11: /* TODO: char inbyte (void); */
2103 env->active_tc.gpr[2] = -1;
2104 break;
2105 case 3:
2106 case 12:
2107 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2108 break;
2109 case 17:
2110 break;
2111 case 158:
2112 {
2113 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2114 printf("%s", fmt);
2115 }
2116 break;
2117 }
2118 }
2119
2120 void helper_wait(CPUMIPSState *env)
2121 {
2122 CPUState *cs = CPU(mips_env_get_cpu(env));
2123
2124 cs->halted = 1;
2125 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2126 helper_raise_exception(env, EXCP_HLT);
2127 }
2128
2129 #if !defined(CONFIG_USER_ONLY)
2130
2131 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2132 target_ulong addr, int is_write,
2133 int is_user, uintptr_t retaddr);
2134
2135 #define MMUSUFFIX _mmu
2136 #define ALIGNED_ONLY
2137
2138 #define SHIFT 0
2139 #include "exec/softmmu_template.h"
2140
2141 #define SHIFT 1
2142 #include "exec/softmmu_template.h"
2143
2144 #define SHIFT 2
2145 #include "exec/softmmu_template.h"
2146
2147 #define SHIFT 3
2148 #include "exec/softmmu_template.h"
2149
2150 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2151 int is_write, int is_user, uintptr_t retaddr)
2152 {
2153 env->CP0_BadVAddr = addr;
2154 do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2155 }
2156
2157 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2158 uintptr_t retaddr)
2159 {
2160 int ret;
2161
2162 ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2163 if (ret) {
2164 MIPSCPU *cpu = MIPS_CPU(cs);
2165 CPUMIPSState *env = &cpu->env;
2166
2167 do_raise_exception_err(env, cs->exception_index,
2168 env->error_code, retaddr);
2169 }
2170 }
2171
2172 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2173 bool is_write, bool is_exec, int unused,
2174 unsigned size)
2175 {
2176 MIPSCPU *cpu = MIPS_CPU(cs);
2177 CPUMIPSState *env = &cpu->env;
2178
2179 if (is_exec) {
2180 helper_raise_exception(env, EXCP_IBE);
2181 } else {
2182 helper_raise_exception(env, EXCP_DBE);
2183 }
2184 }
2185 #endif /* !CONFIG_USER_ONLY */
2186
2187 /* Complex FPU operations which may need stack space. */
2188
2189 #define FLOAT_TWO32 make_float32(1 << 30)
2190 #define FLOAT_TWO64 make_float64(1ULL << 62)
2191 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2192 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2193
2194 /* convert MIPS rounding mode in FCR31 to IEEE library */
2195 static unsigned int ieee_rm[] = {
2196 float_round_nearest_even,
2197 float_round_to_zero,
2198 float_round_up,
2199 float_round_down
2200 };
2201
2202 static inline void restore_rounding_mode(CPUMIPSState *env)
2203 {
2204 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2205 &env->active_fpu.fp_status);
2206 }
2207
2208 static inline void restore_flush_mode(CPUMIPSState *env)
2209 {
2210 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2211 &env->active_fpu.fp_status);
2212 }
2213
2214 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2215 {
2216 target_ulong arg1 = 0;
2217
2218 switch (reg) {
2219 case 0:
2220 arg1 = (int32_t)env->active_fpu.fcr0;
2221 break;
2222 case 1:
2223 /* UFR Support - Read Status FR */
2224 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2225 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2226 arg1 = (int32_t)
2227 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2228 } else {
2229 helper_raise_exception(env, EXCP_RI);
2230 }
2231 }
2232 break;
2233 case 25:
2234 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2235 break;
2236 case 26:
2237 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2238 break;
2239 case 28:
2240 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2241 break;
2242 default:
2243 arg1 = (int32_t)env->active_fpu.fcr31;
2244 break;
2245 }
2246
2247 return arg1;
2248 }
2249
2250 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2251 {
2252 switch (fs) {
2253 case 1:
2254 /* UFR Alias - Reset Status FR */
2255 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2256 return;
2257 }
2258 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2259 env->CP0_Status &= ~(1 << CP0St_FR);
2260 compute_hflags(env);
2261 } else {
2262 helper_raise_exception(env, EXCP_RI);
2263 }
2264 break;
2265 case 4:
2266 /* UNFR Alias - Set Status FR */
2267 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2268 return;
2269 }
2270 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2271 env->CP0_Status |= (1 << CP0St_FR);
2272 compute_hflags(env);
2273 } else {
2274 helper_raise_exception(env, EXCP_RI);
2275 }
2276 break;
2277 case 25:
2278 if (arg1 & 0xffffff00)
2279 return;
2280 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2281 ((arg1 & 0x1) << 23);
2282 break;
2283 case 26:
2284 if (arg1 & 0x007c0000)
2285 return;
2286 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2287 break;
2288 case 28:
2289 if (arg1 & 0x007c0000)
2290 return;
2291 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2292 ((arg1 & 0x4) << 22);
2293 break;
2294 case 31:
2295 if (arg1 & 0x007c0000)
2296 return;
2297 env->active_fpu.fcr31 = arg1;
2298 break;
2299 default:
2300 return;
2301 }
2302 /* set rounding mode */
2303 restore_rounding_mode(env);
2304 /* set flush-to-zero mode */
2305 restore_flush_mode(env);
2306 set_float_exception_flags(0, &env->active_fpu.fp_status);
2307 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2308 do_raise_exception(env, EXCP_FPE, GETPC());
2309 }
2310
2311 static inline int ieee_ex_to_mips(int xcpt)
2312 {
2313 int ret = 0;
2314 if (xcpt) {
2315 if (xcpt & float_flag_invalid) {
2316 ret |= FP_INVALID;
2317 }
2318 if (xcpt & float_flag_overflow) {
2319 ret |= FP_OVERFLOW;
2320 }
2321 if (xcpt & float_flag_underflow) {
2322 ret |= FP_UNDERFLOW;
2323 }
2324 if (xcpt & float_flag_divbyzero) {
2325 ret |= FP_DIV0;
2326 }
2327 if (xcpt & float_flag_inexact) {
2328 ret |= FP_INEXACT;
2329 }
2330 }
2331 return ret;
2332 }
2333
2334 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2335 {
2336 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2337
2338 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2339
2340 if (tmp) {
2341 set_float_exception_flags(0, &env->active_fpu.fp_status);
2342
2343 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2344 do_raise_exception(env, EXCP_FPE, pc);
2345 } else {
2346 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2347 }
2348 }
2349 }
2350
2351 /* Float support.
2352 Single precition routines have a "s" suffix, double precision a
2353 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2354 paired single lower "pl", paired single upper "pu". */
2355
2356 /* unary operations, modifying fp status */
2357 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2358 {
2359 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2360 update_fcr31(env, GETPC());
2361 return fdt0;
2362 }
2363
2364 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2365 {
2366 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2367 update_fcr31(env, GETPC());
2368 return fst0;
2369 }
2370
2371 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2372 {
2373 uint64_t fdt2;
2374
2375 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2376 update_fcr31(env, GETPC());
2377 return fdt2;
2378 }
2379
2380 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2381 {
2382 uint64_t fdt2;
2383
2384 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2385 update_fcr31(env, GETPC());
2386 return fdt2;
2387 }
2388
2389 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2390 {
2391 uint64_t fdt2;
2392
2393 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2394 update_fcr31(env, GETPC());
2395 return fdt2;
2396 }
2397
2398 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2399 {
2400 uint64_t dt2;
2401
2402 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2403 if (get_float_exception_flags(&env->active_fpu.fp_status)
2404 & (float_flag_invalid | float_flag_overflow)) {
2405 dt2 = FP_TO_INT64_OVERFLOW;
2406 }
2407 update_fcr31(env, GETPC());
2408 return dt2;
2409 }
2410
2411 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2412 {
2413 uint64_t dt2;
2414
2415 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2416 if (get_float_exception_flags(&env->active_fpu.fp_status)
2417 & (float_flag_invalid | float_flag_overflow)) {
2418 dt2 = FP_TO_INT64_OVERFLOW;
2419 }
2420 update_fcr31(env, GETPC());
2421 return dt2;
2422 }
2423
2424 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2425 {
2426 uint32_t fst2;
2427 uint32_t fsth2;
2428
2429 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2430 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2431 update_fcr31(env, GETPC());
2432 return ((uint64_t)fsth2 << 32) | fst2;
2433 }
2434
2435 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2436 {
2437 uint32_t wt2;
2438 uint32_t wth2;
2439 int excp, excph;
2440
2441 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2442 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2443 if (excp & (float_flag_overflow | float_flag_invalid)) {
2444 wt2 = FP_TO_INT32_OVERFLOW;
2445 }
2446
2447 set_float_exception_flags(0, &env->active_fpu.fp_status);
2448 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2449 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2450 if (excph & (float_flag_overflow | float_flag_invalid)) {
2451 wth2 = FP_TO_INT32_OVERFLOW;
2452 }
2453
2454 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2455 update_fcr31(env, GETPC());
2456
2457 return ((uint64_t)wth2 << 32) | wt2;
2458 }
2459
2460 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2461 {
2462 uint32_t fst2;
2463
2464 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2465 update_fcr31(env, GETPC());
2466 return fst2;
2467 }
2468
2469 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2470 {
2471 uint32_t fst2;
2472
2473 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2474 update_fcr31(env, GETPC());
2475 return fst2;
2476 }
2477
2478 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2479 {
2480 uint32_t fst2;
2481
2482 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2483 update_fcr31(env, GETPC());
2484 return fst2;
2485 }
2486
2487 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2488 {
2489 uint32_t wt2;
2490
2491 wt2 = wt0;
2492 update_fcr31(env, GETPC());
2493 return wt2;
2494 }
2495
2496 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2497 {
2498 uint32_t wt2;
2499
2500 wt2 = wth0;
2501 update_fcr31(env, GETPC());
2502 return wt2;
2503 }
2504
2505 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2506 {
2507 uint32_t wt2;
2508
2509 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2510 update_fcr31(env, GETPC());
2511 if (get_float_exception_flags(&env->active_fpu.fp_status)
2512 & (float_flag_invalid | float_flag_overflow)) {
2513 wt2 = FP_TO_INT32_OVERFLOW;
2514 }
2515 return wt2;
2516 }
2517
2518 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2519 {
2520 uint32_t wt2;
2521
2522 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2523 if (get_float_exception_flags(&env->active_fpu.fp_status)
2524 & (float_flag_invalid | float_flag_overflow)) {
2525 wt2 = FP_TO_INT32_OVERFLOW;
2526 }
2527 update_fcr31(env, GETPC());
2528 return wt2;
2529 }
2530
2531 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2532 {
2533 uint64_t dt2;
2534
2535 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2536 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2537 restore_rounding_mode(env);
2538 if (get_float_exception_flags(&env->active_fpu.fp_status)
2539 & (float_flag_invalid | float_flag_overflow)) {
2540 dt2 = FP_TO_INT64_OVERFLOW;
2541 }
2542 update_fcr31(env, GETPC());
2543 return dt2;
2544 }
2545
2546 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2547 {
2548 uint64_t dt2;
2549
2550 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2551 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2552 restore_rounding_mode(env);
2553 if (get_float_exception_flags(&env->active_fpu.fp_status)
2554 & (float_flag_invalid | float_flag_overflow)) {
2555 dt2 = FP_TO_INT64_OVERFLOW;
2556 }
2557 update_fcr31(env, GETPC());
2558 return dt2;
2559 }
2560
2561 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2562 {
2563 uint32_t wt2;
2564
2565 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2566 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2567 restore_rounding_mode(env);
2568 if (get_float_exception_flags(&env->active_fpu.fp_status)
2569 & (float_flag_invalid | float_flag_overflow)) {
2570 wt2 = FP_TO_INT32_OVERFLOW;
2571 }
2572 update_fcr31(env, GETPC());
2573 return wt2;
2574 }
2575
2576 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2577 {
2578 uint32_t wt2;
2579
2580 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2581 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2582 restore_rounding_mode(env);
2583 if (get_float_exception_flags(&env->active_fpu.fp_status)
2584 & (float_flag_invalid | float_flag_overflow)) {
2585 wt2 = FP_TO_INT32_OVERFLOW;
2586 }
2587 update_fcr31(env, GETPC());
2588 return wt2;
2589 }
2590
2591 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2592 {
2593 uint64_t dt2;
2594
2595 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2596 if (get_float_exception_flags(&env->active_fpu.fp_status)
2597 & (float_flag_invalid | float_flag_overflow)) {
2598 dt2 = FP_TO_INT64_OVERFLOW;
2599 }
2600 update_fcr31(env, GETPC());
2601 return dt2;
2602 }
2603
2604 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2605 {
2606 uint64_t dt2;
2607
2608 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2609 if (get_float_exception_flags(&env->active_fpu.fp_status)
2610 & (float_flag_invalid | float_flag_overflow)) {
2611 dt2 = FP_TO_INT64_OVERFLOW;
2612 }
2613 update_fcr31(env, GETPC());
2614 return dt2;
2615 }
2616
2617 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2618 {
2619 uint32_t wt2;
2620
2621 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2622 if (get_float_exception_flags(&env->active_fpu.fp_status)
2623 & (float_flag_invalid | float_flag_overflow)) {
2624 wt2 = FP_TO_INT32_OVERFLOW;
2625 }
2626 update_fcr31(env, GETPC());
2627 return wt2;
2628 }
2629
2630 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2631 {
2632 uint32_t wt2;
2633
2634 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2635 if (get_float_exception_flags(&env->active_fpu.fp_status)
2636 & (float_flag_invalid | float_flag_overflow)) {
2637 wt2 = FP_TO_INT32_OVERFLOW;
2638 }
2639 update_fcr31(env, GETPC());
2640 return wt2;
2641 }
2642
2643 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2644 {
2645 uint64_t dt2;
2646
2647 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2648 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2649 restore_rounding_mode(env);
2650 if (get_float_exception_flags(&env->active_fpu.fp_status)
2651 & (float_flag_invalid | float_flag_overflow)) {
2652 dt2 = FP_TO_INT64_OVERFLOW;
2653 }
2654 update_fcr31(env, GETPC());
2655 return dt2;
2656 }
2657
2658 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2659 {
2660 uint64_t dt2;
2661
2662 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2663 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2664 restore_rounding_mode(env);
2665 if (get_float_exception_flags(&env->active_fpu.fp_status)
2666 & (float_flag_invalid | float_flag_overflow)) {
2667 dt2 = FP_TO_INT64_OVERFLOW;
2668 }
2669 update_fcr31(env, GETPC());
2670 return dt2;
2671 }
2672
2673 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2674 {
2675 uint32_t wt2;
2676
2677 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2678 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2679 restore_rounding_mode(env);
2680 if (get_float_exception_flags(&env->active_fpu.fp_status)
2681 & (float_flag_invalid | float_flag_overflow)) {
2682 wt2 = FP_TO_INT32_OVERFLOW;
2683 }
2684 update_fcr31(env, GETPC());
2685 return wt2;
2686 }
2687
2688 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2689 {
2690 uint32_t wt2;
2691
2692 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2693 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2694 restore_rounding_mode(env);
2695 if (get_float_exception_flags(&env->active_fpu.fp_status)
2696 & (float_flag_invalid | float_flag_overflow)) {
2697 wt2 = FP_TO_INT32_OVERFLOW;
2698 }
2699 update_fcr31(env, GETPC());
2700 return wt2;
2701 }
2702
2703 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2704 {
2705 uint64_t dt2;
2706
2707 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2708 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2709 restore_rounding_mode(env);
2710 if (get_float_exception_flags(&env->active_fpu.fp_status)
2711 & (float_flag_invalid | float_flag_overflow)) {
2712 dt2 = FP_TO_INT64_OVERFLOW;
2713 }
2714 update_fcr31(env, GETPC());
2715 return dt2;
2716 }
2717
2718 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2719 {
2720 uint64_t dt2;
2721
2722 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2723 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2724 restore_rounding_mode(env);
2725 if (get_float_exception_flags(&env->active_fpu.fp_status)
2726 & (float_flag_invalid | float_flag_overflow)) {
2727 dt2 = FP_TO_INT64_OVERFLOW;
2728 }
2729 update_fcr31(env, GETPC());
2730 return dt2;
2731 }
2732
2733 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2734 {
2735 uint32_t wt2;
2736
2737 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2738 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2739 restore_rounding_mode(env);
2740 if (get_float_exception_flags(&env->active_fpu.fp_status)
2741 & (float_flag_invalid | float_flag_overflow)) {
2742 wt2 = FP_TO_INT32_OVERFLOW;
2743 }
2744 update_fcr31(env, GETPC());
2745 return wt2;
2746 }
2747
2748 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2749 {
2750 uint32_t wt2;
2751
2752 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2753 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2754 restore_rounding_mode(env);
2755 if (get_float_exception_flags(&env->active_fpu.fp_status)
2756 & (float_flag_invalid | float_flag_overflow)) {
2757 wt2 = FP_TO_INT32_OVERFLOW;
2758 }
2759 update_fcr31(env, GETPC());
2760 return wt2;
2761 }
2762
2763 /* unary operations, not modifying fp status */
2764 #define FLOAT_UNOP(name) \
2765 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2766 { \
2767 return float64_ ## name(fdt0); \
2768 } \
2769 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2770 { \
2771 return float32_ ## name(fst0); \
2772 } \
2773 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2774 { \
2775 uint32_t wt0; \
2776 uint32_t wth0; \
2777 \
2778 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2779 wth0 = float32_ ## name(fdt0 >> 32); \
2780 return ((uint64_t)wth0 << 32) | wt0; \
2781 }
2782 FLOAT_UNOP(abs)
2783 FLOAT_UNOP(chs)
2784 #undef FLOAT_UNOP
2785
2786 /* MIPS specific unary operations */
2787 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2788 {
2789 uint64_t fdt2;
2790
2791 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2792 update_fcr31(env, GETPC());
2793 return fdt2;
2794 }
2795
2796 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2797 {
2798 uint32_t fst2;
2799
2800 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2801 update_fcr31(env, GETPC());
2802 return fst2;
2803 }
2804
2805 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2806 {
2807 uint64_t fdt2;
2808
2809 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2810 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2811 update_fcr31(env, GETPC());
2812 return fdt2;
2813 }
2814
2815 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2816 {
2817 uint32_t fst2;
2818
2819 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2820 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2821 update_fcr31(env, GETPC());
2822 return fst2;
2823 }
2824
2825 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2826 {
2827 uint64_t fdt2;
2828
2829 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2830 update_fcr31(env, GETPC());
2831 return fdt2;
2832 }
2833
2834 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2835 {
2836 uint32_t fst2;
2837
2838 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2839 update_fcr31(env, GETPC());
2840 return fst2;
2841 }
2842
2843 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2844 {
2845 uint32_t fst2;
2846 uint32_t fsth2;
2847
2848 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2849 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2850 update_fcr31(env, GETPC());
2851 return ((uint64_t)fsth2 << 32) | fst2;
2852 }
2853
2854 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2855 {
2856 uint64_t fdt2;
2857
2858 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2859 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2860 update_fcr31(env, GETPC());
2861 return fdt2;
2862 }
2863
2864 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2865 {
2866 uint32_t fst2;
2867
2868 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2869 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2870 update_fcr31(env, GETPC());
2871 return fst2;
2872 }
2873
2874 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2875 {
2876 uint32_t fst2;
2877 uint32_t fsth2;
2878
2879 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2880 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2881 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2882 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2883 update_fcr31(env, GETPC());
2884 return ((uint64_t)fsth2 << 32) | fst2;
2885 }
2886
2887 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2888
2889 /* binary operations */
2890 #define FLOAT_BINOP(name) \
2891 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2892 uint64_t fdt0, uint64_t fdt1) \
2893 { \
2894 uint64_t dt2; \
2895 \
2896 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2897 update_fcr31(env, GETPC()); \
2898 return dt2; \
2899 } \
2900 \
2901 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2902 uint32_t fst0, uint32_t fst1) \
2903 { \
2904 uint32_t wt2; \
2905 \
2906 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2907 update_fcr31(env, GETPC()); \
2908 return wt2; \
2909 } \
2910 \
2911 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2912 uint64_t fdt0, \
2913 uint64_t fdt1) \
2914 { \
2915 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2916 uint32_t fsth0 = fdt0 >> 32; \
2917 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2918 uint32_t fsth1 = fdt1 >> 32; \
2919 uint32_t wt2; \
2920 uint32_t wth2; \
2921 \
2922 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2923 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2924 update_fcr31(env, GETPC()); \
2925 return ((uint64_t)wth2 << 32) | wt2; \
2926 }
2927
2928 FLOAT_BINOP(add)
2929 FLOAT_BINOP(sub)
2930 FLOAT_BINOP(mul)
2931 FLOAT_BINOP(div)
2932 #undef FLOAT_BINOP
2933
2934 #define UNFUSED_FMA(prefix, a, b, c, flags) \
2935 { \
2936 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
2937 if ((flags) & float_muladd_negate_c) { \
2938 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
2939 } else { \
2940 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
2941 } \
2942 if ((flags) & float_muladd_negate_result) { \
2943 a = prefix##_chs(a); \
2944 } \
2945 }
2946
2947 /* FMA based operations */
2948 #define FLOAT_FMA(name, type) \
2949 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2950 uint64_t fdt0, uint64_t fdt1, \
2951 uint64_t fdt2) \
2952 { \
2953 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
2954 update_fcr31(env, GETPC()); \
2955 return fdt0; \
2956 } \
2957 \
2958 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2959 uint32_t fst0, uint32_t fst1, \
2960 uint32_t fst2) \
2961 { \
2962 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2963 update_fcr31(env, GETPC()); \
2964 return fst0; \
2965 } \
2966 \
2967 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2968 uint64_t fdt0, uint64_t fdt1, \
2969 uint64_t fdt2) \
2970 { \
2971 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2972 uint32_t fsth0 = fdt0 >> 32; \
2973 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2974 uint32_t fsth1 = fdt1 >> 32; \
2975 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2976 uint32_t fsth2 = fdt2 >> 32; \
2977 \
2978 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2979 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
2980 update_fcr31(env, GETPC()); \
2981 return ((uint64_t)fsth0 << 32) | fst0; \
2982 }
2983 FLOAT_FMA(madd, 0)
2984 FLOAT_FMA(msub, float_muladd_negate_c)
2985 FLOAT_FMA(nmadd, float_muladd_negate_result)
2986 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2987 #undef FLOAT_FMA
2988
2989 /* MIPS specific binary operations */
2990 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2991 {
2992 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2993 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2994 update_fcr31(env, GETPC());
2995 return fdt2;
2996 }
2997
2998 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2999 {
3000 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3001 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3002 update_fcr31(env, GETPC());
3003 return fst2;
3004 }
3005
3006 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3007 {
3008 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3009 uint32_t fsth0 = fdt0 >> 32;
3010 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3011 uint32_t fsth2 = fdt2 >> 32;
3012
3013 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3014 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3015 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3016 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3017 update_fcr31(env, GETPC());
3018 return ((uint64_t)fsth2 << 32) | fst2;
3019 }
3020
3021 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3022 {
3023 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3024 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3025 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3026 update_fcr31(env, GETPC());
3027 return fdt2;
3028 }
3029
3030 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3031 {
3032 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3033 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3034 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3035 update_fcr31(env, GETPC());
3036 return fst2;
3037 }
3038
3039 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3040 {
3041 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3042 uint32_t fsth0 = fdt0 >> 32;
3043 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3044 uint32_t fsth2 = fdt2 >> 32;
3045
3046 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3047 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3048 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3049 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3050 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3051 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3052 update_fcr31(env, GETPC());
3053 return ((uint64_t)fsth2 << 32) | fst2;
3054 }
3055
3056 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3057 {
3058 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3059 uint32_t fsth0 = fdt0 >> 32;
3060 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3061 uint32_t fsth1 = fdt1 >> 32;
3062 uint32_t fst2;
3063 uint32_t fsth2;
3064
3065 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3066 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3067 update_fcr31(env, GETPC());
3068 return ((uint64_t)fsth2 << 32) | fst2;
3069 }
3070
3071 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3072 {
3073 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3074 uint32_t fsth0 = fdt0 >> 32;
3075 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3076 uint32_t fsth1 = fdt1 >> 32;
3077 uint32_t fst2;
3078 uint32_t fsth2;
3079
3080 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3081 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3082 update_fcr31(env, GETPC());
3083 return ((uint64_t)fsth2 << 32) | fst2;
3084 }
3085
3086 /* compare operations */
3087 #define FOP_COND_D(op, cond) \
3088 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3089 uint64_t fdt1, int cc) \
3090 { \
3091 int c; \
3092 c = cond; \
3093 update_fcr31(env, GETPC()); \
3094 if (c) \
3095 SET_FP_COND(cc, env->active_fpu); \
3096 else \
3097 CLEAR_FP_COND(cc, env->active_fpu); \
3098 } \
3099 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3100 uint64_t fdt1, int cc) \
3101 { \
3102 int c; \
3103 fdt0 = float64_abs(fdt0); \
3104 fdt1 = float64_abs(fdt1); \
3105 c = cond; \
3106 update_fcr31(env, GETPC()); \
3107 if (c) \
3108 SET_FP_COND(cc, env->active_fpu); \
3109 else \
3110 CLEAR_FP_COND(cc, env->active_fpu); \
3111 }
3112
3113 /* NOTE: the comma operator will make "cond" to eval to false,
3114 * but float64_unordered_quiet() is still called. */
3115 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3116 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3117 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3118 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3119 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3120 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3121 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3122 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3123 /* NOTE: the comma operator will make "cond" to eval to false,
3124 * but float64_unordered() is still called. */
3125 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3126 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3127 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3128 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3129 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3130 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3131 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3132 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3133
3134 #define FOP_COND_S(op, cond) \
3135 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3136 uint32_t fst1, int cc) \
3137 { \
3138 int c; \
3139 c = cond; \
3140 update_fcr31(env, GETPC()); \
3141 if (c) \
3142 SET_FP_COND(cc, env->active_fpu); \
3143 else \
3144 CLEAR_FP_COND(cc, env->active_fpu); \
3145 } \
3146 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3147 uint32_t fst1, int cc) \
3148 { \
3149 int c; \
3150 fst0 = float32_abs(fst0); \
3151 fst1 = float32_abs(fst1); \
3152 c = cond; \
3153 update_fcr31(env, GETPC()); \
3154 if (c) \
3155 SET_FP_COND(cc, env->active_fpu); \
3156 else \
3157 CLEAR_FP_COND(cc, env->active_fpu); \
3158 }
3159
3160 /* NOTE: the comma operator will make "cond" to eval to false,
3161 * but float32_unordered_quiet() is still called. */
3162 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3163 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3164 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3165 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3166 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3167 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3168 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3169 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3170 /* NOTE: the comma operator will make "cond" to eval to false,
3171 * but float32_unordered() is still called. */
3172 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3173 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3174 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3175 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3176 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3177 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3178 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3179 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3180
3181 #define FOP_COND_PS(op, condl, condh) \
3182 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3183 uint64_t fdt1, int cc) \
3184 { \
3185 uint32_t fst0, fsth0, fst1, fsth1; \
3186 int ch, cl; \
3187 fst0 = fdt0 & 0XFFFFFFFF; \
3188 fsth0 = fdt0 >> 32; \
3189 fst1 = fdt1 & 0XFFFFFFFF; \
3190 fsth1 = fdt1 >> 32; \
3191 cl = condl; \
3192 ch = condh; \
3193 update_fcr31(env, GETPC()); \
3194 if (cl) \
3195 SET_FP_COND(cc, env->active_fpu); \
3196 else \
3197 CLEAR_FP_COND(cc, env->active_fpu); \