vga: improve documentation
[qemu.git] / target-mips / translate.c
1 /*
2 * MIPS32 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <stdarg.h>
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <string.h>
27 #include <inttypes.h>
28
29 #include "cpu.h"
30 #include "disas.h"
31 #include "tcg-op.h"
32 #include "qemu-common.h"
33
34 #include "helper.h"
35 #define GEN_HELPER 1
36 #include "helper.h"
37
38 //#define MIPS_DEBUG_DISAS
39 //#define MIPS_DEBUG_SIGN_EXTENSIONS
40
41 /* MIPS major opcodes */
42 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
43
44 enum {
45 /* indirect opcode tables */
46 OPC_SPECIAL = (0x00 << 26),
47 OPC_REGIMM = (0x01 << 26),
48 OPC_CP0 = (0x10 << 26),
49 OPC_CP1 = (0x11 << 26),
50 OPC_CP2 = (0x12 << 26),
51 OPC_CP3 = (0x13 << 26),
52 OPC_SPECIAL2 = (0x1C << 26),
53 OPC_SPECIAL3 = (0x1F << 26),
54 /* arithmetic with immediate */
55 OPC_ADDI = (0x08 << 26),
56 OPC_ADDIU = (0x09 << 26),
57 OPC_SLTI = (0x0A << 26),
58 OPC_SLTIU = (0x0B << 26),
59 /* logic with immediate */
60 OPC_ANDI = (0x0C << 26),
61 OPC_ORI = (0x0D << 26),
62 OPC_XORI = (0x0E << 26),
63 OPC_LUI = (0x0F << 26),
64 /* arithmetic with immediate */
65 OPC_DADDI = (0x18 << 26),
66 OPC_DADDIU = (0x19 << 26),
67 /* Jump and branches */
68 OPC_J = (0x02 << 26),
69 OPC_JAL = (0x03 << 26),
70 OPC_JALS = OPC_JAL | 0x5,
71 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
72 OPC_BEQL = (0x14 << 26),
73 OPC_BNE = (0x05 << 26),
74 OPC_BNEL = (0x15 << 26),
75 OPC_BLEZ = (0x06 << 26),
76 OPC_BLEZL = (0x16 << 26),
77 OPC_BGTZ = (0x07 << 26),
78 OPC_BGTZL = (0x17 << 26),
79 OPC_JALX = (0x1D << 26), /* MIPS 16 only */
80 OPC_JALXS = OPC_JALX | 0x5,
81 /* Load and stores */
82 OPC_LDL = (0x1A << 26),
83 OPC_LDR = (0x1B << 26),
84 OPC_LB = (0x20 << 26),
85 OPC_LH = (0x21 << 26),
86 OPC_LWL = (0x22 << 26),
87 OPC_LW = (0x23 << 26),
88 OPC_LWPC = OPC_LW | 0x5,
89 OPC_LBU = (0x24 << 26),
90 OPC_LHU = (0x25 << 26),
91 OPC_LWR = (0x26 << 26),
92 OPC_LWU = (0x27 << 26),
93 OPC_SB = (0x28 << 26),
94 OPC_SH = (0x29 << 26),
95 OPC_SWL = (0x2A << 26),
96 OPC_SW = (0x2B << 26),
97 OPC_SDL = (0x2C << 26),
98 OPC_SDR = (0x2D << 26),
99 OPC_SWR = (0x2E << 26),
100 OPC_LL = (0x30 << 26),
101 OPC_LLD = (0x34 << 26),
102 OPC_LD = (0x37 << 26),
103 OPC_LDPC = OPC_LD | 0x5,
104 OPC_SC = (0x38 << 26),
105 OPC_SCD = (0x3C << 26),
106 OPC_SD = (0x3F << 26),
107 /* Floating point load/store */
108 OPC_LWC1 = (0x31 << 26),
109 OPC_LWC2 = (0x32 << 26),
110 OPC_LDC1 = (0x35 << 26),
111 OPC_LDC2 = (0x36 << 26),
112 OPC_SWC1 = (0x39 << 26),
113 OPC_SWC2 = (0x3A << 26),
114 OPC_SDC1 = (0x3D << 26),
115 OPC_SDC2 = (0x3E << 26),
116 /* MDMX ASE specific */
117 OPC_MDMX = (0x1E << 26),
118 /* Cache and prefetch */
119 OPC_CACHE = (0x2F << 26),
120 OPC_PREF = (0x33 << 26),
121 /* Reserved major opcode */
122 OPC_MAJOR3B_RESERVED = (0x3B << 26),
123 };
124
125 /* MIPS special opcodes */
126 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
127
128 enum {
129 /* Shifts */
130 OPC_SLL = 0x00 | OPC_SPECIAL,
131 /* NOP is SLL r0, r0, 0 */
132 /* SSNOP is SLL r0, r0, 1 */
133 /* EHB is SLL r0, r0, 3 */
134 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
135 OPC_ROTR = OPC_SRL | (1 << 21),
136 OPC_SRA = 0x03 | OPC_SPECIAL,
137 OPC_SLLV = 0x04 | OPC_SPECIAL,
138 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
139 OPC_ROTRV = OPC_SRLV | (1 << 6),
140 OPC_SRAV = 0x07 | OPC_SPECIAL,
141 OPC_DSLLV = 0x14 | OPC_SPECIAL,
142 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
143 OPC_DROTRV = OPC_DSRLV | (1 << 6),
144 OPC_DSRAV = 0x17 | OPC_SPECIAL,
145 OPC_DSLL = 0x38 | OPC_SPECIAL,
146 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
147 OPC_DROTR = OPC_DSRL | (1 << 21),
148 OPC_DSRA = 0x3B | OPC_SPECIAL,
149 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
150 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
151 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
152 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
153 /* Multiplication / division */
154 OPC_MULT = 0x18 | OPC_SPECIAL,
155 OPC_MULTU = 0x19 | OPC_SPECIAL,
156 OPC_DIV = 0x1A | OPC_SPECIAL,
157 OPC_DIVU = 0x1B | OPC_SPECIAL,
158 OPC_DMULT = 0x1C | OPC_SPECIAL,
159 OPC_DMULTU = 0x1D | OPC_SPECIAL,
160 OPC_DDIV = 0x1E | OPC_SPECIAL,
161 OPC_DDIVU = 0x1F | OPC_SPECIAL,
162 /* 2 registers arithmetic / logic */
163 OPC_ADD = 0x20 | OPC_SPECIAL,
164 OPC_ADDU = 0x21 | OPC_SPECIAL,
165 OPC_SUB = 0x22 | OPC_SPECIAL,
166 OPC_SUBU = 0x23 | OPC_SPECIAL,
167 OPC_AND = 0x24 | OPC_SPECIAL,
168 OPC_OR = 0x25 | OPC_SPECIAL,
169 OPC_XOR = 0x26 | OPC_SPECIAL,
170 OPC_NOR = 0x27 | OPC_SPECIAL,
171 OPC_SLT = 0x2A | OPC_SPECIAL,
172 OPC_SLTU = 0x2B | OPC_SPECIAL,
173 OPC_DADD = 0x2C | OPC_SPECIAL,
174 OPC_DADDU = 0x2D | OPC_SPECIAL,
175 OPC_DSUB = 0x2E | OPC_SPECIAL,
176 OPC_DSUBU = 0x2F | OPC_SPECIAL,
177 /* Jumps */
178 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
179 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
180 OPC_JALRC = OPC_JALR | (0x5 << 6),
181 OPC_JALRS = 0x10 | OPC_SPECIAL | (0x5 << 6),
182 /* Traps */
183 OPC_TGE = 0x30 | OPC_SPECIAL,
184 OPC_TGEU = 0x31 | OPC_SPECIAL,
185 OPC_TLT = 0x32 | OPC_SPECIAL,
186 OPC_TLTU = 0x33 | OPC_SPECIAL,
187 OPC_TEQ = 0x34 | OPC_SPECIAL,
188 OPC_TNE = 0x36 | OPC_SPECIAL,
189 /* HI / LO registers load & stores */
190 OPC_MFHI = 0x10 | OPC_SPECIAL,
191 OPC_MTHI = 0x11 | OPC_SPECIAL,
192 OPC_MFLO = 0x12 | OPC_SPECIAL,
193 OPC_MTLO = 0x13 | OPC_SPECIAL,
194 /* Conditional moves */
195 OPC_MOVZ = 0x0A | OPC_SPECIAL,
196 OPC_MOVN = 0x0B | OPC_SPECIAL,
197
198 OPC_MOVCI = 0x01 | OPC_SPECIAL,
199
200 /* Special */
201 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */
202 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
203 OPC_BREAK = 0x0D | OPC_SPECIAL,
204 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
205 OPC_SYNC = 0x0F | OPC_SPECIAL,
206
207 OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
208 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
209 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
210 OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
211 OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
212 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
213 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
214 };
215
216 /* Multiplication variants of the vr54xx. */
217 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
218
219 enum {
220 OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
221 OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
222 OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
223 OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
224 OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
225 OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
226 OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
227 OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
228 OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
229 OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
230 OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
231 OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
232 OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
233 OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
234 };
235
236 /* REGIMM (rt field) opcodes */
237 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
238
239 enum {
240 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
241 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
242 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
243 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
244 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
245 OPC_BLTZALS = OPC_BLTZAL | 0x5, /* microMIPS */
246 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
247 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
248 OPC_BGEZALS = OPC_BGEZAL | 0x5, /* microMIPS */
249 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
250 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
251 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
252 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
253 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
254 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
255 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
256 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
257 };
258
259 /* Special2 opcodes */
260 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
261
262 enum {
263 /* Multiply & xxx operations */
264 OPC_MADD = 0x00 | OPC_SPECIAL2,
265 OPC_MADDU = 0x01 | OPC_SPECIAL2,
266 OPC_MUL = 0x02 | OPC_SPECIAL2,
267 OPC_MSUB = 0x04 | OPC_SPECIAL2,
268 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
269 /* Loongson 2F */
270 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
271 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
272 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
273 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
274 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
275 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
276 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
277 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
278 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
279 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
280 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
281 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
282 /* Misc */
283 OPC_CLZ = 0x20 | OPC_SPECIAL2,
284 OPC_CLO = 0x21 | OPC_SPECIAL2,
285 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
286 OPC_DCLO = 0x25 | OPC_SPECIAL2,
287 /* Special */
288 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
289 };
290
291 /* Special3 opcodes */
292 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
293
294 enum {
295 OPC_EXT = 0x00 | OPC_SPECIAL3,
296 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
297 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
298 OPC_DEXT = 0x03 | OPC_SPECIAL3,
299 OPC_INS = 0x04 | OPC_SPECIAL3,
300 OPC_DINSM = 0x05 | OPC_SPECIAL3,
301 OPC_DINSU = 0x06 | OPC_SPECIAL3,
302 OPC_DINS = 0x07 | OPC_SPECIAL3,
303 OPC_FORK = 0x08 | OPC_SPECIAL3,
304 OPC_YIELD = 0x09 | OPC_SPECIAL3,
305 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
306 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
307 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
308
309 /* Loongson 2E */
310 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
311 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
312 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
313 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
314 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
315 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
316 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
317 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
318 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
319 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
320 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
321 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
322 };
323
324 /* BSHFL opcodes */
325 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
326
327 enum {
328 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
329 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
330 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
331 };
332
333 /* DBSHFL opcodes */
334 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
335
336 enum {
337 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
338 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
339 };
340
341 /* Coprocessor 0 (rs field) */
342 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
343
344 enum {
345 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
346 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
347 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
348 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
349 OPC_MFTR = (0x08 << 21) | OPC_CP0,
350 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
351 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
352 OPC_MTTR = (0x0C << 21) | OPC_CP0,
353 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
354 OPC_C0 = (0x10 << 21) | OPC_CP0,
355 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
356 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
357 };
358
359 /* MFMC0 opcodes */
360 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
361
362 enum {
363 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
364 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
365 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
366 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
367 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
368 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
369 };
370
371 /* Coprocessor 0 (with rs == C0) */
372 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
373
374 enum {
375 OPC_TLBR = 0x01 | OPC_C0,
376 OPC_TLBWI = 0x02 | OPC_C0,
377 OPC_TLBWR = 0x06 | OPC_C0,
378 OPC_TLBP = 0x08 | OPC_C0,
379 OPC_RFE = 0x10 | OPC_C0,
380 OPC_ERET = 0x18 | OPC_C0,
381 OPC_DERET = 0x1F | OPC_C0,
382 OPC_WAIT = 0x20 | OPC_C0,
383 };
384
385 /* Coprocessor 1 (rs field) */
386 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
387
388 /* Values for the fmt field in FP instructions */
389 enum {
390 /* 0 - 15 are reserved */
391 FMT_S = 16, /* single fp */
392 FMT_D = 17, /* double fp */
393 FMT_E = 18, /* extended fp */
394 FMT_Q = 19, /* quad fp */
395 FMT_W = 20, /* 32-bit fixed */
396 FMT_L = 21, /* 64-bit fixed */
397 FMT_PS = 22, /* paired single fp */
398 /* 23 - 31 are reserved */
399 };
400
401 enum {
402 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
403 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
404 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
405 OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
406 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
407 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
408 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
409 OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
410 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
411 OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
412 OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
413 OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
414 OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
415 OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
416 OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
417 OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
418 OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
419 OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
420 };
421
422 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
423 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
424
425 enum {
426 OPC_BC1F = (0x00 << 16) | OPC_BC1,
427 OPC_BC1T = (0x01 << 16) | OPC_BC1,
428 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
429 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
430 };
431
432 enum {
433 OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
434 OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
435 };
436
437 enum {
438 OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
439 OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
440 };
441
442 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
443
444 enum {
445 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
446 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
447 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
448 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
449 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
450 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
451 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
452 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
453 OPC_BC2 = (0x08 << 21) | OPC_CP2,
454 };
455
456 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
457
458 enum {
459 OPC_LWXC1 = 0x00 | OPC_CP3,
460 OPC_LDXC1 = 0x01 | OPC_CP3,
461 OPC_LUXC1 = 0x05 | OPC_CP3,
462 OPC_SWXC1 = 0x08 | OPC_CP3,
463 OPC_SDXC1 = 0x09 | OPC_CP3,
464 OPC_SUXC1 = 0x0D | OPC_CP3,
465 OPC_PREFX = 0x0F | OPC_CP3,
466 OPC_ALNV_PS = 0x1E | OPC_CP3,
467 OPC_MADD_S = 0x20 | OPC_CP3,
468 OPC_MADD_D = 0x21 | OPC_CP3,
469 OPC_MADD_PS = 0x26 | OPC_CP3,
470 OPC_MSUB_S = 0x28 | OPC_CP3,
471 OPC_MSUB_D = 0x29 | OPC_CP3,
472 OPC_MSUB_PS = 0x2E | OPC_CP3,
473 OPC_NMADD_S = 0x30 | OPC_CP3,
474 OPC_NMADD_D = 0x31 | OPC_CP3,
475 OPC_NMADD_PS= 0x36 | OPC_CP3,
476 OPC_NMSUB_S = 0x38 | OPC_CP3,
477 OPC_NMSUB_D = 0x39 | OPC_CP3,
478 OPC_NMSUB_PS= 0x3E | OPC_CP3,
479 };
480
481 /* global register indices */
482 static TCGv_ptr cpu_env;
483 static TCGv cpu_gpr[32], cpu_PC;
484 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
485 static TCGv cpu_dspctrl, btarget, bcond;
486 static TCGv_i32 hflags;
487 static TCGv_i32 fpu_fcr0, fpu_fcr31;
488
489 static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
490
491 #include "gen-icount.h"
492
493 #define gen_helper_0i(name, arg) do { \
494 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
495 gen_helper_##name(helper_tmp); \
496 tcg_temp_free_i32(helper_tmp); \
497 } while(0)
498
499 #define gen_helper_1i(name, arg1, arg2) do { \
500 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
501 gen_helper_##name(arg1, helper_tmp); \
502 tcg_temp_free_i32(helper_tmp); \
503 } while(0)
504
505 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
506 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
507 gen_helper_##name(arg1, arg2, helper_tmp); \
508 tcg_temp_free_i32(helper_tmp); \
509 } while(0)
510
511 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
512 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
513 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
514 tcg_temp_free_i32(helper_tmp); \
515 } while(0)
516
517 typedef struct DisasContext {
518 struct TranslationBlock *tb;
519 target_ulong pc, saved_pc;
520 uint32_t opcode;
521 int singlestep_enabled;
522 /* Routine used to access memory */
523 int mem_idx;
524 uint32_t hflags, saved_hflags;
525 int bstate;
526 target_ulong btarget;
527 } DisasContext;
528
529 enum {
530 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
531 * exception condition */
532 BS_STOP = 1, /* We want to stop translation for any reason */
533 BS_BRANCH = 2, /* We reached a branch condition */
534 BS_EXCP = 3, /* We reached an exception condition */
535 };
536
537 static const char *regnames[] =
538 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
539 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
540 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
541 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
542
543 static const char *regnames_HI[] =
544 { "HI0", "HI1", "HI2", "HI3", };
545
546 static const char *regnames_LO[] =
547 { "LO0", "LO1", "LO2", "LO3", };
548
549 static const char *regnames_ACX[] =
550 { "ACX0", "ACX1", "ACX2", "ACX3", };
551
552 static const char *fregnames[] =
553 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
554 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
555 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
556 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
557
558 #ifdef MIPS_DEBUG_DISAS
559 #define MIPS_DEBUG(fmt, ...) \
560 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
561 TARGET_FMT_lx ": %08x " fmt "\n", \
562 ctx->pc, ctx->opcode , ## __VA_ARGS__)
563 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
564 #else
565 #define MIPS_DEBUG(fmt, ...) do { } while(0)
566 #define LOG_DISAS(...) do { } while (0)
567 #endif
568
569 #define MIPS_INVAL(op) \
570 do { \
571 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
572 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
573 } while (0)
574
575 /* General purpose registers moves. */
576 static inline void gen_load_gpr (TCGv t, int reg)
577 {
578 if (reg == 0)
579 tcg_gen_movi_tl(t, 0);
580 else
581 tcg_gen_mov_tl(t, cpu_gpr[reg]);
582 }
583
584 static inline void gen_store_gpr (TCGv t, int reg)
585 {
586 if (reg != 0)
587 tcg_gen_mov_tl(cpu_gpr[reg], t);
588 }
589
590 /* Moves to/from ACX register. */
591 static inline void gen_load_ACX (TCGv t, int reg)
592 {
593 tcg_gen_mov_tl(t, cpu_ACX[reg]);
594 }
595
596 static inline void gen_store_ACX (TCGv t, int reg)
597 {
598 tcg_gen_mov_tl(cpu_ACX[reg], t);
599 }
600
601 /* Moves to/from shadow registers. */
602 static inline void gen_load_srsgpr (int from, int to)
603 {
604 TCGv t0 = tcg_temp_new();
605
606 if (from == 0)
607 tcg_gen_movi_tl(t0, 0);
608 else {
609 TCGv_i32 t2 = tcg_temp_new_i32();
610 TCGv_ptr addr = tcg_temp_new_ptr();
611
612 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
613 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
614 tcg_gen_andi_i32(t2, t2, 0xf);
615 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
616 tcg_gen_ext_i32_ptr(addr, t2);
617 tcg_gen_add_ptr(addr, cpu_env, addr);
618
619 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
620 tcg_temp_free_ptr(addr);
621 tcg_temp_free_i32(t2);
622 }
623 gen_store_gpr(t0, to);
624 tcg_temp_free(t0);
625 }
626
627 static inline void gen_store_srsgpr (int from, int to)
628 {
629 if (to != 0) {
630 TCGv t0 = tcg_temp_new();
631 TCGv_i32 t2 = tcg_temp_new_i32();
632 TCGv_ptr addr = tcg_temp_new_ptr();
633
634 gen_load_gpr(t0, from);
635 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
636 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
637 tcg_gen_andi_i32(t2, t2, 0xf);
638 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
639 tcg_gen_ext_i32_ptr(addr, t2);
640 tcg_gen_add_ptr(addr, cpu_env, addr);
641
642 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
643 tcg_temp_free_ptr(addr);
644 tcg_temp_free_i32(t2);
645 tcg_temp_free(t0);
646 }
647 }
648
649 /* Floating point register moves. */
650 static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
651 {
652 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
653 }
654
655 static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
656 {
657 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
658 }
659
660 static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
661 {
662 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
663 }
664
665 static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
666 {
667 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
668 }
669
670 static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
671 {
672 if (ctx->hflags & MIPS_HFLAG_F64) {
673 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
674 } else {
675 TCGv_i32 t0 = tcg_temp_new_i32();
676 TCGv_i32 t1 = tcg_temp_new_i32();
677 gen_load_fpr32(t0, reg & ~1);
678 gen_load_fpr32(t1, reg | 1);
679 tcg_gen_concat_i32_i64(t, t0, t1);
680 tcg_temp_free_i32(t0);
681 tcg_temp_free_i32(t1);
682 }
683 }
684
685 static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
686 {
687 if (ctx->hflags & MIPS_HFLAG_F64) {
688 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
689 } else {
690 TCGv_i64 t0 = tcg_temp_new_i64();
691 TCGv_i32 t1 = tcg_temp_new_i32();
692 tcg_gen_trunc_i64_i32(t1, t);
693 gen_store_fpr32(t1, reg & ~1);
694 tcg_gen_shri_i64(t0, t, 32);
695 tcg_gen_trunc_i64_i32(t1, t0);
696 gen_store_fpr32(t1, reg | 1);
697 tcg_temp_free_i32(t1);
698 tcg_temp_free_i64(t0);
699 }
700 }
701
702 static inline int get_fp_bit (int cc)
703 {
704 if (cc)
705 return 24 + cc;
706 else
707 return 23;
708 }
709
710 /* Tests */
711 static inline void gen_save_pc(target_ulong pc)
712 {
713 tcg_gen_movi_tl(cpu_PC, pc);
714 }
715
716 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
717 {
718 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
719 if (do_save_pc && ctx->pc != ctx->saved_pc) {
720 gen_save_pc(ctx->pc);
721 ctx->saved_pc = ctx->pc;
722 }
723 if (ctx->hflags != ctx->saved_hflags) {
724 tcg_gen_movi_i32(hflags, ctx->hflags);
725 ctx->saved_hflags = ctx->hflags;
726 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
727 case MIPS_HFLAG_BR:
728 break;
729 case MIPS_HFLAG_BC:
730 case MIPS_HFLAG_BL:
731 case MIPS_HFLAG_B:
732 tcg_gen_movi_tl(btarget, ctx->btarget);
733 break;
734 }
735 }
736 }
737
738 static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
739 {
740 ctx->saved_hflags = ctx->hflags;
741 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
742 case MIPS_HFLAG_BR:
743 break;
744 case MIPS_HFLAG_BC:
745 case MIPS_HFLAG_BL:
746 case MIPS_HFLAG_B:
747 ctx->btarget = env->btarget;
748 break;
749 }
750 }
751
752 static inline void
753 generate_exception_err (DisasContext *ctx, int excp, int err)
754 {
755 TCGv_i32 texcp = tcg_const_i32(excp);
756 TCGv_i32 terr = tcg_const_i32(err);
757 save_cpu_state(ctx, 1);
758 gen_helper_raise_exception_err(texcp, terr);
759 tcg_temp_free_i32(terr);
760 tcg_temp_free_i32(texcp);
761 }
762
763 static inline void
764 generate_exception (DisasContext *ctx, int excp)
765 {
766 save_cpu_state(ctx, 1);
767 gen_helper_0i(raise_exception, excp);
768 }
769
770 /* Addresses computation */
771 static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
772 {
773 tcg_gen_add_tl(ret, arg0, arg1);
774
775 #if defined(TARGET_MIPS64)
776 /* For compatibility with 32-bit code, data reference in user mode
777 with Status_UX = 0 should be casted to 32-bit and sign extended.
778 See the MIPS64 PRA manual, section 4.10. */
779 if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
780 !(ctx->hflags & MIPS_HFLAG_UX)) {
781 tcg_gen_ext32s_i64(ret, ret);
782 }
783 #endif
784 }
785
786 static inline void check_cp0_enabled(DisasContext *ctx)
787 {
788 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
789 generate_exception_err(ctx, EXCP_CpU, 0);
790 }
791
792 static inline void check_cp1_enabled(DisasContext *ctx)
793 {
794 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
795 generate_exception_err(ctx, EXCP_CpU, 1);
796 }
797
798 /* Verify that the processor is running with COP1X instructions enabled.
799 This is associated with the nabla symbol in the MIPS32 and MIPS64
800 opcode tables. */
801
802 static inline void check_cop1x(DisasContext *ctx)
803 {
804 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
805 generate_exception(ctx, EXCP_RI);
806 }
807
808 /* Verify that the processor is running with 64-bit floating-point
809 operations enabled. */
810
811 static inline void check_cp1_64bitmode(DisasContext *ctx)
812 {
813 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
814 generate_exception(ctx, EXCP_RI);
815 }
816
817 /*
818 * Verify if floating point register is valid; an operation is not defined
819 * if bit 0 of any register specification is set and the FR bit in the
820 * Status register equals zero, since the register numbers specify an
821 * even-odd pair of adjacent coprocessor general registers. When the FR bit
822 * in the Status register equals one, both even and odd register numbers
823 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
824 *
825 * Multiple 64 bit wide registers can be checked by calling
826 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
827 */
828 static inline void check_cp1_registers(DisasContext *ctx, int regs)
829 {
830 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
831 generate_exception(ctx, EXCP_RI);
832 }
833
834 /* This code generates a "reserved instruction" exception if the
835 CPU does not support the instruction set corresponding to flags. */
836 static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
837 {
838 if (unlikely(!(env->insn_flags & flags)))
839 generate_exception(ctx, EXCP_RI);
840 }
841
842 /* This code generates a "reserved instruction" exception if 64-bit
843 instructions are not enabled. */
844 static inline void check_mips_64(DisasContext *ctx)
845 {
846 if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
847 generate_exception(ctx, EXCP_RI);
848 }
849
850 /* Define small wrappers for gen_load_fpr* so that we have a uniform
851 calling interface for 32 and 64-bit FPRs. No sense in changing
852 all callers for gen_load_fpr32 when we need the CTX parameter for
853 this one use. */
854 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y)
855 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
856 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
857 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
858 int ft, int fs, int cc) \
859 { \
860 TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
861 TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
862 switch (ifmt) { \
863 case FMT_PS: \
864 check_cp1_64bitmode(ctx); \
865 break; \
866 case FMT_D: \
867 if (abs) { \
868 check_cop1x(ctx); \
869 } \
870 check_cp1_registers(ctx, fs | ft); \
871 break; \
872 case FMT_S: \
873 if (abs) { \
874 check_cop1x(ctx); \
875 } \
876 break; \
877 } \
878 gen_ldcmp_fpr##bits (ctx, fp0, fs); \
879 gen_ldcmp_fpr##bits (ctx, fp1, ft); \
880 switch (n) { \
881 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
882 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
883 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
884 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
885 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
886 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
887 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
888 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
889 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
890 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
891 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
892 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
893 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
894 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
895 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
896 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
897 default: abort(); \
898 } \
899 tcg_temp_free_i##bits (fp0); \
900 tcg_temp_free_i##bits (fp1); \
901 }
902
903 FOP_CONDS(, 0, d, FMT_D, 64)
904 FOP_CONDS(abs, 1, d, FMT_D, 64)
905 FOP_CONDS(, 0, s, FMT_S, 32)
906 FOP_CONDS(abs, 1, s, FMT_S, 32)
907 FOP_CONDS(, 0, ps, FMT_PS, 64)
908 FOP_CONDS(abs, 1, ps, FMT_PS, 64)
909 #undef FOP_CONDS
910 #undef gen_ldcmp_fpr32
911 #undef gen_ldcmp_fpr64
912
913 /* load/store instructions. */
914 #define OP_LD(insn,fname) \
915 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
916 { \
917 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
918 }
919 OP_LD(lb,ld8s);
920 OP_LD(lbu,ld8u);
921 OP_LD(lh,ld16s);
922 OP_LD(lhu,ld16u);
923 OP_LD(lw,ld32s);
924 #if defined(TARGET_MIPS64)
925 OP_LD(lwu,ld32u);
926 OP_LD(ld,ld64);
927 #endif
928 #undef OP_LD
929
930 #define OP_ST(insn,fname) \
931 static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
932 { \
933 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
934 }
935 OP_ST(sb,st8);
936 OP_ST(sh,st16);
937 OP_ST(sw,st32);
938 #if defined(TARGET_MIPS64)
939 OP_ST(sd,st64);
940 #endif
941 #undef OP_ST
942
943 #ifdef CONFIG_USER_ONLY
944 #define OP_LD_ATOMIC(insn,fname) \
945 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
946 { \
947 TCGv t0 = tcg_temp_new(); \
948 tcg_gen_mov_tl(t0, arg1); \
949 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
950 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
951 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
952 tcg_temp_free(t0); \
953 }
954 #else
955 #define OP_LD_ATOMIC(insn,fname) \
956 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
957 { \
958 gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
959 }
960 #endif
961 OP_LD_ATOMIC(ll,ld32s);
962 #if defined(TARGET_MIPS64)
963 OP_LD_ATOMIC(lld,ld64);
964 #endif
965 #undef OP_LD_ATOMIC
966
967 #ifdef CONFIG_USER_ONLY
968 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
969 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
970 { \
971 TCGv t0 = tcg_temp_new(); \
972 int l1 = gen_new_label(); \
973 int l2 = gen_new_label(); \
974 \
975 tcg_gen_andi_tl(t0, arg2, almask); \
976 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
977 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
978 generate_exception(ctx, EXCP_AdES); \
979 gen_set_label(l1); \
980 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
981 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
982 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
983 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
984 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
985 gen_helper_0i(raise_exception, EXCP_SC); \
986 gen_set_label(l2); \
987 tcg_gen_movi_tl(t0, 0); \
988 gen_store_gpr(t0, rt); \
989 tcg_temp_free(t0); \
990 }
991 #else
992 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
993 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
994 { \
995 TCGv t0 = tcg_temp_new(); \
996 gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
997 gen_store_gpr(t0, rt); \
998 tcg_temp_free(t0); \
999 }
1000 #endif
1001 OP_ST_ATOMIC(sc,st32,ld32s,0x3);
1002 #if defined(TARGET_MIPS64)
1003 OP_ST_ATOMIC(scd,st64,ld64,0x7);
1004 #endif
1005 #undef OP_ST_ATOMIC
1006
1007 static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
1008 int base, int16_t offset)
1009 {
1010 if (base == 0) {
1011 tcg_gen_movi_tl(addr, offset);
1012 } else if (offset == 0) {
1013 gen_load_gpr(addr, base);
1014 } else {
1015 tcg_gen_movi_tl(addr, offset);
1016 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
1017 }
1018 }
1019
1020 static target_ulong pc_relative_pc (DisasContext *ctx)
1021 {
1022 target_ulong pc = ctx->pc;
1023
1024 if (ctx->hflags & MIPS_HFLAG_BMASK) {
1025 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
1026
1027 pc -= branch_bytes;
1028 }
1029
1030 pc &= ~(target_ulong)3;
1031 return pc;
1032 }
1033
1034 /* Load */
1035 static void gen_ld (CPUState *env, DisasContext *ctx, uint32_t opc,
1036 int rt, int base, int16_t offset)
1037 {
1038 const char *opn = "ld";
1039 TCGv t0, t1;
1040
1041 if (rt == 0 && env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
1042 /* Loongson CPU uses a load to zero register for prefetch.
1043 We emulate it as a NOP. On other CPU we must perform the
1044 actual memory access. */
1045 MIPS_DEBUG("NOP");
1046 return;
1047 }
1048
1049 t0 = tcg_temp_new();
1050 t1 = tcg_temp_new();
1051 gen_base_offset_addr(ctx, t0, base, offset);
1052
1053 switch (opc) {
1054 #if defined(TARGET_MIPS64)
1055 case OPC_LWU:
1056 save_cpu_state(ctx, 0);
1057 op_ld_lwu(t0, t0, ctx);
1058 gen_store_gpr(t0, rt);
1059 opn = "lwu";
1060 break;
1061 case OPC_LD:
1062 save_cpu_state(ctx, 0);
1063 op_ld_ld(t0, t0, ctx);
1064 gen_store_gpr(t0, rt);
1065 opn = "ld";
1066 break;
1067 case OPC_LLD:
1068 save_cpu_state(ctx, 1);
1069 op_ld_lld(t0, t0, ctx);
1070 gen_store_gpr(t0, rt);
1071 opn = "lld";
1072 break;
1073 case OPC_LDL:
1074 save_cpu_state(ctx, 1);
1075 gen_load_gpr(t1, rt);
1076 gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
1077 gen_store_gpr(t1, rt);
1078 opn = "ldl";
1079 break;
1080 case OPC_LDR:
1081 save_cpu_state(ctx, 1);
1082 gen_load_gpr(t1, rt);
1083 gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
1084 gen_store_gpr(t1, rt);
1085 opn = "ldr";
1086 break;
1087 case OPC_LDPC:
1088 save_cpu_state(ctx, 0);
1089 tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
1090 gen_op_addr_add(ctx, t0, t0, t1);
1091 op_ld_ld(t0, t0, ctx);
1092 gen_store_gpr(t0, rt);
1093 opn = "ldpc";
1094 break;
1095 #endif
1096 case OPC_LWPC:
1097 save_cpu_state(ctx, 0);
1098 tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
1099 gen_op_addr_add(ctx, t0, t0, t1);
1100 op_ld_lw(t0, t0, ctx);
1101 gen_store_gpr(t0, rt);
1102 opn = "lwpc";
1103 break;
1104 case OPC_LW:
1105 save_cpu_state(ctx, 0);
1106 op_ld_lw(t0, t0, ctx);
1107 gen_store_gpr(t0, rt);
1108 opn = "lw";
1109 break;
1110 case OPC_LH:
1111 save_cpu_state(ctx, 0);
1112 op_ld_lh(t0, t0, ctx);
1113 gen_store_gpr(t0, rt);
1114 opn = "lh";
1115 break;
1116 case OPC_LHU:
1117 save_cpu_state(ctx, 0);
1118 op_ld_lhu(t0, t0, ctx);
1119 gen_store_gpr(t0, rt);
1120 opn = "lhu";
1121 break;
1122 case OPC_LB:
1123 save_cpu_state(ctx, 0);
1124 op_ld_lb(t0, t0, ctx);
1125 gen_store_gpr(t0, rt);
1126 opn = "lb";
1127 break;
1128 case OPC_LBU:
1129 save_cpu_state(ctx, 0);
1130 op_ld_lbu(t0, t0, ctx);
1131 gen_store_gpr(t0, rt);
1132 opn = "lbu";
1133 break;
1134 case OPC_LWL:
1135 save_cpu_state(ctx, 1);
1136 gen_load_gpr(t1, rt);
1137 gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
1138 gen_store_gpr(t1, rt);
1139 opn = "lwl";
1140 break;
1141 case OPC_LWR:
1142 save_cpu_state(ctx, 1);
1143 gen_load_gpr(t1, rt);
1144 gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
1145 gen_store_gpr(t1, rt);
1146 opn = "lwr";
1147 break;
1148 case OPC_LL:
1149 save_cpu_state(ctx, 1);
1150 op_ld_ll(t0, t0, ctx);
1151 gen_store_gpr(t0, rt);
1152 opn = "ll";
1153 break;
1154 }
1155 (void)opn; /* avoid a compiler warning */
1156 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1157 tcg_temp_free(t0);
1158 tcg_temp_free(t1);
1159 }
1160
1161 /* Store */
1162 static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
1163 int base, int16_t offset)
1164 {
1165 const char *opn = "st";
1166 TCGv t0 = tcg_temp_new();
1167 TCGv t1 = tcg_temp_new();
1168
1169 gen_base_offset_addr(ctx, t0, base, offset);
1170 gen_load_gpr(t1, rt);
1171 switch (opc) {
1172 #if defined(TARGET_MIPS64)
1173 case OPC_SD:
1174 save_cpu_state(ctx, 0);
1175 op_st_sd(t1, t0, ctx);
1176 opn = "sd";
1177 break;
1178 case OPC_SDL:
1179 save_cpu_state(ctx, 1);
1180 gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
1181 opn = "sdl";
1182 break;
1183 case OPC_SDR:
1184 save_cpu_state(ctx, 1);
1185 gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
1186 opn = "sdr";
1187 break;
1188 #endif
1189 case OPC_SW:
1190 save_cpu_state(ctx, 0);
1191 op_st_sw(t1, t0, ctx);
1192 opn = "sw";
1193 break;
1194 case OPC_SH:
1195 save_cpu_state(ctx, 0);
1196 op_st_sh(t1, t0, ctx);
1197 opn = "sh";
1198 break;
1199 case OPC_SB:
1200 save_cpu_state(ctx, 0);
1201 op_st_sb(t1, t0, ctx);
1202 opn = "sb";
1203 break;
1204 case OPC_SWL:
1205 save_cpu_state(ctx, 1);
1206 gen_helper_2i(swl, t1, t0, ctx->mem_idx);
1207 opn = "swl";
1208 break;
1209 case OPC_SWR:
1210 save_cpu_state(ctx, 1);
1211 gen_helper_2i(swr, t1, t0, ctx->mem_idx);
1212 opn = "swr";
1213 break;
1214 }
1215 (void)opn; /* avoid a compiler warning */
1216 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1217 tcg_temp_free(t0);
1218 tcg_temp_free(t1);
1219 }
1220
1221
1222 /* Store conditional */
1223 static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
1224 int base, int16_t offset)
1225 {
1226 const char *opn = "st_cond";
1227 TCGv t0, t1;
1228
1229 t0 = tcg_temp_local_new();
1230
1231 gen_base_offset_addr(ctx, t0, base, offset);
1232 /* Don't do NOP if destination is zero: we must perform the actual
1233 memory access. */
1234
1235 t1 = tcg_temp_local_new();
1236 gen_load_gpr(t1, rt);
1237 switch (opc) {
1238 #if defined(TARGET_MIPS64)
1239 case OPC_SCD:
1240 save_cpu_state(ctx, 1);
1241 op_st_scd(t1, t0, rt, ctx);
1242 opn = "scd";
1243 break;
1244 #endif
1245 case OPC_SC:
1246 save_cpu_state(ctx, 1);
1247 op_st_sc(t1, t0, rt, ctx);
1248 opn = "sc";
1249 break;
1250 }
1251 (void)opn; /* avoid a compiler warning */
1252 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1253 tcg_temp_free(t1);
1254 tcg_temp_free(t0);
1255 }
1256
1257 /* Load and store */
1258 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1259 int base, int16_t offset)
1260 {
1261 const char *opn = "flt_ldst";
1262 TCGv t0 = tcg_temp_new();
1263
1264 gen_base_offset_addr(ctx, t0, base, offset);
1265 /* Don't do NOP if destination is zero: we must perform the actual
1266 memory access. */
1267 switch (opc) {
1268 case OPC_LWC1:
1269 {
1270 TCGv_i32 fp0 = tcg_temp_new_i32();
1271
1272 tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
1273 tcg_gen_trunc_tl_i32(fp0, t0);
1274 gen_store_fpr32(fp0, ft);
1275 tcg_temp_free_i32(fp0);
1276 }
1277 opn = "lwc1";
1278 break;
1279 case OPC_SWC1:
1280 {
1281 TCGv_i32 fp0 = tcg_temp_new_i32();
1282 TCGv t1 = tcg_temp_new();
1283
1284 gen_load_fpr32(fp0, ft);
1285 tcg_gen_extu_i32_tl(t1, fp0);
1286 tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
1287 tcg_temp_free(t1);
1288 tcg_temp_free_i32(fp0);
1289 }
1290 opn = "swc1";
1291 break;
1292 case OPC_LDC1:
1293 {
1294 TCGv_i64 fp0 = tcg_temp_new_i64();
1295
1296 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
1297 gen_store_fpr64(ctx, fp0, ft);
1298 tcg_temp_free_i64(fp0);
1299 }
1300 opn = "ldc1";
1301 break;
1302 case OPC_SDC1:
1303 {
1304 TCGv_i64 fp0 = tcg_temp_new_i64();
1305
1306 gen_load_fpr64(ctx, fp0, ft);
1307 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
1308 tcg_temp_free_i64(fp0);
1309 }
1310 opn = "sdc1";
1311 break;
1312 default:
1313 MIPS_INVAL(opn);
1314 generate_exception(ctx, EXCP_RI);
1315 goto out;
1316 }
1317 (void)opn; /* avoid a compiler warning */
1318 MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
1319 out:
1320 tcg_temp_free(t0);
1321 }
1322
1323 static void gen_cop1_ldst(CPUState *env, DisasContext *ctx,
1324 uint32_t op, int rt, int rs, int16_t imm)
1325 {
1326 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1327 check_cp1_enabled(ctx);
1328 gen_flt_ldst(ctx, op, rt, rs, imm);
1329 } else {
1330 generate_exception_err(ctx, EXCP_CpU, 1);
1331 }
1332 }
1333
1334 /* Arithmetic with immediate operand */
1335 static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1336 int rt, int rs, int16_t imm)
1337 {
1338 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1339 const char *opn = "imm arith";
1340
1341 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
1342 /* If no destination, treat it as a NOP.
1343 For addi, we must generate the overflow exception when needed. */
1344 MIPS_DEBUG("NOP");
1345 return;
1346 }
1347 switch (opc) {
1348 case OPC_ADDI:
1349 {
1350 TCGv t0 = tcg_temp_local_new();
1351 TCGv t1 = tcg_temp_new();
1352 TCGv t2 = tcg_temp_new();
1353 int l1 = gen_new_label();
1354
1355 gen_load_gpr(t1, rs);
1356 tcg_gen_addi_tl(t0, t1, uimm);
1357 tcg_gen_ext32s_tl(t0, t0);
1358
1359 tcg_gen_xori_tl(t1, t1, ~uimm);
1360 tcg_gen_xori_tl(t2, t0, uimm);
1361 tcg_gen_and_tl(t1, t1, t2);
1362 tcg_temp_free(t2);
1363 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1364 tcg_temp_free(t1);
1365 /* operands of same sign, result different sign */
1366 generate_exception(ctx, EXCP_OVERFLOW);
1367 gen_set_label(l1);
1368 tcg_gen_ext32s_tl(t0, t0);
1369 gen_store_gpr(t0, rt);
1370 tcg_temp_free(t0);
1371 }
1372 opn = "addi";
1373 break;
1374 case OPC_ADDIU:
1375 if (rs != 0) {
1376 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1377 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
1378 } else {
1379 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1380 }
1381 opn = "addiu";
1382 break;
1383 #if defined(TARGET_MIPS64)
1384 case OPC_DADDI:
1385 {
1386 TCGv t0 = tcg_temp_local_new();
1387 TCGv t1 = tcg_temp_new();
1388 TCGv t2 = tcg_temp_new();
1389 int l1 = gen_new_label();
1390
1391 gen_load_gpr(t1, rs);
1392 tcg_gen_addi_tl(t0, t1, uimm);
1393
1394 tcg_gen_xori_tl(t1, t1, ~uimm);
1395 tcg_gen_xori_tl(t2, t0, uimm);
1396 tcg_gen_and_tl(t1, t1, t2);
1397 tcg_temp_free(t2);
1398 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1399 tcg_temp_free(t1);
1400 /* operands of same sign, result different sign */
1401 generate_exception(ctx, EXCP_OVERFLOW);
1402 gen_set_label(l1);
1403 gen_store_gpr(t0, rt);
1404 tcg_temp_free(t0);
1405 }
1406 opn = "daddi";
1407 break;
1408 case OPC_DADDIU:
1409 if (rs != 0) {
1410 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1411 } else {
1412 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1413 }
1414 opn = "daddiu";
1415 break;
1416 #endif
1417 }
1418 (void)opn; /* avoid a compiler warning */
1419 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1420 }
1421
1422 /* Logic with immediate operand */
1423 static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1424 {
1425 target_ulong uimm;
1426 const char *opn = "imm logic";
1427
1428 if (rt == 0) {
1429 /* If no destination, treat it as a NOP. */
1430 MIPS_DEBUG("NOP");
1431 return;
1432 }
1433 uimm = (uint16_t)imm;
1434 switch (opc) {
1435 case OPC_ANDI:
1436 if (likely(rs != 0))
1437 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1438 else
1439 tcg_gen_movi_tl(cpu_gpr[rt], 0);
1440 opn = "andi";
1441 break;
1442 case OPC_ORI:
1443 if (rs != 0)
1444 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1445 else
1446 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1447 opn = "ori";
1448 break;
1449 case OPC_XORI:
1450 if (likely(rs != 0))
1451 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1452 else
1453 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1454 opn = "xori";
1455 break;
1456 case OPC_LUI:
1457 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
1458 opn = "lui";
1459 break;
1460 }
1461 (void)opn; /* avoid a compiler warning */
1462 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1463 }
1464
1465 /* Set on less than with immediate operand */
1466 static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1467 {
1468 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1469 const char *opn = "imm arith";
1470 TCGv t0;
1471
1472 if (rt == 0) {
1473 /* If no destination, treat it as a NOP. */
1474 MIPS_DEBUG("NOP");
1475 return;
1476 }
1477 t0 = tcg_temp_new();
1478 gen_load_gpr(t0, rs);
1479 switch (opc) {
1480 case OPC_SLTI:
1481 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
1482 opn = "slti";
1483 break;
1484 case OPC_SLTIU:
1485 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
1486 opn = "sltiu";
1487 break;
1488 }
1489 (void)opn; /* avoid a compiler warning */
1490 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1491 tcg_temp_free(t0);
1492 }
1493
1494 /* Shifts with immediate operand */
1495 static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
1496 int rt, int rs, int16_t imm)
1497 {
1498 target_ulong uimm = ((uint16_t)imm) & 0x1f;
1499 const char *opn = "imm shift";
1500 TCGv t0;
1501
1502 if (rt == 0) {
1503 /* If no destination, treat it as a NOP. */
1504 MIPS_DEBUG("NOP");
1505 return;
1506 }
1507
1508 t0 = tcg_temp_new();
1509 gen_load_gpr(t0, rs);
1510 switch (opc) {
1511 case OPC_SLL:
1512 tcg_gen_shli_tl(t0, t0, uimm);
1513 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1514 opn = "sll";
1515 break;
1516 case OPC_SRA:
1517 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
1518 opn = "sra";
1519 break;
1520 case OPC_SRL:
1521 if (uimm != 0) {
1522 tcg_gen_ext32u_tl(t0, t0);
1523 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1524 } else {
1525 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1526 }
1527 opn = "srl";
1528 break;
1529 case OPC_ROTR:
1530 if (uimm != 0) {
1531 TCGv_i32 t1 = tcg_temp_new_i32();
1532
1533 tcg_gen_trunc_tl_i32(t1, t0);
1534 tcg_gen_rotri_i32(t1, t1, uimm);
1535 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
1536 tcg_temp_free_i32(t1);
1537 } else {
1538 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1539 }
1540 opn = "rotr";
1541 break;
1542 #if defined(TARGET_MIPS64)
1543 case OPC_DSLL:
1544 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
1545 opn = "dsll";
1546 break;
1547 case OPC_DSRA:
1548 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
1549 opn = "dsra";
1550 break;
1551 case OPC_DSRL:
1552 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1553 opn = "dsrl";
1554 break;
1555 case OPC_DROTR:
1556 if (uimm != 0) {
1557 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
1558 } else {
1559 tcg_gen_mov_tl(cpu_gpr[rt], t0);
1560 }
1561 opn = "drotr";
1562 break;
1563 case OPC_DSLL32:
1564 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
1565 opn = "dsll32";
1566 break;
1567 case OPC_DSRA32:
1568 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
1569 opn = "dsra32";
1570 break;
1571 case OPC_DSRL32:
1572 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
1573 opn = "dsrl32";
1574 break;
1575 case OPC_DROTR32:
1576 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
1577 opn = "drotr32";
1578 break;
1579 #endif
1580 }
1581 (void)opn; /* avoid a compiler warning */
1582 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1583 tcg_temp_free(t0);
1584 }
1585
1586 /* Arithmetic */
1587 static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1588 int rd, int rs, int rt)
1589 {
1590 const char *opn = "arith";
1591
1592 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
1593 && opc != OPC_DADD && opc != OPC_DSUB) {
1594 /* If no destination, treat it as a NOP.
1595 For add & sub, we must generate the overflow exception when needed. */
1596 MIPS_DEBUG("NOP");
1597 return;
1598 }
1599
1600 switch (opc) {
1601 case OPC_ADD:
1602 {
1603 TCGv t0 = tcg_temp_local_new();
1604 TCGv t1 = tcg_temp_new();
1605 TCGv t2 = tcg_temp_new();
1606 int l1 = gen_new_label();
1607
1608 gen_load_gpr(t1, rs);
1609 gen_load_gpr(t2, rt);
1610 tcg_gen_add_tl(t0, t1, t2);
1611 tcg_gen_ext32s_tl(t0, t0);
1612 tcg_gen_xor_tl(t1, t1, t2);
1613 tcg_gen_xor_tl(t2, t0, t2);
1614 tcg_gen_andc_tl(t1, t2, t1);
1615 tcg_temp_free(t2);
1616 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1617 tcg_temp_free(t1);
1618 /* operands of same sign, result different sign */
1619 generate_exception(ctx, EXCP_OVERFLOW);
1620 gen_set_label(l1);
1621 gen_store_gpr(t0, rd);
1622 tcg_temp_free(t0);
1623 }
1624 opn = "add";
1625 break;
1626 case OPC_ADDU:
1627 if (rs != 0 && rt != 0) {
1628 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1629 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1630 } else if (rs == 0 && rt != 0) {
1631 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1632 } else if (rs != 0 && rt == 0) {
1633 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1634 } else {
1635 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1636 }
1637 opn = "addu";
1638 break;
1639 case OPC_SUB:
1640 {
1641 TCGv t0 = tcg_temp_local_new();
1642 TCGv t1 = tcg_temp_new();
1643 TCGv t2 = tcg_temp_new();
1644 int l1 = gen_new_label();
1645
1646 gen_load_gpr(t1, rs);
1647 gen_load_gpr(t2, rt);
1648 tcg_gen_sub_tl(t0, t1, t2);
1649 tcg_gen_ext32s_tl(t0, t0);
1650 tcg_gen_xor_tl(t2, t1, t2);
1651 tcg_gen_xor_tl(t1, t0, t1);
1652 tcg_gen_and_tl(t1, t1, t2);
1653 tcg_temp_free(t2);
1654 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1655 tcg_temp_free(t1);
1656 /* operands of different sign, first operand and result different sign */
1657 generate_exception(ctx, EXCP_OVERFLOW);
1658 gen_set_label(l1);
1659 gen_store_gpr(t0, rd);
1660 tcg_temp_free(t0);
1661 }
1662 opn = "sub";
1663 break;
1664 case OPC_SUBU:
1665 if (rs != 0 && rt != 0) {
1666 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1667 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1668 } else if (rs == 0 && rt != 0) {
1669 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
1670 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1671 } else if (rs != 0 && rt == 0) {
1672 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1673 } else {
1674 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1675 }
1676 opn = "subu";
1677 break;
1678 #if defined(TARGET_MIPS64)
1679 case OPC_DADD:
1680 {
1681 TCGv t0 = tcg_temp_local_new();
1682 TCGv t1 = tcg_temp_new();
1683 TCGv t2 = tcg_temp_new();
1684 int l1 = gen_new_label();
1685
1686 gen_load_gpr(t1, rs);
1687 gen_load_gpr(t2, rt);
1688 tcg_gen_add_tl(t0, t1, t2);
1689 tcg_gen_xor_tl(t1, t1, t2);
1690 tcg_gen_xor_tl(t2, t0, t2);
1691 tcg_gen_andc_tl(t1, t2, t1);
1692 tcg_temp_free(t2);
1693 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1694 tcg_temp_free(t1);
1695 /* operands of same sign, result different sign */
1696 generate_exception(ctx, EXCP_OVERFLOW);
1697 gen_set_label(l1);
1698 gen_store_gpr(t0, rd);
1699 tcg_temp_free(t0);
1700 }
1701 opn = "dadd";
1702 break;
1703 case OPC_DADDU:
1704 if (rs != 0 && rt != 0) {
1705 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1706 } else if (rs == 0 && rt != 0) {
1707 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1708 } else if (rs != 0 && rt == 0) {
1709 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1710 } else {
1711 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1712 }
1713 opn = "daddu";
1714 break;
1715 case OPC_DSUB:
1716 {
1717 TCGv t0 = tcg_temp_local_new();
1718 TCGv t1 = tcg_temp_new();
1719 TCGv t2 = tcg_temp_new();
1720 int l1 = gen_new_label();
1721
1722 gen_load_gpr(t1, rs);
1723 gen_load_gpr(t2, rt);
1724 tcg_gen_sub_tl(t0, t1, t2);
1725 tcg_gen_xor_tl(t2, t1, t2);
1726 tcg_gen_xor_tl(t1, t0, t1);
1727 tcg_gen_and_tl(t1, t1, t2);
1728 tcg_temp_free(t2);
1729 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1730 tcg_temp_free(t1);
1731 /* operands of different sign, first operand and result different sign */
1732 generate_exception(ctx, EXCP_OVERFLOW);
1733 gen_set_label(l1);
1734 gen_store_gpr(t0, rd);
1735 tcg_temp_free(t0);
1736 }
1737 opn = "dsub";
1738 break;
1739 case OPC_DSUBU:
1740 if (rs != 0 && rt != 0) {
1741 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1742 } else if (rs == 0 && rt != 0) {
1743 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
1744 } else if (rs != 0 && rt == 0) {
1745 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1746 } else {
1747 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1748 }
1749 opn = "dsubu";
1750 break;
1751 #endif
1752 case OPC_MUL:
1753 if (likely(rs != 0 && rt != 0)) {
1754 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1755 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1756 } else {
1757 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1758 }
1759 opn = "mul";
1760 break;
1761 }
1762 (void)opn; /* avoid a compiler warning */
1763 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1764 }
1765
1766 /* Conditional move */
1767 static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1768 {
1769 const char *opn = "cond move";
1770 int l1;
1771
1772 if (rd == 0) {
1773 /* If no destination, treat it as a NOP.
1774 For add & sub, we must generate the overflow exception when needed. */
1775 MIPS_DEBUG("NOP");
1776 return;
1777 }
1778
1779 l1 = gen_new_label();
1780 switch (opc) {
1781 case OPC_MOVN:
1782 if (likely(rt != 0))
1783 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1);
1784 else
1785 tcg_gen_br(l1);
1786 opn = "movn";
1787 break;
1788 case OPC_MOVZ:
1789 if (likely(rt != 0))
1790 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1);
1791 opn = "movz";
1792 break;
1793 }
1794 if (rs != 0)
1795 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1796 else
1797 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1798 gen_set_label(l1);
1799
1800 (void)opn; /* avoid a compiler warning */
1801 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1802 }
1803
1804 /* Logic */
1805 static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1806 {
1807 const char *opn = "logic";
1808
1809 if (rd == 0) {
1810 /* If no destination, treat it as a NOP. */
1811 MIPS_DEBUG("NOP");
1812 return;
1813 }
1814
1815 switch (opc) {
1816 case OPC_AND:
1817 if (likely(rs != 0 && rt != 0)) {
1818 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1819 } else {
1820 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1821 }
1822 opn = "and";
1823 break;
1824 case OPC_NOR:
1825 if (rs != 0 && rt != 0) {
1826 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1827 } else if (rs == 0 && rt != 0) {
1828 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
1829 } else if (rs != 0 && rt == 0) {
1830 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
1831 } else {
1832 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
1833 }
1834 opn = "nor";
1835 break;
1836 case OPC_OR:
1837 if (likely(rs != 0 && rt != 0)) {
1838 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1839 } else if (rs == 0 && rt != 0) {
1840 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1841 } else if (rs != 0 && rt == 0) {
1842 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1843 } else {
1844 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1845 }
1846 opn = "or";
1847 break;
1848 case OPC_XOR:
1849 if (likely(rs != 0 && rt != 0)) {
1850 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1851 } else if (rs == 0 && rt != 0) {
1852 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1853 } else if (rs != 0 && rt == 0) {
1854 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1855 } else {
1856 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1857 }
1858 opn = "xor";
1859 break;
1860 }
1861 (void)opn; /* avoid a compiler warning */
1862 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1863 }
1864
1865 /* Set on lower than */
1866 static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1867 {
1868 const char *opn = "slt";
1869 TCGv t0, t1;
1870
1871 if (rd == 0) {
1872 /* If no destination, treat it as a NOP. */
1873 MIPS_DEBUG("NOP");
1874 return;
1875 }
1876
1877 t0 = tcg_temp_new();
1878 t1 = tcg_temp_new();
1879 gen_load_gpr(t0, rs);
1880 gen_load_gpr(t1, rt);
1881 switch (opc) {
1882 case OPC_SLT:
1883 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
1884 opn = "slt";
1885 break;
1886 case OPC_SLTU:
1887 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
1888 opn = "sltu";
1889 break;
1890 }
1891 (void)opn; /* avoid a compiler warning */
1892 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1893 tcg_temp_free(t0);
1894 tcg_temp_free(t1);
1895 }
1896
1897 /* Shifts */
1898 static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
1899 int rd, int rs, int rt)
1900 {
1901 const char *opn = "shifts";
1902 TCGv t0, t1;
1903
1904 if (rd == 0) {
1905 /* If no destination, treat it as a NOP.
1906 For add & sub, we must generate the overflow exception when needed. */
1907 MIPS_DEBUG("NOP");
1908 return;
1909 }
1910
1911 t0 = tcg_temp_new();
1912 t1 = tcg_temp_new();
1913 gen_load_gpr(t0, rs);
1914 gen_load_gpr(t1, rt);
1915 switch (opc) {
1916 case OPC_SLLV:
1917 tcg_gen_andi_tl(t0, t0, 0x1f);
1918 tcg_gen_shl_tl(t0, t1, t0);
1919 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
1920 opn = "sllv";
1921 break;
1922 case OPC_SRAV:
1923 tcg_gen_andi_tl(t0, t0, 0x1f);
1924 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
1925 opn = "srav";
1926 break;
1927 case OPC_SRLV:
1928 tcg_gen_ext32u_tl(t1, t1);
1929 tcg_gen_andi_tl(t0, t0, 0x1f);
1930 tcg_gen_shr_tl(t0, t1, t0);
1931 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
1932 opn = "srlv";
1933 break;
1934 case OPC_ROTRV:
1935 {
1936 TCGv_i32 t2 = tcg_temp_new_i32();
1937 TCGv_i32 t3 = tcg_temp_new_i32();
1938
1939 tcg_gen_trunc_tl_i32(t2, t0);
1940 tcg_gen_trunc_tl_i32(t3, t1);
1941 tcg_gen_andi_i32(t2, t2, 0x1f);
1942 tcg_gen_rotr_i32(t2, t3, t2);
1943 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
1944 tcg_temp_free_i32(t2);
1945 tcg_temp_free_i32(t3);
1946 opn = "rotrv";
1947 }
1948 break;
1949 #if defined(TARGET_MIPS64)
1950 case OPC_DSLLV:
1951 tcg_gen_andi_tl(t0, t0, 0x3f);
1952 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
1953 opn = "dsllv";
1954 break;
1955 case OPC_DSRAV:
1956 tcg_gen_andi_tl(t0, t0, 0x3f);
1957 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
1958 opn = "dsrav";
1959 break;
1960 case OPC_DSRLV:
1961 tcg_gen_andi_tl(t0, t0, 0x3f);
1962 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
1963 opn = "dsrlv";
1964 break;
1965 case OPC_DROTRV:
1966 tcg_gen_andi_tl(t0, t0, 0x3f);
1967 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
1968 opn = "drotrv";
1969 break;
1970 #endif
1971 }
1972 (void)opn; /* avoid a compiler warning */
1973 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1974 tcg_temp_free(t0);
1975 tcg_temp_free(t1);
1976 }
1977
1978 /* Arithmetic on HI/LO registers */
1979 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1980 {
1981 const char *opn = "hilo";
1982
1983 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1984 /* Treat as NOP. */
1985 MIPS_DEBUG("NOP");
1986 return;
1987 }
1988 switch (opc) {
1989 case OPC_MFHI:
1990 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]);
1991 opn = "mfhi";
1992 break;
1993 case OPC_MFLO:
1994 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]);
1995 opn = "mflo";
1996 break;
1997 case OPC_MTHI:
1998 if (reg != 0)
1999 tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]);
2000 else
2001 tcg_gen_movi_tl(cpu_HI[0], 0);
2002 opn = "mthi";
2003 break;
2004 case OPC_MTLO:
2005 if (reg != 0)
2006 tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]);
2007 else
2008 tcg_gen_movi_tl(cpu_LO[0], 0);
2009 opn = "mtlo";
2010 break;
2011 }
2012 (void)opn; /* avoid a compiler warning */
2013 MIPS_DEBUG("%s %s", opn, regnames[reg]);
2014 }
2015
2016 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
2017 int rs, int rt)
2018 {
2019 const char *opn = "mul/div";
2020 TCGv t0, t1;
2021
2022 switch (opc) {
2023 case OPC_DIV:
2024 case OPC_DIVU:
2025 #if defined(TARGET_MIPS64)
2026 case OPC_DDIV:
2027 case OPC_DDIVU:
2028 #endif
2029 t0 = tcg_temp_local_new();
2030 t1 = tcg_temp_local_new();
2031 break;
2032 default:
2033 t0 = tcg_temp_new();
2034 t1 = tcg_temp_new();
2035 break;
2036 }
2037
2038 gen_load_gpr(t0, rs);
2039 gen_load_gpr(t1, rt);
2040 switch (opc) {
2041 case OPC_DIV:
2042 {
2043 int l1 = gen_new_label();
2044 int l2 = gen_new_label();
2045
2046 tcg_gen_ext32s_tl(t0, t0);
2047 tcg_gen_ext32s_tl(t1, t1);
2048 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2049 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
2050 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
2051
2052 tcg_gen_mov_tl(cpu_LO[0], t0);
2053 tcg_gen_movi_tl(cpu_HI[0], 0);
2054 tcg_gen_br(l1);
2055 gen_set_label(l2);
2056 tcg_gen_div_tl(cpu_LO[0], t0, t1);
2057 tcg_gen_rem_tl(cpu_HI[0], t0, t1);
2058 tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
2059 tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
2060 gen_set_label(l1);
2061 }
2062 opn = "div";
2063 break;
2064 case OPC_DIVU:
2065 {
2066 int l1 = gen_new_label();
2067
2068 tcg_gen_ext32u_tl(t0, t0);
2069 tcg_gen_ext32u_tl(t1, t1);
2070 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2071 tcg_gen_divu_tl(cpu_LO[0], t0, t1);
2072 tcg_gen_remu_tl(cpu_HI[0], t0, t1);
2073 tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
2074 tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
2075 gen_set_label(l1);
2076 }
2077 opn = "divu";
2078 break;
2079 case OPC_MULT:
2080 {
2081 TCGv_i64 t2 = tcg_temp_new_i64();
2082 TCGv_i64 t3 = tcg_temp_new_i64();
2083
2084 tcg_gen_ext_tl_i64(t2, t0);
2085 tcg_gen_ext_tl_i64(t3, t1);
2086 tcg_gen_mul_i64(t2, t2, t3);
2087 tcg_temp_free_i64(t3);
2088 tcg_gen_trunc_i64_tl(t0, t2);
2089 tcg_gen_shri_i64(t2, t2, 32);
2090 tcg_gen_trunc_i64_tl(t1, t2);
2091 tcg_temp_free_i64(t2);
2092 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2093 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2094 }
2095 opn = "mult";
2096 break;
2097 case OPC_MULTU:
2098 {
2099 TCGv_i64 t2 = tcg_temp_new_i64();
2100 TCGv_i64 t3 = tcg_temp_new_i64();
2101
2102 tcg_gen_ext32u_tl(t0, t0);
2103 tcg_gen_ext32u_tl(t1, t1);
2104 tcg_gen_extu_tl_i64(t2, t0);
2105 tcg_gen_extu_tl_i64(t3, t1);
2106 tcg_gen_mul_i64(t2, t2, t3);
2107 tcg_temp_free_i64(t3);
2108 tcg_gen_trunc_i64_tl(t0, t2);
2109 tcg_gen_shri_i64(t2, t2, 32);
2110 tcg_gen_trunc_i64_tl(t1, t2);
2111 tcg_temp_free_i64(t2);
2112 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2113 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2114 }
2115 opn = "multu";
2116 break;
2117 #if defined(TARGET_MIPS64)
2118 case OPC_DDIV:
2119 {
2120 int l1 = gen_new_label();
2121 int l2 = gen_new_label();
2122
2123 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2124 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
2125 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
2126 tcg_gen_mov_tl(cpu_LO[0], t0);
2127 tcg_gen_movi_tl(cpu_HI[0], 0);
2128 tcg_gen_br(l1);
2129 gen_set_label(l2);
2130 tcg_gen_div_i64(cpu_LO[0], t0, t1);
2131 tcg_gen_rem_i64(cpu_HI[0], t0, t1);
2132 gen_set_label(l1);
2133 }
2134 opn = "ddiv";
2135 break;
2136 case OPC_DDIVU:
2137 {
2138 int l1 = gen_new_label();
2139
2140 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2141 tcg_gen_divu_i64(cpu_LO[0], t0, t1);
2142 tcg_gen_remu_i64(cpu_HI[0], t0, t1);
2143 gen_set_label(l1);
2144 }
2145 opn = "ddivu";
2146 break;
2147 case OPC_DMULT:
2148 gen_helper_dmult(t0, t1);
2149 opn = "dmult";
2150 break;
2151 case OPC_DMULTU:
2152 gen_helper_dmultu(t0, t1);
2153 opn = "dmultu";
2154 break;
2155 #endif
2156 case OPC_MADD:
2157 {
2158 TCGv_i64 t2 = tcg_temp_new_i64();
2159 TCGv_i64 t3 = tcg_temp_new_i64();
2160
2161 tcg_gen_ext_tl_i64(t2, t0);
2162 tcg_gen_ext_tl_i64(t3, t1);
2163 tcg_gen_mul_i64(t2, t2, t3);
2164 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2165 tcg_gen_add_i64(t2, t2, t3);
2166 tcg_temp_free_i64(t3);
2167 tcg_gen_trunc_i64_tl(t0, t2);
2168 tcg_gen_shri_i64(t2, t2, 32);
2169 tcg_gen_trunc_i64_tl(t1, t2);
2170 tcg_temp_free_i64(t2);
2171 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2172 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2173 }
2174 opn = "madd";
2175 break;
2176 case OPC_MADDU:
2177 {
2178 TCGv_i64 t2 = tcg_temp_new_i64();
2179 TCGv_i64 t3 = tcg_temp_new_i64();
2180
2181 tcg_gen_ext32u_tl(t0, t0);
2182 tcg_gen_ext32u_tl(t1, t1);
2183 tcg_gen_extu_tl_i64(t2, t0);
2184 tcg_gen_extu_tl_i64(t3, t1);
2185 tcg_gen_mul_i64(t2, t2, t3);
2186 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2187 tcg_gen_add_i64(t2, t2, t3);
2188 tcg_temp_free_i64(t3);
2189 tcg_gen_trunc_i64_tl(t0, t2);
2190 tcg_gen_shri_i64(t2, t2, 32);
2191 tcg_gen_trunc_i64_tl(t1, t2);
2192 tcg_temp_free_i64(t2);
2193 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2194 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2195 }
2196 opn = "maddu";
2197 break;
2198 case OPC_MSUB:
2199 {
2200 TCGv_i64 t2 = tcg_temp_new_i64();
2201 TCGv_i64 t3 = tcg_temp_new_i64();
2202
2203 tcg_gen_ext_tl_i64(t2, t0);
2204 tcg_gen_ext_tl_i64(t3, t1);
2205 tcg_gen_mul_i64(t2, t2, t3);
2206 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2207 tcg_gen_sub_i64(t2, t3, t2);
2208 tcg_temp_free_i64(t3);
2209 tcg_gen_trunc_i64_tl(t0, t2);
2210 tcg_gen_shri_i64(t2, t2, 32);
2211 tcg_gen_trunc_i64_tl(t1, t2);
2212 tcg_temp_free_i64(t2);
2213 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2214 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2215 }
2216 opn = "msub";
2217 break;
2218 case OPC_MSUBU:
2219 {
2220 TCGv_i64 t2 = tcg_temp_new_i64();
2221 TCGv_i64 t3 = tcg_temp_new_i64();
2222
2223 tcg_gen_ext32u_tl(t0, t0);
2224 tcg_gen_ext32u_tl(t1, t1);
2225 tcg_gen_extu_tl_i64(t2, t0);
2226 tcg_gen_extu_tl_i64(t3, t1);
2227 tcg_gen_mul_i64(t2, t2, t3);
2228 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2229 tcg_gen_sub_i64(t2, t3, t2);
2230 tcg_temp_free_i64(t3);
2231 tcg_gen_trunc_i64_tl(t0, t2);
2232 tcg_gen_shri_i64(t2, t2, 32);
2233 tcg_gen_trunc_i64_tl(t1, t2);
2234 tcg_temp_free_i64(t2);
2235 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2236 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2237 }
2238 opn = "msubu";
2239 break;
2240 default:
2241 MIPS_INVAL(opn);
2242 generate_exception(ctx, EXCP_RI);
2243 goto out;
2244 }
2245 (void)opn; /* avoid a compiler warning */
2246 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
2247 out:
2248 tcg_temp_free(t0);
2249 tcg_temp_free(t1);
2250 }
2251
2252 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2253 int rd, int rs, int rt)
2254 {
2255 const char *opn = "mul vr54xx";
2256 TCGv t0 = tcg_temp_new();
2257 TCGv t1 = tcg_temp_new();
2258
2259 gen_load_gpr(t0, rs);
2260 gen_load_gpr(t1, rt);
2261
2262 switch (opc) {
2263 case OPC_VR54XX_MULS:
2264 gen_helper_muls(t0, t0, t1);
2265 opn = "muls";
2266 break;
2267 case OPC_VR54XX_MULSU:
2268 gen_helper_mulsu(t0, t0, t1);
2269 opn = "mulsu";
2270 break;
2271 case OPC_VR54XX_MACC:
2272 gen_helper_macc(t0, t0, t1);
2273 opn = "macc";
2274 break;
2275 case OPC_VR54XX_MACCU:
2276 gen_helper_maccu(t0, t0, t1);
2277 opn = "maccu";
2278 break;
2279 case OPC_VR54XX_MSAC:
2280 gen_helper_msac(t0, t0, t1);
2281 opn = "msac";
2282 break;
2283 case OPC_VR54XX_MSACU:
2284 gen_helper_msacu(t0, t0, t1);
2285 opn = "msacu";
2286 break;
2287 case OPC_VR54XX_MULHI:
2288 gen_helper_mulhi(t0, t0, t1);
2289 opn = "mulhi";
2290 break;
2291 case OPC_VR54XX_MULHIU:
2292 gen_helper_mulhiu(t0, t0, t1);
2293 opn = "mulhiu";
2294 break;
2295 case OPC_VR54XX_MULSHI:
2296 gen_helper_mulshi(t0, t0, t1);
2297 opn = "mulshi";
2298 break;
2299 case OPC_VR54XX_MULSHIU:
2300 gen_helper_mulshiu(t0, t0, t1);
2301 opn = "mulshiu";
2302 break;
2303 case OPC_VR54XX_MACCHI:
2304 gen_helper_macchi(t0, t0, t1);
2305 opn = "macchi";
2306 break;
2307 case OPC_VR54XX_MACCHIU:
2308 gen_helper_macchiu(t0, t0, t1);
2309 opn = "macchiu";
2310 break;
2311 case OPC_VR54XX_MSACHI:
2312 gen_helper_msachi(t0, t0, t1);
2313 opn = "msachi";
2314 break;
2315 case OPC_VR54XX_MSACHIU:
2316 gen_helper_msachiu(t0, t0, t1);
2317 opn = "msachiu";
2318 break;
2319 default:
2320 MIPS_INVAL("mul vr54xx");
2321 generate_exception(ctx, EXCP_RI);
2322 goto out;
2323 }
2324 gen_store_gpr(t0, rd);
2325 (void)opn; /* avoid a compiler warning */
2326 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
2327
2328 out:
2329 tcg_temp_free(t0);
2330 tcg_temp_free(t1);
2331 }
2332
2333 static void gen_cl (DisasContext *ctx, uint32_t opc,
2334 int rd, int rs)
2335 {
2336 const char *opn = "CLx";
2337 TCGv t0;
2338
2339 if (rd == 0) {
2340 /* Treat as NOP. */
2341 MIPS_DEBUG("NOP");
2342 return;
2343 }
2344 t0 = tcg_temp_new();
2345 gen_load_gpr(t0, rs);
2346 switch (opc) {
2347 case OPC_CLO:
2348 gen_helper_clo(cpu_gpr[rd], t0);
2349 opn = "clo";
2350 break;
2351 case OPC_CLZ:
2352 gen_helper_clz(cpu_gpr[rd], t0);
2353 opn = "clz";
2354 break;
2355 #if defined(TARGET_MIPS64)
2356 case OPC_DCLO:
2357 gen_helper_dclo(cpu_gpr[rd], t0);
2358 opn = "dclo";
2359 break;
2360 case OPC_DCLZ:
2361 gen_helper_dclz(cpu_gpr[rd], t0);
2362 opn = "dclz";
2363 break;
2364 #endif
2365 }
2366 (void)opn; /* avoid a compiler warning */
2367 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
2368 tcg_temp_free(t0);
2369 }
2370
2371 /* Godson integer instructions */
2372 static void gen_loongson_integer (DisasContext *ctx, uint32_t opc,
2373 int rd, int rs, int rt)
2374 {
2375 const char *opn = "loongson";
2376 TCGv t0, t1;
2377
2378 if (rd == 0) {
2379 /* Treat as NOP. */
2380 MIPS_DEBUG("NOP");
2381 return;
2382 }
2383
2384 switch (opc) {
2385 case OPC_MULT_G_2E:
2386 case OPC_MULT_G_2F:
2387 case OPC_MULTU_G_2E:
2388 case OPC_MULTU_G_2F:
2389 #if defined(TARGET_MIPS64)
2390 case OPC_DMULT_G_2E:
2391 case OPC_DMULT_G_2F:
2392 case OPC_DMULTU_G_2E:
2393 case OPC_DMULTU_G_2F:
2394 #endif
2395 t0 = tcg_temp_new();
2396 t1 = tcg_temp_new();
2397 break;
2398 default:
2399 t0 = tcg_temp_local_new();
2400 t1 = tcg_temp_local_new();
2401 break;
2402 }
2403
2404 gen_load_gpr(t0, rs);
2405 gen_load_gpr(t1, rt);
2406
2407 switch (opc) {
2408 case OPC_MULT_G_2E:
2409 case OPC_MULT_G_2F:
2410 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
2411 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2412 opn = "mult.g";
2413 break;
2414 case OPC_MULTU_G_2E:
2415 case OPC_MULTU_G_2F:
2416 tcg_gen_ext32u_tl(t0, t0);
2417 tcg_gen_ext32u_tl(t1, t1);
2418 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
2419 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2420 opn = "multu.g";
2421 break;
2422 case OPC_DIV_G_2E:
2423 case OPC_DIV_G_2F:
2424 {
2425 int l1 = gen_new_label();
2426 int l2 = gen_new_label();
2427 int l3 = gen_new_label();
2428 tcg_gen_ext32s_tl(t0, t0);
2429 tcg_gen_ext32s_tl(t1, t1);
2430 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
2431 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2432 tcg_gen_br(l3);
2433 gen_set_label(l1);
2434 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
2435 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
2436 tcg_gen_mov_tl(cpu_gpr[rd], t0);
2437 tcg_gen_br(l3);
2438 gen_set_label(l2);
2439 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
2440 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2441 gen_set_label(l3);
2442 }
2443 opn = "div.g";
2444 break;
2445 case OPC_DIVU_G_2E:
2446 case OPC_DIVU_G_2F:
2447 {
2448 int l1 = gen_new_label();
2449 int l2 = gen_new_label();
2450 tcg_gen_ext32u_tl(t0, t0);
2451 tcg_gen_ext32u_tl(t1, t1);
2452 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
2453 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2454 tcg_gen_br(l2);
2455 gen_set_label(l1);
2456 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
2457 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2458 gen_set_label(l2);
2459 }
2460 opn = "divu.g";
2461 break;
2462 case OPC_MOD_G_2E:
2463 case OPC_MOD_G_2F:
2464 {
2465 int l1 = gen_new_label();
2466 int l2 = gen_new_label();
2467 int l3 = gen_new_label();
2468 tcg_gen_ext32u_tl(t0, t0);
2469 tcg_gen_ext32u_tl(t1, t1);
2470 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2471 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
2472 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
2473 gen_set_label(l1);
2474 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2475 tcg_gen_br(l3);
2476 gen_set_label(l2);
2477 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
2478 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2479 gen_set_label(l3);
2480 }
2481 opn = "mod.g";
2482 break;
2483 case OPC_MODU_G_2E:
2484 case OPC_MODU_G_2F:
2485 {
2486 int l1 = gen_new_label();
2487 int l2 = gen_new_label();
2488 tcg_gen_ext32u_tl(t0, t0);
2489 tcg_gen_ext32u_tl(t1, t1);
2490 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
2491 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2492 tcg_gen_br(l2);
2493 gen_set_label(l1);
2494 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
2495 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2496 gen_set_label(l2);
2497 }
2498 opn = "modu.g";
2499 break;
2500 #if defined(TARGET_MIPS64)
2501 case OPC_DMULT_G_2E:
2502 case OPC_DMULT_G_2F:
2503 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
2504 opn = "dmult.g";
2505 break;
2506 case OPC_DMULTU_G_2E:
2507 case OPC_DMULTU_G_2F:
2508 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
2509 opn = "dmultu.g";
2510 break;
2511 case OPC_DDIV_G_2E:
2512 case OPC_DDIV_G_2F:
2513 {
2514 int l1 = gen_new_label();
2515 int l2 = gen_new_label();
2516 int l3 = gen_new_label();
2517 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
2518 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2519 tcg_gen_br(l3);
2520 gen_set_label(l1);
2521 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
2522 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
2523 tcg_gen_mov_tl(cpu_gpr[rd], t0);
2524 tcg_gen_br(l3);
2525 gen_set_label(l2);
2526 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
2527 gen_set_label(l3);
2528 }
2529 opn = "ddiv.g";
2530 break;
2531 case OPC_DDIVU_G_2E:
2532 case OPC_DDIVU_G_2F:
2533 {
2534 int l1 = gen_new_label();
2535 int l2 = gen_new_label();
2536 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
2537 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2538 tcg_gen_br(l2);
2539 gen_set_label(l1);
2540 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
2541 gen_set_label(l2);
2542 }
2543 opn = "ddivu.g";
2544 break;
2545 case OPC_DMOD_G_2E:
2546 case OPC_DMOD_G_2F:
2547 {
2548 int l1 = gen_new_label();
2549 int l2 = gen_new_label();
2550 int l3 = gen_new_label();
2551 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2552 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
2553 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
2554 gen_set_label(l1);
2555 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2556 tcg_gen_br(l3);
2557 gen_set_label(l2);
2558 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
2559 gen_set_label(l3);
2560 }
2561 opn = "dmod.g";
2562 break;
2563 case OPC_DMODU_G_2E:
2564 case OPC_DMODU_G_2F:
2565 {
2566 int l1 = gen_new_label();
2567 int l2 = gen_new_label();
2568 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
2569 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2570 tcg_gen_br(l2);
2571 gen_set_label(l1);
2572 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
2573 gen_set_label(l2);
2574 }
2575 opn = "dmodu.g";
2576 break;
2577 #endif
2578 }
2579
2580 (void)opn; /* avoid a compiler warning */
2581 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
2582 tcg_temp_free(t0);
2583 tcg_temp_free(t1);
2584 }
2585
2586 /* Traps */
2587 static void gen_trap (DisasContext *ctx, uint32_t opc,
2588 int rs, int rt, int16_t imm)
2589 {
2590 int cond;
2591 TCGv t0 = tcg_temp_new();
2592 TCGv t1 = tcg_temp_new();
2593
2594 cond = 0;
2595 /* Load needed operands */
2596 switch (opc) {
2597 case OPC_TEQ:
2598 case OPC_TGE:
2599 case OPC_TGEU:
2600 case OPC_TLT:
2601 case OPC_TLTU:
2602 case OPC_TNE:
2603 /* Compare two registers */
2604 if (rs != rt) {
2605 gen_load_gpr(t0, rs);
2606 gen_load_gpr(t1, rt);
2607 cond = 1;
2608 }
2609 break;
2610 case OPC_TEQI:
2611 case OPC_TGEI:
2612 case OPC_TGEIU:
2613 case OPC_TLTI:
2614 case OPC_TLTIU:
2615 case OPC_TNEI:
2616 /* Compare register to immediate */
2617 if (rs != 0 || imm != 0) {
2618 gen_load_gpr(t0, rs);
2619 tcg_gen_movi_tl(t1, (int32_t)imm);
2620 cond = 1;
2621 }
2622 break;
2623 }
2624 if (cond == 0) {
2625 switch (opc) {
2626 case OPC_TEQ: /* rs == rs */
2627 case OPC_TEQI: /* r0 == 0 */
2628 case OPC_TGE: /* rs >= rs */
2629 case OPC_TGEI: /* r0 >= 0 */
2630 case OPC_TGEU: /* rs >= rs unsigned */
2631 case OPC_TGEIU: /* r0 >= 0 unsigned */
2632 /* Always trap */
2633 generate_exception(ctx, EXCP_TRAP);
2634 break;
2635 case OPC_TLT: /* rs < rs */
2636 case OPC_TLTI: /* r0 < 0 */
2637 case OPC_TLTU: /* rs < rs unsigned */
2638 case OPC_TLTIU: /* r0 < 0 unsigned */
2639 case OPC_TNE: /* rs != rs */
2640 case OPC_TNEI: /* r0 != 0 */
2641 /* Never trap: treat as NOP. */
2642 break;
2643 }
2644 } else {
2645 int l1 = gen_new_label();
2646
2647 switch (opc) {
2648 case OPC_TEQ:
2649 case OPC_TEQI:
2650 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
2651 break;
2652 case OPC_TGE:
2653 case OPC_TGEI:
2654 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
2655 break;
2656 case OPC_TGEU:
2657 case OPC_TGEIU:
2658 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
2659 break;
2660 case OPC_TLT:
2661 case OPC_TLTI:
2662 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
2663 break;
2664 case OPC_TLTU:
2665 case OPC_TLTIU:
2666 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
2667 break;
2668 case OPC_TNE:
2669 case OPC_TNEI:
2670 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
2671 break;
2672 }
2673 generate_exception(ctx, EXCP_TRAP);
2674 gen_set_label(l1);
2675 }
2676 tcg_temp_free(t0);
2677 tcg_temp_free(t1);
2678 }
2679
2680 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2681 {
2682 TranslationBlock *tb;
2683 tb = ctx->tb;
2684 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2685 likely(!ctx->singlestep_enabled)) {
2686 tcg_gen_goto_tb(n);
2687 gen_save_pc(dest);
2688 tcg_gen_exit_tb((tcg_target_long)tb + n);
2689 } else {
2690 gen_save_pc(dest);
2691 if (ctx->singlestep_enabled) {
2692 save_cpu_state(ctx, 0);
2693 gen_helper_0i(raise_exception, EXCP_DEBUG);
2694 }
2695 tcg_gen_exit_tb(0);
2696 }
2697 }
2698
2699 /* Branches (before delay slot) */
2700 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2701 int insn_bytes,
2702 int rs, int rt, int32_t offset)
2703 {
2704 target_ulong btgt = -1;
2705 int blink = 0;
2706 int bcond_compute = 0;
2707 TCGv t0 = tcg_temp_new();
2708 TCGv t1 = tcg_temp_new();
2709
2710 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2711 #ifdef MIPS_DEBUG_DISAS
2712 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
2713 #endif
2714 generate_exception(ctx, EXCP_RI);
2715 goto out;
2716 }
2717
2718 /* Load needed operands */
2719 switch (opc) {
2720 case OPC_BEQ:
2721 case OPC_BEQL:
2722 case OPC_BNE:
2723 case OPC_BNEL:
2724 /* Compare two registers */
2725 if (rs != rt) {
2726 gen_load_gpr(t0, rs);
2727 gen_load_gpr(t1, rt);
2728 bcond_compute = 1;
2729 }
2730 btgt = ctx->pc + insn_bytes + offset;
2731 break;
2732 case OPC_BGEZ:
2733 case OPC_BGEZAL:
2734 case OPC_BGEZALS:
2735 case OPC_BGEZALL:
2736 case OPC_BGEZL:
2737 case OPC_BGTZ:
2738 case OPC_BGTZL:
2739 case OPC_BLEZ:
2740 case OPC_BLEZL:
2741 case OPC_BLTZ:
2742 case OPC_BLTZAL:
2743 case OPC_BLTZALS:
2744 case OPC_BLTZALL:
2745 case OPC_BLTZL:
2746 /* Compare to zero */
2747 if (rs != 0) {
2748 gen_load_gpr(t0, rs);
2749 bcond_compute = 1;
2750 }
2751 btgt = ctx->pc + insn_bytes + offset;
2752 break;
2753 case OPC_J:
2754 case OPC_JAL:
2755 case OPC_JALX:
2756 case OPC_JALS:
2757 case OPC_JALXS:
2758 /* Jump to immediate */
2759 btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_t)offset;
2760 break;
2761 case OPC_JR:
2762 case OPC_JALR:
2763 case OPC_JALRC:
2764 case OPC_JALRS:
2765 /* Jump to register */
2766 if (offset != 0 && offset != 16) {
2767 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2768 others are reserved. */
2769 MIPS_INVAL("jump hint");
2770 generate_exception(ctx, EXCP_RI);
2771 goto out;
2772 }
2773 gen_load_gpr(btarget, rs);
2774 break;
2775 default:
2776 MIPS_INVAL("branch/jump");
2777 generate_exception(ctx, EXCP_RI);
2778 goto out;
2779 }
2780 if (bcond_compute == 0) {
2781 /* No condition to be computed */
2782 switch (opc) {
2783 case OPC_BEQ: /* rx == rx */
2784 case OPC_BEQL: /* rx == rx likely */
2785 case OPC_BGEZ: /* 0 >= 0 */
2786 case OPC_BGEZL: /* 0 >= 0 likely */
2787 case OPC_BLEZ: /* 0 <= 0 */
2788 case OPC_BLEZL: /* 0 <= 0 likely */
2789 /* Always take */
2790 ctx->hflags |= MIPS_HFLAG_B;
2791 MIPS_DEBUG("balways");
2792 break;
2793 case OPC_BGEZALS:
2794 case OPC_BGEZAL: /* 0 >= 0 */
2795 case OPC_BGEZALL: /* 0 >= 0 likely */
2796 ctx->hflags |= (opc == OPC_BGEZALS
2797 ? MIPS_HFLAG_BDS16
2798 : MIPS_HFLAG_BDS32);
2799 /* Always take and link */
2800 blink = 31;
2801 ctx->hflags |= MIPS_HFLAG_B;
2802 MIPS_DEBUG("balways and link");
2803 break;
2804 case OPC_BNE: /* rx != rx */
2805 case OPC_BGTZ: /* 0 > 0 */
2806 case OPC_BLTZ: /* 0 < 0 */
2807 /* Treat as NOP. */
2808 MIPS_DEBUG("bnever (NOP)");
2809 goto out;
2810 case OPC_BLTZALS:
2811 case OPC_BLTZAL: /* 0 < 0 */
2812 ctx->hflags |= (opc == OPC_BLTZALS
2813 ? MIPS_HFLAG_BDS16
2814 : MIPS_HFLAG_BDS32);
2815 /* Handle as an unconditional branch to get correct delay
2816 slot checking. */
2817 blink = 31;
2818 btgt = ctx->pc + (opc == OPC_BLTZALS ? 6 : 8);
2819 ctx->hflags |= MIPS_HFLAG_B;
2820 MIPS_DEBUG("bnever and link");
2821 break;
2822 case OPC_BLTZALL: /* 0 < 0 likely */
2823 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
2824 /* Skip the instruction in the delay slot */
2825 MIPS_DEBUG("bnever, link and skip");
2826 ctx->pc += 4;
2827 goto out;
2828 case OPC_BNEL: /* rx != rx likely */
2829 case OPC_BGTZL: /* 0 > 0 likely */
2830 case OPC_BLTZL: /* 0 < 0 likely */
2831 /* Skip the instruction in the delay slot */
2832 MIPS_DEBUG("bnever and skip");
2833 ctx->pc += 4;
2834 goto out;
2835 case OPC_J:
2836 ctx->hflags |= MIPS_HFLAG_B;
2837 MIPS_DEBUG("j " TARGET_FMT_lx, btgt);
2838 break;
2839 case OPC_JALXS:
2840 case OPC_JALX:
2841 ctx->hflags |= MIPS_HFLAG_BX;
2842 /* Fallthrough */
2843 case OPC_JALS:
2844 case OPC_JAL:
2845 blink = 31;
2846 ctx->hflags |= MIPS_HFLAG_B;
2847 ctx->hflags |= ((opc == OPC_JALS || opc == OPC_JALXS)
2848 ? MIPS_HFLAG_BDS16
2849 : MIPS_HFLAG_BDS32);
2850 MIPS_DEBUG("jal " TARGET_FMT_lx, btgt);
2851 break;
2852 case OPC_JR:
2853 ctx->hflags |= MIPS_HFLAG_BR;
2854 if (insn_bytes == 4)
2855 ctx->hflags |= MIPS_HFLAG_BDS32;
2856 MIPS_DEBUG("jr %s", regnames[rs]);
2857 break;
2858 case OPC_JALRS:
2859 case OPC_JALR:
2860 case OPC_JALRC:
2861 blink = rt;
2862 ctx->hflags |= MIPS_HFLAG_BR;
2863 ctx->hflags |= (opc == OPC_JALRS
2864 ? MIPS_HFLAG_BDS16
2865 : MIPS_HFLAG_BDS32);
2866 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
2867 break;
2868 default:
2869 MIPS_INVAL("branch/jump");
2870 generate_exception(ctx, EXCP_RI);
2871 goto out;
2872 }
2873 } else {
2874 switch (opc) {
2875 case OPC_BEQ:
2876 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
2877 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2878 regnames[rs], regnames[rt], btgt);
2879 goto not_likely;
2880 case OPC_BEQL:
2881 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
2882 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2883 regnames[rs], regnames[rt], btgt);
2884 goto likely;
2885 case OPC_BNE:
2886 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
2887 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2888 regnames[rs], regnames[rt], btgt);
2889 goto not_likely;
2890 case OPC_BNEL:
2891 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
2892 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2893 regnames[rs], regnames[rt], btgt);
2894 goto likely;
2895 case OPC_BGEZ:
2896 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
2897 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2898 goto not_likely;
2899 case OPC_BGEZL:
2900 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
2901 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2902 goto likely;
2903 case OPC_BGEZALS:
2904 case OPC_BGEZAL:
2905 ctx->hflags |= (opc == OPC_BGEZALS
2906 ? MIPS_HFLAG_BDS16
2907 : MIPS_HFLAG_BDS32);
2908 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
2909 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2910 blink = 31;
2911 goto not_likely;
2912 case OPC_BGEZALL:
2913 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
2914 blink = 31;
2915 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2916 goto likely;
2917 case OPC_BGTZ:
2918 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
2919 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2920 goto not_likely;
2921 case OPC_BGTZL:
2922 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
2923 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2924 goto likely;
2925 case OPC_BLEZ:
2926 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
2927 MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2928 goto not_likely;
2929 case OPC_BLEZL:
2930 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
2931 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2932 goto likely;
2933 case OPC_BLTZ:
2934 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
2935 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2936 goto not_likely;
2937 case OPC_BLTZL:
2938 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
2939 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2940 goto likely;
2941 case OPC_BLTZALS:
2942 case OPC_BLTZAL:
2943 ctx->hflags |= (opc == OPC_BLTZALS
2944 ? MIPS_HFLAG_BDS16
2945 : MIPS_HFLAG_BDS32);
2946 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
2947 blink = 31;
2948 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2949 not_likely:
2950 ctx->hflags |= MIPS_HFLAG_BC;
2951 break;
2952 case OPC_BLTZALL:
2953 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
2954 blink = 31;
2955 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2956 likely:
2957 ctx->hflags |= MIPS_HFLAG_BL;
2958 break;
2959 default:
2960 MIPS_INVAL("conditional branch/jump");
2961 generate_exception(ctx, EXCP_RI);
2962 goto out;
2963 }
2964 }
2965 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
2966 blink, ctx->hflags, btgt);
2967
2968 ctx->btarget = btgt;
2969 if (blink > 0) {
2970 int post_delay = insn_bytes;
2971 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
2972
2973 if (opc != OPC_JALRC)
2974 post_delay += ((ctx->hflags & MIPS_HFLAG_BDS16) ? 2 : 4);
2975
2976 tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit);
2977 }
2978
2979 out:
2980 if (insn_bytes == 2)
2981 ctx->hflags |= MIPS_HFLAG_B16;
2982 tcg_temp_free(t0);
2983 tcg_temp_free(t1);
2984 }
2985
2986 /* special3 bitfield operations */
2987 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2988 int rs, int lsb, int msb)
2989 {
2990 TCGv t0 = tcg_temp_new();
2991 TCGv t1 = tcg_temp_new();
2992 target_ulong mask;
2993
2994 gen_load_gpr(t1, rs);
2995 switch (opc) {
2996 case OPC_EXT:
2997 if (lsb + msb > 31)
2998 goto fail;
2999 tcg_gen_shri_tl(t0, t1, lsb);
3000 if (msb != 31) {
3001 tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);
3002 } else {
3003 tcg_gen_ext32s_tl(t0, t0);
3004 }
3005 break;
3006 #if defined(TARGET_MIPS64)
3007 case OPC_DEXTM:
3008 tcg_gen_shri_tl(t0, t1, lsb);
3009 if (msb != 31) {
3010 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1);
3011 }
3012 break;
3013 case OPC_DEXTU:
3014 tcg_gen_shri_tl(t0, t1, lsb + 32);
3015 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
3016 break;
3017 case OPC_DEXT:
3018 tcg_gen_shri_tl(t0, t1, lsb);
3019 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
3020 break;
3021 #endif
3022 case OPC_INS:
3023 if (lsb > msb)
3024 goto fail;
3025 mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb;
3026 gen_load_gpr(t0, rt);
3027 tcg_gen_andi_tl(t0, t0, ~mask);
3028 tcg_gen_shli_tl(t1, t1, lsb);
3029 tcg_gen_andi_tl(t1, t1, mask);
3030 tcg_gen_or_tl(t0, t0, t1);
3031 tcg_gen_ext32s_tl(t0, t0);
3032 break;
3033 #if defined(TARGET_MIPS64)
3034 case OPC_DINSM:
3035 if (lsb > msb)
3036 goto fail;
3037 mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb;
3038 gen_load_gpr(t0, rt);
3039 tcg_gen_andi_tl(t0, t0, ~mask);
3040 tcg_gen_shli_tl(t1, t1, lsb);
3041 tcg_gen_andi_tl(t1, t1, mask);
3042 tcg_gen_or_tl(t0, t0, t1);
3043 break;
3044 case OPC_DINSU:
3045 if (lsb > msb)
3046 goto fail;
3047 mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32);
3048 gen_load_gpr(t0, rt);
3049 tcg_gen_andi_tl(t0, t0, ~mask);
3050 tcg_gen_shli_tl(t1, t1, lsb + 32);
3051 tcg_gen_andi_tl(t1, t1, mask);
3052 tcg_gen_or_tl(t0, t0, t1);
3053 break;
3054 case OPC_DINS:
3055 if (lsb > msb)
3056 goto fail;
3057 gen_load_gpr(t0, rt);
3058 mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
3059 gen_load_gpr(t0, rt);
3060 tcg_gen_andi_tl(t0, t0, ~mask);
3061 tcg_gen_shli_tl(t1, t1, lsb);
3062 tcg_gen_andi_tl(t1, t1, mask);
3063 tcg_gen_or_tl(t0, t0, t1);
3064 break;
3065 #endif
3066 default:
3067 fail:
3068 MIPS_INVAL("bitops");
3069 generate_exception(ctx, EXCP_RI);
3070 tcg_temp_free(t0);
3071 tcg_temp_free(t1);
3072 return;
3073 }
3074 gen_store_gpr(t0, rt);
3075 tcg_temp_free(t0);
3076 tcg_temp_free(t1);
3077 }
3078
3079 static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
3080 {
3081 TCGv t0;
3082
3083 if (rd == 0) {
3084 /* If no destination, treat it as a NOP. */
3085 MIPS_DEBUG("NOP");
3086 return;
3087 }
3088
3089 t0 = tcg_temp_new();
3090 gen_load_gpr(t0, rt);
3091 switch (op2) {
3092 case OPC_WSBH:
3093 {
3094 TCGv t1 = tcg_temp_new();
3095
3096 tcg_gen_shri_tl(t1, t0, 8);
3097 tcg_gen_andi_tl(t1, t1, 0x00FF00FF);
3098 tcg_gen_shli_tl(t0, t0, 8);
3099 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF);
3100 tcg_gen_or_tl(t0, t0, t1);
3101 tcg_temp_free(t1);
3102 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
3103 }
3104 break;
3105 case OPC_SEB:
3106 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
3107 break;
3108 case OPC_SEH:
3109 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
3110 break;
3111 #if defined(TARGET_MIPS64)
3112 case OPC_DSBH:
3113 {
3114 TCGv t1 = tcg_temp_new();
3115
3116 tcg_gen_shri_tl(t1, t0, 8);
3117 tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL);
3118 tcg_gen_shli_tl(t0, t0, 8);
3119 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL);
3120 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
3121 tcg_temp_free(t1);
3122 }
3123 break;
3124 case OPC_DSHD:
3125 {
3126 TCGv t1 = tcg_temp_new();
3127
3128 tcg_gen_shri_tl(t1, t0, 16);
3129 tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL);
3130 tcg_gen_shli_tl(t0, t0, 16);
3131 tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL);
3132 tcg_gen_or_tl(t0, t0, t1);
3133 tcg_gen_shri_tl(t1, t0, 32);
3134 tcg_gen_shli_tl(t0, t0, 32);
3135 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
3136 tcg_temp_free(t1);
3137 }
3138 break;
3139 #endif
3140 default:
3141 MIPS_INVAL("bsfhl");
3142 generate_exception(ctx, EXCP_RI);
3143 tcg_temp_free(t0);
3144 return;
3145 }
3146 tcg_temp_free(t0);
3147 }