scsi: pvscsi: check command descriptor ring buffer size (CVE-2016-4952)
[qemu.git] / target-mips / translate_init.c
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t CP1_fcr31;
88 int32_t MSAIR;
89 int32_t SEGBITS;
90 int32_t PABITS;
91 int32_t CP0_SRSConf0_rw_bitmask;
92 int32_t CP0_SRSConf0;
93 int32_t CP0_SRSConf1_rw_bitmask;
94 int32_t CP0_SRSConf1;
95 int32_t CP0_SRSConf2_rw_bitmask;
96 int32_t CP0_SRSConf2;
97 int32_t CP0_SRSConf3_rw_bitmask;
98 int32_t CP0_SRSConf3;
99 int32_t CP0_SRSConf4_rw_bitmask;
100 int32_t CP0_SRSConf4;
101 int32_t CP0_PageGrain_rw_bitmask;
102 int32_t CP0_PageGrain;
103 int insn_flags;
104 enum mips_mmu_types mmu_type;
105 };
106
107 /*****************************************************************************/
108 /* MIPS CPU definitions */
109 static const mips_def_t mips_defs[] =
110 {
111 {
112 .name = "4Kc",
113 .CP0_PRid = 0x00018000,
114 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
115 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
116 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
117 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
118 (0 << CP0C1_CA),
119 .CP0_Config2 = MIPS_CONFIG2,
120 .CP0_Config3 = MIPS_CONFIG3,
121 .CP0_LLAddr_rw_bitmask = 0,
122 .CP0_LLAddr_shift = 4,
123 .SYNCI_Step = 32,
124 .CCRes = 2,
125 .CP0_Status_rw_bitmask = 0x1278FF17,
126 .SEGBITS = 32,
127 .PABITS = 32,
128 .insn_flags = CPU_MIPS32,
129 .mmu_type = MMU_TYPE_R4000,
130 },
131 {
132 .name = "4Km",
133 .CP0_PRid = 0x00018300,
134 /* Config1 implemented, fixed mapping MMU,
135 no virtual icache, uncached coherency. */
136 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
137 .CP0_Config1 = MIPS_CONFIG1 |
138 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
139 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
140 (1 << CP0C1_CA),
141 .CP0_Config2 = MIPS_CONFIG2,
142 .CP0_Config3 = MIPS_CONFIG3,
143 .CP0_LLAddr_rw_bitmask = 0,
144 .CP0_LLAddr_shift = 4,
145 .SYNCI_Step = 32,
146 .CCRes = 2,
147 .CP0_Status_rw_bitmask = 0x1258FF17,
148 .SEGBITS = 32,
149 .PABITS = 32,
150 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
151 .mmu_type = MMU_TYPE_FMT,
152 },
153 {
154 .name = "4KEcR1",
155 .CP0_PRid = 0x00018400,
156 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
157 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
158 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
159 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
160 (0 << CP0C1_CA),
161 .CP0_Config2 = MIPS_CONFIG2,
162 .CP0_Config3 = MIPS_CONFIG3,
163 .CP0_LLAddr_rw_bitmask = 0,
164 .CP0_LLAddr_shift = 4,
165 .SYNCI_Step = 32,
166 .CCRes = 2,
167 .CP0_Status_rw_bitmask = 0x1278FF17,
168 .SEGBITS = 32,
169 .PABITS = 32,
170 .insn_flags = CPU_MIPS32,
171 .mmu_type = MMU_TYPE_R4000,
172 },
173 {
174 .name = "4KEmR1",
175 .CP0_PRid = 0x00018500,
176 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
177 .CP0_Config1 = MIPS_CONFIG1 |
178 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
179 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
180 (1 << CP0C1_CA),
181 .CP0_Config2 = MIPS_CONFIG2,
182 .CP0_Config3 = MIPS_CONFIG3,
183 .CP0_LLAddr_rw_bitmask = 0,
184 .CP0_LLAddr_shift = 4,
185 .SYNCI_Step = 32,
186 .CCRes = 2,
187 .CP0_Status_rw_bitmask = 0x1258FF17,
188 .SEGBITS = 32,
189 .PABITS = 32,
190 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
191 .mmu_type = MMU_TYPE_FMT,
192 },
193 {
194 .name = "4KEc",
195 .CP0_PRid = 0x00019000,
196 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
197 (MMU_TYPE_R4000 << CP0C0_MT),
198 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
199 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
200 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
201 (0 << CP0C1_CA),
202 .CP0_Config2 = MIPS_CONFIG2,
203 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
204 .CP0_LLAddr_rw_bitmask = 0,
205 .CP0_LLAddr_shift = 4,
206 .SYNCI_Step = 32,
207 .CCRes = 2,
208 .CP0_Status_rw_bitmask = 0x1278FF17,
209 .SEGBITS = 32,
210 .PABITS = 32,
211 .insn_flags = CPU_MIPS32R2,
212 .mmu_type = MMU_TYPE_R4000,
213 },
214 {
215 .name = "4KEm",
216 .CP0_PRid = 0x00019100,
217 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
218 (MMU_TYPE_FMT << CP0C0_MT),
219 .CP0_Config1 = MIPS_CONFIG1 |
220 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
221 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
222 (1 << CP0C1_CA),
223 .CP0_Config2 = MIPS_CONFIG2,
224 .CP0_Config3 = MIPS_CONFIG3,
225 .CP0_LLAddr_rw_bitmask = 0,
226 .CP0_LLAddr_shift = 4,
227 .SYNCI_Step = 32,
228 .CCRes = 2,
229 .CP0_Status_rw_bitmask = 0x1258FF17,
230 .SEGBITS = 32,
231 .PABITS = 32,
232 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
233 .mmu_type = MMU_TYPE_FMT,
234 },
235 {
236 .name = "24Kc",
237 .CP0_PRid = 0x00019300,
238 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
239 (MMU_TYPE_R4000 << CP0C0_MT),
240 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
241 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
242 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
243 (1 << CP0C1_CA),
244 .CP0_Config2 = MIPS_CONFIG2,
245 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
246 .CP0_LLAddr_rw_bitmask = 0,
247 .CP0_LLAddr_shift = 4,
248 .SYNCI_Step = 32,
249 .CCRes = 2,
250 /* No DSP implemented. */
251 .CP0_Status_rw_bitmask = 0x1278FF1F,
252 .SEGBITS = 32,
253 .PABITS = 32,
254 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
255 .mmu_type = MMU_TYPE_R4000,
256 },
257 {
258 .name = "24Kf",
259 .CP0_PRid = 0x00019300,
260 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
261 (MMU_TYPE_R4000 << CP0C0_MT),
262 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
263 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
264 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
265 (1 << CP0C1_CA),
266 .CP0_Config2 = MIPS_CONFIG2,
267 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
268 .CP0_LLAddr_rw_bitmask = 0,
269 .CP0_LLAddr_shift = 4,
270 .SYNCI_Step = 32,
271 .CCRes = 2,
272 /* No DSP implemented. */
273 .CP0_Status_rw_bitmask = 0x3678FF1F,
274 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
275 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 .SEGBITS = 32,
277 .PABITS = 32,
278 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
279 .mmu_type = MMU_TYPE_R4000,
280 },
281 {
282 .name = "34Kf",
283 .CP0_PRid = 0x00019500,
284 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
285 (MMU_TYPE_R4000 << CP0C0_MT),
286 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
287 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
288 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
289 (1 << CP0C1_CA),
290 .CP0_Config2 = MIPS_CONFIG2,
291 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
292 (1 << CP0C3_DSPP),
293 .CP0_LLAddr_rw_bitmask = 0,
294 .CP0_LLAddr_shift = 0,
295 .SYNCI_Step = 32,
296 .CCRes = 2,
297 .CP0_Status_rw_bitmask = 0x3778FF1F,
298 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
299 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
300 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
301 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
302 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
303 (0xff << CP0TCSt_TASID),
304 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
305 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
306 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
307 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
308 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
309 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
310 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
311 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
312 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
313 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
314 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
315 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
316 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
317 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
318 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
319 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
320 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
321 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
322 .SEGBITS = 32,
323 .PABITS = 32,
324 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
325 .mmu_type = MMU_TYPE_R4000,
326 },
327 {
328 .name = "74Kf",
329 .CP0_PRid = 0x00019700,
330 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
331 (MMU_TYPE_R4000 << CP0C0_MT),
332 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
333 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
334 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
335 (1 << CP0C1_CA),
336 .CP0_Config2 = MIPS_CONFIG2,
337 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
338 (1 << CP0C3_VInt),
339 .CP0_LLAddr_rw_bitmask = 0,
340 .CP0_LLAddr_shift = 4,
341 .SYNCI_Step = 32,
342 .CCRes = 2,
343 .CP0_Status_rw_bitmask = 0x3778FF1F,
344 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
345 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
346 .SEGBITS = 32,
347 .PABITS = 32,
348 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
349 .mmu_type = MMU_TYPE_R4000,
350 },
351 {
352 .name = "M14K",
353 .CP0_PRid = 0x00019b00,
354 /* Config1 implemented, fixed mapping MMU,
355 no virtual icache, uncached coherency. */
356 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
357 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
358 .CP0_Config1 = MIPS_CONFIG1,
359 .CP0_Config2 = MIPS_CONFIG2,
360 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
361 .CP0_LLAddr_rw_bitmask = 0,
362 .CP0_LLAddr_shift = 4,
363 .SYNCI_Step = 32,
364 .CCRes = 2,
365 .CP0_Status_rw_bitmask = 0x1258FF17,
366 .SEGBITS = 32,
367 .PABITS = 32,
368 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
369 .mmu_type = MMU_TYPE_FMT,
370 },
371 {
372 .name = "M14Kc",
373 /* This is the TLB-based MMU core. */
374 .CP0_PRid = 0x00019c00,
375 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
376 (MMU_TYPE_R4000 << CP0C0_MT),
377 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
378 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
379 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
380 .CP0_Config2 = MIPS_CONFIG2,
381 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
382 .CP0_LLAddr_rw_bitmask = 0,
383 .CP0_LLAddr_shift = 4,
384 .SYNCI_Step = 32,
385 .CCRes = 2,
386 .CP0_Status_rw_bitmask = 0x1278FF17,
387 .SEGBITS = 32,
388 .PABITS = 32,
389 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
390 .mmu_type = MMU_TYPE_R4000,
391 },
392 {
393 /* FIXME:
394 * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
395 * Config4: MMUExtDef
396 * Config5: EVA, MRP
397 * FIR(FCR0): Has2008
398 * */
399 .name = "P5600",
400 .CP0_PRid = 0x0001A800,
401 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
402 (MMU_TYPE_R4000 << CP0C0_MT),
403 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
404 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
405 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
406 (1 << CP0C1_PC) | (1 << CP0C1_FP),
407 .CP0_Config2 = MIPS_CONFIG2,
408 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
409 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
410 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
411 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
412 (0x1c << CP0C4_KScrExist),
413 .CP0_Config4_rw_bitmask = 0,
414 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) |
415 (1 << CP0C5_MRP),
416 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
417 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
418 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
419 .CP0_LLAddr_rw_bitmask = 0,
420 .CP0_LLAddr_shift = 0,
421 .SYNCI_Step = 32,
422 .CCRes = 2,
423 .CP0_Status_rw_bitmask = 0x3C68FF1F,
424 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
425 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
426 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
427 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
428 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
429 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
430 .SEGBITS = 32,
431 .PABITS = 40,
432 .insn_flags = CPU_MIPS32R5 | ASE_MSA,
433 .mmu_type = MMU_TYPE_R4000,
434 },
435 {
436 /* A generic CPU supporting MIPS32 Release 6 ISA.
437 FIXME: Support IEEE 754-2008 FP.
438 Eventually this should be replaced by a real CPU model. */
439 .name = "mips32r6-generic",
440 .CP0_PRid = 0x00010000,
441 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
442 (MMU_TYPE_R4000 << CP0C0_MT),
443 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
444 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
445 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
446 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
447 .CP0_Config2 = MIPS_CONFIG2,
448 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
449 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
450 (1 << CP0C3_RXI) | (1U << CP0C3_M),
451 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
452 (3 << CP0C4_IE) | (1U << CP0C4_M),
453 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
454 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
455 (1 << CP0C5_UFE),
456 .CP0_LLAddr_rw_bitmask = 0,
457 .CP0_LLAddr_shift = 0,
458 .SYNCI_Step = 32,
459 .CCRes = 2,
460 .CP0_Status_rw_bitmask = 0x3058FF1F,
461 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
462 (1U << CP0PG_RIE),
463 .CP0_PageGrain_rw_bitmask = 0,
464 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
465 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
466 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
467 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
468 .SEGBITS = 32,
469 .PABITS = 32,
470 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
471 .mmu_type = MMU_TYPE_R4000,
472 },
473 #if defined(TARGET_MIPS64)
474 {
475 .name = "R4000",
476 .CP0_PRid = 0x00000400,
477 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
478 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
479 /* Note: Config1 is only used internally, the R4000 has only Config0. */
480 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
481 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
482 .CP0_LLAddr_shift = 4,
483 .SYNCI_Step = 16,
484 .CCRes = 2,
485 .CP0_Status_rw_bitmask = 0x3678FFFF,
486 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
487 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
488 .SEGBITS = 40,
489 .PABITS = 36,
490 .insn_flags = CPU_MIPS3,
491 .mmu_type = MMU_TYPE_R4000,
492 },
493 {
494 .name = "VR5432",
495 .CP0_PRid = 0x00005400,
496 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
497 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
498 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
499 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
500 .CP0_LLAddr_shift = 4,
501 .SYNCI_Step = 16,
502 .CCRes = 2,
503 .CP0_Status_rw_bitmask = 0x3678FFFF,
504 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
505 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
506 .SEGBITS = 40,
507 .PABITS = 32,
508 .insn_flags = CPU_VR54XX,
509 .mmu_type = MMU_TYPE_R4000,
510 },
511 {
512 .name = "5Kc",
513 .CP0_PRid = 0x00018100,
514 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
515 (MMU_TYPE_R4000 << CP0C0_MT),
516 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
517 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
518 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
519 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
520 .CP0_Config2 = MIPS_CONFIG2,
521 .CP0_Config3 = MIPS_CONFIG3,
522 .CP0_LLAddr_rw_bitmask = 0,
523 .CP0_LLAddr_shift = 4,
524 .SYNCI_Step = 32,
525 .CCRes = 2,
526 .CP0_Status_rw_bitmask = 0x12F8FFFF,
527 .SEGBITS = 42,
528 .PABITS = 36,
529 .insn_flags = CPU_MIPS64,
530 .mmu_type = MMU_TYPE_R4000,
531 },
532 {
533 .name = "5Kf",
534 .CP0_PRid = 0x00018100,
535 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
536 (MMU_TYPE_R4000 << CP0C0_MT),
537 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
538 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
539 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
540 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
541 .CP0_Config2 = MIPS_CONFIG2,
542 .CP0_Config3 = MIPS_CONFIG3,
543 .CP0_LLAddr_rw_bitmask = 0,
544 .CP0_LLAddr_shift = 4,
545 .SYNCI_Step = 32,
546 .CCRes = 2,
547 .CP0_Status_rw_bitmask = 0x36F8FFFF,
548 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
549 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
550 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
551 .SEGBITS = 42,
552 .PABITS = 36,
553 .insn_flags = CPU_MIPS64,
554 .mmu_type = MMU_TYPE_R4000,
555 },
556 {
557 .name = "20Kc",
558 /* We emulate a later version of the 20Kc, earlier ones had a broken
559 WAIT instruction. */
560 .CP0_PRid = 0x000182a0,
561 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
562 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
563 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
564 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
565 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
566 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
567 .CP0_Config2 = MIPS_CONFIG2,
568 .CP0_Config3 = MIPS_CONFIG3,
569 .CP0_LLAddr_rw_bitmask = 0,
570 .CP0_LLAddr_shift = 0,
571 .SYNCI_Step = 32,
572 .CCRes = 1,
573 .CP0_Status_rw_bitmask = 0x36FBFFFF,
574 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
575 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
576 (1 << FCR0_D) | (1 << FCR0_S) |
577 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
578 .SEGBITS = 40,
579 .PABITS = 36,
580 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
581 .mmu_type = MMU_TYPE_R4000,
582 },
583 {
584 /* A generic CPU providing MIPS64 Release 2 features.
585 FIXME: Eventually this should be replaced by a real CPU model. */
586 .name = "MIPS64R2-generic",
587 .CP0_PRid = 0x00010000,
588 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
589 (MMU_TYPE_R4000 << CP0C0_MT),
590 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
591 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
592 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
593 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
594 .CP0_Config2 = MIPS_CONFIG2,
595 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
596 .CP0_LLAddr_rw_bitmask = 0,
597 .CP0_LLAddr_shift = 0,
598 .SYNCI_Step = 32,
599 .CCRes = 2,
600 .CP0_Status_rw_bitmask = 0x36FBFFFF,
601 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
602 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
603 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
604 .SEGBITS = 42,
605 .PABITS = 36,
606 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
607 .mmu_type = MMU_TYPE_R4000,
608 },
609 {
610 .name = "5KEc",
611 .CP0_PRid = 0x00018900,
612 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
613 (MMU_TYPE_R4000 << CP0C0_MT),
614 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
615 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
616 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
617 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
618 .CP0_Config2 = MIPS_CONFIG2,
619 .CP0_Config3 = MIPS_CONFIG3,
620 .CP0_LLAddr_rw_bitmask = 0,
621 .CP0_LLAddr_shift = 4,
622 .SYNCI_Step = 32,
623 .CCRes = 2,
624 .CP0_Status_rw_bitmask = 0x12F8FFFF,
625 .SEGBITS = 42,
626 .PABITS = 36,
627 .insn_flags = CPU_MIPS64R2,
628 .mmu_type = MMU_TYPE_R4000,
629 },
630 {
631 .name = "5KEf",
632 .CP0_PRid = 0x00018900,
633 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
634 (MMU_TYPE_R4000 << CP0C0_MT),
635 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
636 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
637 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
638 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
639 .CP0_Config2 = MIPS_CONFIG2,
640 .CP0_Config3 = MIPS_CONFIG3,
641 .CP0_LLAddr_rw_bitmask = 0,
642 .CP0_LLAddr_shift = 4,
643 .SYNCI_Step = 32,
644 .CCRes = 2,
645 .CP0_Status_rw_bitmask = 0x36F8FFFF,
646 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
647 (1 << FCR0_D) | (1 << FCR0_S) |
648 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
649 .SEGBITS = 42,
650 .PABITS = 36,
651 .insn_flags = CPU_MIPS64R2,
652 .mmu_type = MMU_TYPE_R4000,
653 },
654 {
655 /* A generic CPU supporting MIPS64 Release 6 ISA.
656 FIXME: Support IEEE 754-2008 FP.
657 Eventually this should be replaced by a real CPU model. */
658 .name = "MIPS64R6-generic",
659 .CP0_PRid = 0x00010000,
660 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
661 (MMU_TYPE_R4000 << CP0C0_MT),
662 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
663 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
664 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
665 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
666 .CP0_Config2 = MIPS_CONFIG2,
667 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
668 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
669 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
670 (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
671 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
672 (0xfc << CP0C4_KScrExist),
673 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
674 (1 << CP0C5_LLB),
675 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
676 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
677 .CP0_LLAddr_rw_bitmask = 0,
678 .CP0_LLAddr_shift = 0,
679 .SYNCI_Step = 32,
680 .CCRes = 2,
681 .CP0_Status_rw_bitmask = 0x30D8FFFF,
682 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
683 (1U << CP0PG_RIE),
684 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
685 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
686 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
687 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
688 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
689 .SEGBITS = 48,
690 .PABITS = 48,
691 .insn_flags = CPU_MIPS64R6 | ASE_MSA,
692 .mmu_type = MMU_TYPE_R4000,
693 },
694 {
695 .name = "Loongson-2E",
696 .CP0_PRid = 0x6302,
697 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
698 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
699 (0x1<<5) | (0x1<<4) | (0x1<<1),
700 /* Note: Config1 is only used internally,
701 Loongson-2E has only Config0. */
702 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
703 .SYNCI_Step = 16,
704 .CCRes = 2,
705 .CP0_Status_rw_bitmask = 0x35D0FFFF,
706 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
707 .SEGBITS = 40,
708 .PABITS = 40,
709 .insn_flags = CPU_LOONGSON2E,
710 .mmu_type = MMU_TYPE_R4000,
711 },
712 {
713 .name = "Loongson-2F",
714 .CP0_PRid = 0x6303,
715 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
716 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
717 (0x1<<5) | (0x1<<4) | (0x1<<1),
718 /* Note: Config1 is only used internally,
719 Loongson-2F has only Config0. */
720 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
721 .SYNCI_Step = 16,
722 .CCRes = 2,
723 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
724 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
725 .SEGBITS = 40,
726 .PABITS = 40,
727 .insn_flags = CPU_LOONGSON2F,
728 .mmu_type = MMU_TYPE_R4000,
729 },
730 {
731 /* A generic CPU providing MIPS64 ASE DSP 2 features.
732 FIXME: Eventually this should be replaced by a real CPU model. */
733 .name = "mips64dspr2",
734 .CP0_PRid = 0x00010000,
735 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
736 (MMU_TYPE_R4000 << CP0C0_MT),
737 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
738 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
739 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
740 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
741 .CP0_Config2 = MIPS_CONFIG2,
742 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
743 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
744 .CP0_LLAddr_rw_bitmask = 0,
745 .CP0_LLAddr_shift = 0,
746 .SYNCI_Step = 32,
747 .CCRes = 2,
748 .CP0_Status_rw_bitmask = 0x37FBFFFF,
749 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
750 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
751 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
752 .SEGBITS = 42,
753 .PABITS = 36,
754 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
755 .mmu_type = MMU_TYPE_R4000,
756 },
757
758 #endif
759 };
760
761 static const mips_def_t *cpu_mips_find_by_name (const char *name)
762 {
763 int i;
764
765 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
766 if (strcasecmp(name, mips_defs[i].name) == 0) {
767 return &mips_defs[i];
768 }
769 }
770 return NULL;
771 }
772
773 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
774 {
775 int i;
776
777 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
778 (*cpu_fprintf)(f, "MIPS '%s'\n",
779 mips_defs[i].name);
780 }
781 }
782
783 #ifndef CONFIG_USER_ONLY
784 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
785 {
786 env->tlb->nb_tlb = 1;
787 env->tlb->map_address = &no_mmu_map_address;
788 }
789
790 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
791 {
792 env->tlb->nb_tlb = 1;
793 env->tlb->map_address = &fixed_mmu_map_address;
794 }
795
796 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
797 {
798 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
799 env->tlb->map_address = &r4k_map_address;
800 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
801 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
802 env->tlb->helper_tlbp = r4k_helper_tlbp;
803 env->tlb->helper_tlbr = r4k_helper_tlbr;
804 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
805 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
806 }
807
808 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
809 {
810 MIPSCPU *cpu = mips_env_get_cpu(env);
811
812 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
813
814 switch (def->mmu_type) {
815 case MMU_TYPE_NONE:
816 no_mmu_init(env, def);
817 break;
818 case MMU_TYPE_R4000:
819 r4k_mmu_init(env, def);
820 break;
821 case MMU_TYPE_FMT:
822 fixed_mmu_init(env, def);
823 break;
824 case MMU_TYPE_R3000:
825 case MMU_TYPE_R6000:
826 case MMU_TYPE_R8000:
827 default:
828 cpu_abort(CPU(cpu), "MMU type not supported\n");
829 }
830 }
831 #endif /* CONFIG_USER_ONLY */
832
833 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
834 {
835 int i;
836
837 for (i = 0; i < MIPS_FPU_MAX; i++)
838 env->fpus[i].fcr0 = def->CP1_fcr0;
839
840 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
841 }
842
843 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
844 {
845 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
846
847 /* MVPConf1 implemented, TLB sharable, no gating storage support,
848 programmable cache partitioning implemented, number of allocatable
849 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
850 implemented, 5 TCs implemented. */
851 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
852 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
853 // TODO: actually do 2 VPEs.
854 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
855 // (0x04 << CP0MVPC0_PTC);
856 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
857 (0x00 << CP0MVPC0_PTC);
858 #if !defined(CONFIG_USER_ONLY)
859 /* Usermode has no TLB support */
860 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
861 #endif
862
863 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
864 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
865 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
866 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
867 (0x1 << CP0MVPC1_PCP1);
868 }
869
870 static void msa_reset(CPUMIPSState *env)
871 {
872 #ifdef CONFIG_USER_ONLY
873 /* MSA access enabled */
874 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
875 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
876 #endif
877
878 /* MSA CSR:
879 - non-signaling floating point exception mode off (NX bit is 0)
880 - Cause, Enables, and Flags are all 0
881 - round to nearest / ties to even (RM bits are 0) */
882 env->active_tc.msacsr = 0;
883
884 restore_msa_fp_status(env);
885
886 /* tininess detected after rounding.*/
887 set_float_detect_tininess(float_tininess_after_rounding,
888 &env->active_tc.msa_fp_status);
889
890 /* clear float_status exception flags */
891 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
892
893 /* clear float_status nan mode */
894 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
895 }