cpu: Factor out cpu_generic_init()
[qemu.git] / target-openrisc / cpu.c
1 /*
2 * QEMU OpenRISC CPU
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "qemu-common.h"
22
23 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
24 {
25 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
26
27 cpu->env.pc = value;
28 }
29
30 static bool openrisc_cpu_has_work(CPUState *cs)
31 {
32 return cs->interrupt_request & (CPU_INTERRUPT_HARD |
33 CPU_INTERRUPT_TIMER);
34 }
35
36 /* CPUClass::reset() */
37 static void openrisc_cpu_reset(CPUState *s)
38 {
39 OpenRISCCPU *cpu = OPENRISC_CPU(s);
40 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
41
42 occ->parent_reset(s);
43
44 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
45
46 tlb_flush(&cpu->env, 1);
47 /*tb_flush(&cpu->env); FIXME: Do we need it? */
48
49 cpu->env.pc = 0x100;
50 cpu->env.sr = SR_FO | SR_SM;
51 cpu->env.exception_index = -1;
52
53 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
54 cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
55 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
56 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
57
58 #ifndef CONFIG_USER_ONLY
59 cpu->env.picmr = 0x00000000;
60 cpu->env.picsr = 0x00000000;
61
62 cpu->env.ttmr = 0x00000000;
63 cpu->env.ttcr = 0x00000000;
64 #endif
65 }
66
67 static inline void set_feature(OpenRISCCPU *cpu, int feature)
68 {
69 cpu->feature |= feature;
70 cpu->env.cpucfgr = cpu->feature;
71 }
72
73 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
74 {
75 CPUState *cs = CPU(dev);
76 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
77
78 qemu_init_vcpu(cs);
79 cpu_reset(cs);
80
81 occ->parent_realize(dev, errp);
82 }
83
84 static void openrisc_cpu_initfn(Object *obj)
85 {
86 CPUState *cs = CPU(obj);
87 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
88 static int inited;
89
90 cs->env_ptr = &cpu->env;
91 cpu_exec_init(&cpu->env);
92
93 #ifndef CONFIG_USER_ONLY
94 cpu_openrisc_mmu_init(cpu);
95 #endif
96
97 if (tcg_enabled() && !inited) {
98 inited = 1;
99 openrisc_translate_init();
100 }
101 }
102
103 /* CPU models */
104
105 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
106 {
107 ObjectClass *oc;
108 char *typename;
109
110 if (cpu_model == NULL) {
111 return NULL;
112 }
113
114 typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
115 oc = object_class_by_name(typename);
116 g_free(typename);
117 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
118 object_class_is_abstract(oc))) {
119 return NULL;
120 }
121 return oc;
122 }
123
124 static void or1200_initfn(Object *obj)
125 {
126 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
127
128 set_feature(cpu, OPENRISC_FEATURE_OB32S);
129 set_feature(cpu, OPENRISC_FEATURE_OF32S);
130 }
131
132 static void openrisc_any_initfn(Object *obj)
133 {
134 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
135
136 set_feature(cpu, OPENRISC_FEATURE_OB32S);
137 }
138
139 typedef struct OpenRISCCPUInfo {
140 const char *name;
141 void (*initfn)(Object *obj);
142 } OpenRISCCPUInfo;
143
144 static const OpenRISCCPUInfo openrisc_cpus[] = {
145 { .name = "or1200", .initfn = or1200_initfn },
146 { .name = "any", .initfn = openrisc_any_initfn },
147 };
148
149 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
150 {
151 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
152 CPUClass *cc = CPU_CLASS(occ);
153 DeviceClass *dc = DEVICE_CLASS(oc);
154
155 occ->parent_realize = dc->realize;
156 dc->realize = openrisc_cpu_realizefn;
157
158 occ->parent_reset = cc->reset;
159 cc->reset = openrisc_cpu_reset;
160
161 cc->class_by_name = openrisc_cpu_class_by_name;
162 cc->has_work = openrisc_cpu_has_work;
163 cc->do_interrupt = openrisc_cpu_do_interrupt;
164 cc->dump_state = openrisc_cpu_dump_state;
165 cc->set_pc = openrisc_cpu_set_pc;
166 cc->gdb_read_register = openrisc_cpu_gdb_read_register;
167 cc->gdb_write_register = openrisc_cpu_gdb_write_register;
168 #ifndef CONFIG_USER_ONLY
169 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
170 dc->vmsd = &vmstate_openrisc_cpu;
171 #endif
172 cc->gdb_num_core_regs = 32 + 3;
173 }
174
175 static void cpu_register(const OpenRISCCPUInfo *info)
176 {
177 TypeInfo type_info = {
178 .parent = TYPE_OPENRISC_CPU,
179 .instance_size = sizeof(OpenRISCCPU),
180 .instance_init = info->initfn,
181 .class_size = sizeof(OpenRISCCPUClass),
182 };
183
184 type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
185 type_register(&type_info);
186 g_free((void *)type_info.name);
187 }
188
189 static const TypeInfo openrisc_cpu_type_info = {
190 .name = TYPE_OPENRISC_CPU,
191 .parent = TYPE_CPU,
192 .instance_size = sizeof(OpenRISCCPU),
193 .instance_init = openrisc_cpu_initfn,
194 .abstract = true,
195 .class_size = sizeof(OpenRISCCPUClass),
196 .class_init = openrisc_cpu_class_init,
197 };
198
199 static void openrisc_cpu_register_types(void)
200 {
201 int i;
202
203 type_register_static(&openrisc_cpu_type_info);
204 for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
205 cpu_register(&openrisc_cpus[i]);
206 }
207 }
208
209 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
210 {
211 return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
212 }
213
214 /* Sort alphabetically by type name, except for "any". */
215 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
216 {
217 ObjectClass *class_a = (ObjectClass *)a;
218 ObjectClass *class_b = (ObjectClass *)b;
219 const char *name_a, *name_b;
220
221 name_a = object_class_get_name(class_a);
222 name_b = object_class_get_name(class_b);
223 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
224 return 1;
225 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
226 return -1;
227 } else {
228 return strcmp(name_a, name_b);
229 }
230 }
231
232 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
233 {
234 ObjectClass *oc = data;
235 CPUListState *s = user_data;
236 const char *typename;
237 char *name;
238
239 typename = object_class_get_name(oc);
240 name = g_strndup(typename,
241 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
242 (*s->cpu_fprintf)(s->file, " %s\n",
243 name);
244 g_free(name);
245 }
246
247 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
248 {
249 CPUListState s = {
250 .file = f,
251 .cpu_fprintf = cpu_fprintf,
252 };
253 GSList *list;
254
255 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
256 list = g_slist_sort(list, openrisc_cpu_list_compare);
257 (*cpu_fprintf)(f, "Available CPUs:\n");
258 g_slist_foreach(list, openrisc_cpu_list_entry, &s);
259 g_slist_free(list);
260 }
261
262 type_init(openrisc_cpu_register_types)