vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-openrisc / cpu.c
1 /*
2 * QEMU OpenRISC CPU
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "qemu-common.h"
24 #include "exec/exec-all.h"
25
26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
27 {
28 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
29
30 cpu->env.pc = value;
31 }
32
33 static bool openrisc_cpu_has_work(CPUState *cs)
34 {
35 return cs->interrupt_request & (CPU_INTERRUPT_HARD |
36 CPU_INTERRUPT_TIMER);
37 }
38
39 /* CPUClass::reset() */
40 static void openrisc_cpu_reset(CPUState *s)
41 {
42 OpenRISCCPU *cpu = OPENRISC_CPU(s);
43 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
44
45 occ->parent_reset(s);
46
47 #ifndef CONFIG_USER_ONLY
48 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb));
49 #else
50 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
51 #endif
52
53 tlb_flush(s, 1);
54 /*tb_flush(&cpu->env); FIXME: Do we need it? */
55
56 cpu->env.pc = 0x100;
57 cpu->env.sr = SR_FO | SR_SM;
58 s->exception_index = -1;
59
60 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
61 cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
62 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
63 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
64
65 #ifndef CONFIG_USER_ONLY
66 cpu->env.picmr = 0x00000000;
67 cpu->env.picsr = 0x00000000;
68
69 cpu->env.ttmr = 0x00000000;
70 cpu->env.ttcr = 0x00000000;
71 #endif
72 }
73
74 static inline void set_feature(OpenRISCCPU *cpu, int feature)
75 {
76 cpu->feature |= feature;
77 cpu->env.cpucfgr = cpu->feature;
78 }
79
80 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
81 {
82 CPUState *cs = CPU(dev);
83 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
84
85 qemu_init_vcpu(cs);
86 cpu_reset(cs);
87
88 occ->parent_realize(dev, errp);
89 }
90
91 static void openrisc_cpu_initfn(Object *obj)
92 {
93 CPUState *cs = CPU(obj);
94 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
95 static int inited;
96
97 cs->env_ptr = &cpu->env;
98 cpu_exec_init(cs, &error_abort);
99
100 #ifndef CONFIG_USER_ONLY
101 cpu_openrisc_mmu_init(cpu);
102 #endif
103
104 if (tcg_enabled() && !inited) {
105 inited = 1;
106 openrisc_translate_init();
107 }
108 }
109
110 /* CPU models */
111
112 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
113 {
114 ObjectClass *oc;
115 char *typename;
116
117 if (cpu_model == NULL) {
118 return NULL;
119 }
120
121 typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
122 oc = object_class_by_name(typename);
123 g_free(typename);
124 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
125 object_class_is_abstract(oc))) {
126 return NULL;
127 }
128 return oc;
129 }
130
131 static void or1200_initfn(Object *obj)
132 {
133 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
134
135 set_feature(cpu, OPENRISC_FEATURE_OB32S);
136 set_feature(cpu, OPENRISC_FEATURE_OF32S);
137 }
138
139 static void openrisc_any_initfn(Object *obj)
140 {
141 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
142
143 set_feature(cpu, OPENRISC_FEATURE_OB32S);
144 }
145
146 typedef struct OpenRISCCPUInfo {
147 const char *name;
148 void (*initfn)(Object *obj);
149 } OpenRISCCPUInfo;
150
151 static const OpenRISCCPUInfo openrisc_cpus[] = {
152 { .name = "or1200", .initfn = or1200_initfn },
153 { .name = "any", .initfn = openrisc_any_initfn },
154 };
155
156 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
157 {
158 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
159 CPUClass *cc = CPU_CLASS(occ);
160 DeviceClass *dc = DEVICE_CLASS(oc);
161
162 occ->parent_realize = dc->realize;
163 dc->realize = openrisc_cpu_realizefn;
164
165 occ->parent_reset = cc->reset;
166 cc->reset = openrisc_cpu_reset;
167
168 cc->class_by_name = openrisc_cpu_class_by_name;
169 cc->has_work = openrisc_cpu_has_work;
170 cc->do_interrupt = openrisc_cpu_do_interrupt;
171 cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
172 cc->dump_state = openrisc_cpu_dump_state;
173 cc->set_pc = openrisc_cpu_set_pc;
174 cc->gdb_read_register = openrisc_cpu_gdb_read_register;
175 cc->gdb_write_register = openrisc_cpu_gdb_write_register;
176 #ifdef CONFIG_USER_ONLY
177 cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
178 #else
179 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
180 dc->vmsd = &vmstate_openrisc_cpu;
181 #endif
182 cc->gdb_num_core_regs = 32 + 3;
183
184 /*
185 * Reason: openrisc_cpu_initfn() calls cpu_exec_init(), which saves
186 * the object in cpus -> dangling pointer after final
187 * object_unref().
188 */
189 dc->cannot_destroy_with_object_finalize_yet = true;
190 }
191
192 static void cpu_register(const OpenRISCCPUInfo *info)
193 {
194 TypeInfo type_info = {
195 .parent = TYPE_OPENRISC_CPU,
196 .instance_size = sizeof(OpenRISCCPU),
197 .instance_init = info->initfn,
198 .class_size = sizeof(OpenRISCCPUClass),
199 };
200
201 type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
202 type_register(&type_info);
203 g_free((void *)type_info.name);
204 }
205
206 static const TypeInfo openrisc_cpu_type_info = {
207 .name = TYPE_OPENRISC_CPU,
208 .parent = TYPE_CPU,
209 .instance_size = sizeof(OpenRISCCPU),
210 .instance_init = openrisc_cpu_initfn,
211 .abstract = true,
212 .class_size = sizeof(OpenRISCCPUClass),
213 .class_init = openrisc_cpu_class_init,
214 };
215
216 static void openrisc_cpu_register_types(void)
217 {
218 int i;
219
220 type_register_static(&openrisc_cpu_type_info);
221 for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
222 cpu_register(&openrisc_cpus[i]);
223 }
224 }
225
226 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
227 {
228 return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
229 }
230
231 /* Sort alphabetically by type name, except for "any". */
232 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
233 {
234 ObjectClass *class_a = (ObjectClass *)a;
235 ObjectClass *class_b = (ObjectClass *)b;
236 const char *name_a, *name_b;
237
238 name_a = object_class_get_name(class_a);
239 name_b = object_class_get_name(class_b);
240 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
241 return 1;
242 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
243 return -1;
244 } else {
245 return strcmp(name_a, name_b);
246 }
247 }
248
249 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
250 {
251 ObjectClass *oc = data;
252 CPUListState *s = user_data;
253 const char *typename;
254 char *name;
255
256 typename = object_class_get_name(oc);
257 name = g_strndup(typename,
258 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
259 (*s->cpu_fprintf)(s->file, " %s\n",
260 name);
261 g_free(name);
262 }
263
264 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
265 {
266 CPUListState s = {
267 .file = f,
268 .cpu_fprintf = cpu_fprintf,
269 };
270 GSList *list;
271
272 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
273 list = g_slist_sort(list, openrisc_cpu_list_compare);
274 (*cpu_fprintf)(f, "Available CPUs:\n");
275 g_slist_foreach(list, openrisc_cpu_list_entry, &s);
276 g_slist_free(list);
277 }
278
279 type_init(openrisc_cpu_register_types)