vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-openrisc / interrupt.c
1 /*
2 * OpenRISC interrupt.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "qemu-common.h"
24 #include "exec/gdbstub.h"
25 #include "qemu/host-utils.h"
26 #ifndef CONFIG_USER_ONLY
27 #include "hw/loader.h"
28 #endif
29
30 void openrisc_cpu_do_interrupt(CPUState *cs)
31 {
32 #ifndef CONFIG_USER_ONLY
33 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
34 CPUOpenRISCState *env = &cpu->env;
35
36 env->epcr = env->pc;
37 if (env->flags & D_FLAG) {
38 env->flags &= ~D_FLAG;
39 env->sr |= SR_DSX;
40 env->epcr -= 4;
41 }
42 if (cs->exception_index == EXCP_SYSCALL) {
43 env->epcr += 4;
44 }
45
46 /* For machine-state changed between user-mode and supervisor mode,
47 we need flush TLB when we enter&exit EXCP. */
48 tlb_flush(cs, 1);
49
50 env->esr = env->sr;
51 env->sr &= ~SR_DME;
52 env->sr &= ~SR_IME;
53 env->sr |= SR_SM;
54 env->sr &= ~SR_IEE;
55 env->sr &= ~SR_TEE;
56 env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
57 env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
58
59 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
60 env->pc = (cs->exception_index << 8);
61 } else {
62 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
63 }
64 #endif
65
66 cs->exception_index = -1;
67 }
68
69 bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
70 {
71 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
72 CPUOpenRISCState *env = &cpu->env;
73 int idx = -1;
74
75 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) {
76 idx = EXCP_INT;
77 }
78 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) {
79 idx = EXCP_TICK;
80 }
81 if (idx >= 0) {
82 cs->exception_index = idx;
83 openrisc_cpu_do_interrupt(cs);
84 return true;
85 }
86 return false;
87 }