vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-openrisc / translate.c
1 /*
2 * OpenRISC translation
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "disas/disas.h"
25 #include "tcg-op.h"
26 #include "qemu-common.h"
27 #include "qemu/log.h"
28 #include "qemu/bitops.h"
29 #include "exec/cpu_ldst.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33
34 #include "trace-tcg.h"
35 #include "exec/log.h"
36
37
38 #define OPENRISC_DISAS
39
40 #ifdef OPENRISC_DISAS
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
42 #else
43 # define LOG_DIS(...) do { } while (0)
44 #endif
45
46 typedef struct DisasContext {
47 TranslationBlock *tb;
48 target_ulong pc, ppc, npc;
49 uint32_t tb_flags, synced_flags, flags;
50 uint32_t is_jmp;
51 uint32_t mem_idx;
52 int singlestep_enabled;
53 uint32_t delayed_branch;
54 } DisasContext;
55
56 static TCGv_env cpu_env;
57 static TCGv cpu_sr;
58 static TCGv cpu_R[32];
59 static TCGv cpu_pc;
60 static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
61 static TCGv cpu_npc;
62 static TCGv cpu_ppc;
63 static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
64 static TCGv_i32 fpcsr;
65 static TCGv machi, maclo;
66 static TCGv fpmaddhi, fpmaddlo;
67 static TCGv_i32 env_flags;
68 #include "exec/gen-icount.h"
69
70 void openrisc_translate_init(void)
71 {
72 static const char * const regnames[] = {
73 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
74 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
75 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
76 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
77 };
78 int i;
79
80 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
81 cpu_sr = tcg_global_mem_new(cpu_env,
82 offsetof(CPUOpenRISCState, sr), "sr");
83 env_flags = tcg_global_mem_new_i32(cpu_env,
84 offsetof(CPUOpenRISCState, flags),
85 "flags");
86 cpu_pc = tcg_global_mem_new(cpu_env,
87 offsetof(CPUOpenRISCState, pc), "pc");
88 cpu_npc = tcg_global_mem_new(cpu_env,
89 offsetof(CPUOpenRISCState, npc), "npc");
90 cpu_ppc = tcg_global_mem_new(cpu_env,
91 offsetof(CPUOpenRISCState, ppc), "ppc");
92 jmp_pc = tcg_global_mem_new(cpu_env,
93 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
94 env_btaken = tcg_global_mem_new_i32(cpu_env,
95 offsetof(CPUOpenRISCState, btaken),
96 "btaken");
97 fpcsr = tcg_global_mem_new_i32(cpu_env,
98 offsetof(CPUOpenRISCState, fpcsr),
99 "fpcsr");
100 machi = tcg_global_mem_new(cpu_env,
101 offsetof(CPUOpenRISCState, machi),
102 "machi");
103 maclo = tcg_global_mem_new(cpu_env,
104 offsetof(CPUOpenRISCState, maclo),
105 "maclo");
106 fpmaddhi = tcg_global_mem_new(cpu_env,
107 offsetof(CPUOpenRISCState, fpmaddhi),
108 "fpmaddhi");
109 fpmaddlo = tcg_global_mem_new(cpu_env,
110 offsetof(CPUOpenRISCState, fpmaddlo),
111 "fpmaddlo");
112 for (i = 0; i < 32; i++) {
113 cpu_R[i] = tcg_global_mem_new(cpu_env,
114 offsetof(CPUOpenRISCState, gpr[i]),
115 regnames[i]);
116 }
117 }
118
119 /* Writeback SR_F translation space to execution space. */
120 static inline void wb_SR_F(void)
121 {
122 TCGLabel *label = gen_new_label();
123 tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
124 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
125 tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
126 gen_set_label(label);
127 }
128
129 static inline int zero_extend(unsigned int val, int width)
130 {
131 return val & ((1 << width) - 1);
132 }
133
134 static inline int sign_extend(unsigned int val, int width)
135 {
136 int sval;
137
138 /* LSL */
139 val <<= TARGET_LONG_BITS - width;
140 sval = val;
141 /* ASR. */
142 sval >>= TARGET_LONG_BITS - width;
143 return sval;
144 }
145
146 static inline void gen_sync_flags(DisasContext *dc)
147 {
148 /* Sync the tb dependent flag between translate and runtime. */
149 if (dc->tb_flags != dc->synced_flags) {
150 tcg_gen_movi_tl(env_flags, dc->tb_flags);
151 dc->synced_flags = dc->tb_flags;
152 }
153 }
154
155 static void gen_exception(DisasContext *dc, unsigned int excp)
156 {
157 TCGv_i32 tmp = tcg_const_i32(excp);
158 gen_helper_exception(cpu_env, tmp);
159 tcg_temp_free_i32(tmp);
160 }
161
162 static void gen_illegal_exception(DisasContext *dc)
163 {
164 tcg_gen_movi_tl(cpu_pc, dc->pc);
165 gen_exception(dc, EXCP_ILLEGAL);
166 dc->is_jmp = DISAS_UPDATE;
167 }
168
169 /* not used yet, open it when we need or64. */
170 /*#ifdef TARGET_OPENRISC64
171 static void check_ob64s(DisasContext *dc)
172 {
173 if (!(dc->flags & CPUCFGR_OB64S)) {
174 gen_illegal_exception(dc);
175 }
176 }
177
178 static void check_of64s(DisasContext *dc)
179 {
180 if (!(dc->flags & CPUCFGR_OF64S)) {
181 gen_illegal_exception(dc);
182 }
183 }
184
185 static void check_ov64s(DisasContext *dc)
186 {
187 if (!(dc->flags & CPUCFGR_OV64S)) {
188 gen_illegal_exception(dc);
189 }
190 }
191 #endif*/
192
193 static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
194 {
195 if (unlikely(dc->singlestep_enabled)) {
196 return false;
197 }
198
199 #ifndef CONFIG_USER_ONLY
200 return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
201 #else
202 return true;
203 #endif
204 }
205
206 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
207 {
208 if (use_goto_tb(dc, dest)) {
209 tcg_gen_movi_tl(cpu_pc, dest);
210 tcg_gen_goto_tb(n);
211 tcg_gen_exit_tb((uintptr_t)dc->tb + n);
212 } else {
213 tcg_gen_movi_tl(cpu_pc, dest);
214 if (dc->singlestep_enabled) {
215 gen_exception(dc, EXCP_DEBUG);
216 }
217 tcg_gen_exit_tb(0);
218 }
219 }
220
221 static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
222 {
223 target_ulong tmp_pc;
224 /* N26, 26bits imm */
225 tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
226
227 switch (op0) {
228 case 0x00: /* l.j */
229 tcg_gen_movi_tl(jmp_pc, tmp_pc);
230 break;
231 case 0x01: /* l.jal */
232 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
233 tcg_gen_movi_tl(jmp_pc, tmp_pc);
234 break;
235 case 0x03: /* l.bnf */
236 case 0x04: /* l.bf */
237 {
238 TCGLabel *lab = gen_new_label();
239 TCGv sr_f = tcg_temp_new();
240 tcg_gen_movi_tl(jmp_pc, dc->pc+8);
241 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
242 tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
243 sr_f, SR_F, lab);
244 tcg_gen_movi_tl(jmp_pc, tmp_pc);
245 gen_set_label(lab);
246 tcg_temp_free(sr_f);
247 }
248 break;
249 case 0x11: /* l.jr */
250 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
251 break;
252 case 0x12: /* l.jalr */
253 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
254 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
255 break;
256 default:
257 gen_illegal_exception(dc);
258 break;
259 }
260
261 dc->delayed_branch = 2;
262 dc->tb_flags |= D_FLAG;
263 gen_sync_flags(dc);
264 }
265
266
267 static void dec_calc(DisasContext *dc, uint32_t insn)
268 {
269 uint32_t op0, op1, op2;
270 uint32_t ra, rb, rd;
271 op0 = extract32(insn, 0, 4);
272 op1 = extract32(insn, 8, 2);
273 op2 = extract32(insn, 6, 2);
274 ra = extract32(insn, 16, 5);
275 rb = extract32(insn, 11, 5);
276 rd = extract32(insn, 21, 5);
277
278 switch (op0) {
279 case 0x0000:
280 switch (op1) {
281 case 0x00: /* l.add */
282 LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
283 {
284 TCGLabel *lab = gen_new_label();
285 TCGv_i64 ta = tcg_temp_new_i64();
286 TCGv_i64 tb = tcg_temp_new_i64();
287 TCGv_i64 td = tcg_temp_local_new_i64();
288 TCGv_i32 res = tcg_temp_local_new_i32();
289 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
290 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
291 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
292 tcg_gen_add_i64(td, ta, tb);
293 tcg_gen_extrl_i64_i32(res, td);
294 tcg_gen_shri_i64(td, td, 31);
295 tcg_gen_andi_i64(td, td, 0x3);
296 /* Jump to lab when no overflow. */
297 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
298 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
299 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
300 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
301 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
302 gen_exception(dc, EXCP_RANGE);
303 gen_set_label(lab);
304 tcg_gen_mov_i32(cpu_R[rd], res);
305 tcg_temp_free_i64(ta);
306 tcg_temp_free_i64(tb);
307 tcg_temp_free_i64(td);
308 tcg_temp_free_i32(res);
309 tcg_temp_free_i32(sr_ove);
310 }
311 break;
312 default:
313 gen_illegal_exception(dc);
314 break;
315 }
316 break;
317
318 case 0x0001: /* l.addc */
319 switch (op1) {
320 case 0x00:
321 LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
322 {
323 TCGLabel *lab = gen_new_label();
324 TCGv_i64 ta = tcg_temp_new_i64();
325 TCGv_i64 tb = tcg_temp_new_i64();
326 TCGv_i64 tcy = tcg_temp_local_new_i64();
327 TCGv_i64 td = tcg_temp_local_new_i64();
328 TCGv_i32 res = tcg_temp_local_new_i32();
329 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
330 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
331 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
332 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
333 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
334 tcg_gen_extu_i32_i64(tcy, sr_cy);
335 tcg_gen_shri_i64(tcy, tcy, 10);
336 tcg_gen_add_i64(td, ta, tb);
337 tcg_gen_add_i64(td, td, tcy);
338 tcg_gen_extrl_i64_i32(res, td);
339 tcg_gen_shri_i64(td, td, 32);
340 tcg_gen_andi_i64(td, td, 0x3);
341 /* Jump to lab when no overflow. */
342 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
343 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
344 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
345 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
346 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
347 gen_exception(dc, EXCP_RANGE);
348 gen_set_label(lab);
349 tcg_gen_mov_i32(cpu_R[rd], res);
350 tcg_temp_free_i64(ta);
351 tcg_temp_free_i64(tb);
352 tcg_temp_free_i64(tcy);
353 tcg_temp_free_i64(td);
354 tcg_temp_free_i32(res);
355 tcg_temp_free_i32(sr_cy);
356 tcg_temp_free_i32(sr_ove);
357 }
358 break;
359 default:
360 gen_illegal_exception(dc);
361 break;
362 }
363 break;
364
365 case 0x0002: /* l.sub */
366 switch (op1) {
367 case 0x00:
368 LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
369 {
370 TCGLabel *lab = gen_new_label();
371 TCGv_i64 ta = tcg_temp_new_i64();
372 TCGv_i64 tb = tcg_temp_new_i64();
373 TCGv_i64 td = tcg_temp_local_new_i64();
374 TCGv_i32 res = tcg_temp_local_new_i32();
375 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
376
377 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
378 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
379 tcg_gen_sub_i64(td, ta, tb);
380 tcg_gen_extrl_i64_i32(res, td);
381 tcg_gen_shri_i64(td, td, 31);
382 tcg_gen_andi_i64(td, td, 0x3);
383 /* Jump to lab when no overflow. */
384 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
385 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
386 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
387 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
388 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
389 gen_exception(dc, EXCP_RANGE);
390 gen_set_label(lab);
391 tcg_gen_mov_i32(cpu_R[rd], res);
392 tcg_temp_free_i64(ta);
393 tcg_temp_free_i64(tb);
394 tcg_temp_free_i64(td);
395 tcg_temp_free_i32(res);
396 tcg_temp_free_i32(sr_ove);
397 }
398 break;
399 default:
400 gen_illegal_exception(dc);
401 break;
402 }
403 break;
404
405 case 0x0003: /* l.and */
406 switch (op1) {
407 case 0x00:
408 LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb);
409 tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
410 break;
411 default:
412 gen_illegal_exception(dc);
413 break;
414 }
415 break;
416
417 case 0x0004: /* l.or */
418 switch (op1) {
419 case 0x00:
420 LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb);
421 tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
422 break;
423 default:
424 gen_illegal_exception(dc);
425 break;
426 }
427 break;
428
429 case 0x0005:
430 switch (op1) {
431 case 0x00: /* l.xor */
432 LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb);
433 tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
434 break;
435 default:
436 gen_illegal_exception(dc);
437 break;
438 }
439 break;
440
441 case 0x0006:
442 switch (op1) {
443 case 0x03: /* l.mul */
444 LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb);
445 if (ra != 0 && rb != 0) {
446 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
447 } else {
448 tcg_gen_movi_tl(cpu_R[rd], 0x0);
449 }
450 break;
451 default:
452 gen_illegal_exception(dc);
453 break;
454 }
455 break;
456
457 case 0x0009:
458 switch (op1) {
459 case 0x03: /* l.div */
460 LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
461 {
462 TCGLabel *lab0 = gen_new_label();
463 TCGLabel *lab1 = gen_new_label();
464 TCGLabel *lab2 = gen_new_label();
465 TCGLabel *lab3 = gen_new_label();
466 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
467 if (rb == 0) {
468 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
469 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
470 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
471 gen_exception(dc, EXCP_RANGE);
472 gen_set_label(lab0);
473 } else {
474 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb],
475 0x00000000, lab1);
476 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra],
477 0x80000000, lab2);
478 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
479 0xffffffff, lab2);
480 gen_set_label(lab1);
481 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
482 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
483 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3);
484 gen_exception(dc, EXCP_RANGE);
485 gen_set_label(lab2);
486 tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
487 gen_set_label(lab3);
488 }
489 tcg_temp_free_i32(sr_ove);
490 }
491 break;
492
493 default:
494 gen_illegal_exception(dc);
495 break;
496 }
497 break;
498
499 case 0x000a:
500 switch (op1) {
501 case 0x03: /* l.divu */
502 LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
503 {
504 TCGLabel *lab0 = gen_new_label();
505 TCGLabel *lab1 = gen_new_label();
506 TCGLabel *lab2 = gen_new_label();
507 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
508 if (rb == 0) {
509 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
510 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
511 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
512 gen_exception(dc, EXCP_RANGE);
513 gen_set_label(lab0);
514 } else {
515 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
516 0x00000000, lab1);
517 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
518 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
519 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2);
520 gen_exception(dc, EXCP_RANGE);
521 gen_set_label(lab1);
522 tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
523 gen_set_label(lab2);
524 }
525 tcg_temp_free_i32(sr_ove);
526 }
527 break;
528
529 default:
530 gen_illegal_exception(dc);
531 break;
532 }
533 break;
534
535 case 0x000b:
536 switch (op1) {
537 case 0x03: /* l.mulu */
538 LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb);
539 if (rb != 0 && ra != 0) {
540 TCGv_i64 result = tcg_temp_local_new_i64();
541 TCGv_i64 tra = tcg_temp_local_new_i64();
542 TCGv_i64 trb = tcg_temp_local_new_i64();
543 TCGv_i64 high = tcg_temp_new_i64();
544 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
545 TCGLabel *lab = gen_new_label();
546 /* Calculate each result. */
547 tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
548 tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
549 tcg_gen_mul_i64(result, tra, trb);
550 tcg_temp_free_i64(tra);
551 tcg_temp_free_i64(trb);
552 tcg_gen_shri_i64(high, result, TARGET_LONG_BITS);
553 /* Overflow or not. */
554 tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab);
555 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
556 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
557 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab);
558 gen_exception(dc, EXCP_RANGE);
559 gen_set_label(lab);
560 tcg_temp_free_i64(high);
561 tcg_gen_trunc_i64_tl(cpu_R[rd], result);
562 tcg_temp_free_i64(result);
563 tcg_temp_free_i32(sr_ove);
564 } else {
565 tcg_gen_movi_tl(cpu_R[rd], 0);
566 }
567 break;
568
569 default:
570 gen_illegal_exception(dc);
571 break;
572 }
573 break;
574
575 case 0x000e:
576 switch (op1) {
577 case 0x00: /* l.cmov */
578 LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
579 {
580 TCGLabel *lab = gen_new_label();
581 TCGv res = tcg_temp_local_new();
582 TCGv sr_f = tcg_temp_new();
583 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
584 tcg_gen_mov_tl(res, cpu_R[rb]);
585 tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
586 tcg_gen_mov_tl(res, cpu_R[ra]);
587 gen_set_label(lab);
588 tcg_gen_mov_tl(cpu_R[rd], res);
589 tcg_temp_free(sr_f);
590 tcg_temp_free(res);
591 }
592 break;
593
594 default:
595 gen_illegal_exception(dc);
596 break;
597 }
598 break;
599
600 case 0x000f:
601 switch (op1) {
602 case 0x00: /* l.ff1 */
603 LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
604 gen_helper_ff1(cpu_R[rd], cpu_R[ra]);
605 break;
606 case 0x01: /* l.fl1 */
607 LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
608 gen_helper_fl1(cpu_R[rd], cpu_R[ra]);
609 break;
610
611 default:
612 gen_illegal_exception(dc);
613 break;
614 }
615 break;
616
617 case 0x0008:
618 switch (op1) {
619 case 0x00:
620 switch (op2) {
621 case 0x00: /* l.sll */
622 LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb);
623 tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
624 break;
625 case 0x01: /* l.srl */
626 LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb);
627 tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
628 break;
629 case 0x02: /* l.sra */
630 LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb);
631 tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
632 break;
633 case 0x03: /* l.ror */
634 LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb);
635 tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
636 break;
637
638 default:
639 gen_illegal_exception(dc);
640 break;
641 }
642 break;
643
644 default:
645 gen_illegal_exception(dc);
646 break;
647 }
648 break;
649
650 case 0x000c:
651 switch (op1) {
652 case 0x00:
653 switch (op2) {
654 case 0x00: /* l.exths */
655 LOG_DIS("l.exths r%d, r%d\n", rd, ra);
656 tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]);
657 break;
658 case 0x01: /* l.extbs */
659 LOG_DIS("l.extbs r%d, r%d\n", rd, ra);
660 tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]);
661 break;
662 case 0x02: /* l.exthz */
663 LOG_DIS("l.exthz r%d, r%d\n", rd, ra);
664 tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]);
665 break;
666 case 0x03: /* l.extbz */
667 LOG_DIS("l.extbz r%d, r%d\n", rd, ra);
668 tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]);
669 break;
670
671 default:
672 gen_illegal_exception(dc);
673 break;
674 }
675 break;
676
677 default:
678 gen_illegal_exception(dc);
679 break;
680 }
681 break;
682
683 case 0x000d:
684 switch (op1) {
685 case 0x00:
686 switch (op2) {
687 case 0x00: /* l.extws */
688 LOG_DIS("l.extws r%d, r%d\n", rd, ra);
689 tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]);
690 break;
691 case 0x01: /* l.extwz */
692 LOG_DIS("l.extwz r%d, r%d\n", rd, ra);
693 tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]);
694 break;
695
696 default:
697 gen_illegal_exception(dc);
698 break;
699 }
700 break;
701
702 default:
703 gen_illegal_exception(dc);
704 break;
705 }
706 break;
707
708 default:
709 gen_illegal_exception(dc);
710 break;
711 }
712 }
713
714 static void dec_misc(DisasContext *dc, uint32_t insn)
715 {
716 uint32_t op0, op1;
717 uint32_t ra, rb, rd;
718 #ifdef OPENRISC_DISAS
719 uint32_t L6, K5;
720 #endif
721 uint32_t I16, I5, I11, N26, tmp;
722 TCGMemOp mop;
723
724 op0 = extract32(insn, 26, 6);
725 op1 = extract32(insn, 24, 2);
726 ra = extract32(insn, 16, 5);
727 rb = extract32(insn, 11, 5);
728 rd = extract32(insn, 21, 5);
729 #ifdef OPENRISC_DISAS
730 L6 = extract32(insn, 5, 6);
731 K5 = extract32(insn, 0, 5);
732 #endif
733 I16 = extract32(insn, 0, 16);
734 I5 = extract32(insn, 21, 5);
735 I11 = extract32(insn, 0, 11);
736 N26 = extract32(insn, 0, 26);
737 tmp = (I5<<11) + I11;
738
739 switch (op0) {
740 case 0x00: /* l.j */
741 LOG_DIS("l.j %d\n", N26);
742 gen_jump(dc, N26, 0, op0);
743 break;
744
745 case 0x01: /* l.jal */
746 LOG_DIS("l.jal %d\n", N26);
747 gen_jump(dc, N26, 0, op0);
748 break;
749
750 case 0x03: /* l.bnf */
751 LOG_DIS("l.bnf %d\n", N26);
752 gen_jump(dc, N26, 0, op0);
753 break;
754
755 case 0x04: /* l.bf */
756 LOG_DIS("l.bf %d\n", N26);
757 gen_jump(dc, N26, 0, op0);
758 break;
759
760 case 0x05:
761 switch (op1) {
762 case 0x01: /* l.nop */
763 LOG_DIS("l.nop %d\n", I16);
764 break;
765
766 default:
767 gen_illegal_exception(dc);
768 break;
769 }
770 break;
771
772 case 0x11: /* l.jr */
773 LOG_DIS("l.jr r%d\n", rb);
774 gen_jump(dc, 0, rb, op0);
775 break;
776
777 case 0x12: /* l.jalr */
778 LOG_DIS("l.jalr r%d\n", rb);
779 gen_jump(dc, 0, rb, op0);
780 break;
781
782 case 0x13: /* l.maci */
783 LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11);
784 {
785 TCGv_i64 t1 = tcg_temp_new_i64();
786 TCGv_i64 t2 = tcg_temp_new_i64();
787 TCGv_i32 dst = tcg_temp_new_i32();
788 TCGv ttmp = tcg_const_tl(tmp);
789 tcg_gen_mul_tl(dst, cpu_R[ra], ttmp);
790 tcg_gen_ext_i32_i64(t1, dst);
791 tcg_gen_concat_i32_i64(t2, maclo, machi);
792 tcg_gen_add_i64(t2, t2, t1);
793 tcg_gen_extrl_i64_i32(maclo, t2);
794 tcg_gen_shri_i64(t2, t2, 32);
795 tcg_gen_extrl_i64_i32(machi, t2);
796 tcg_temp_free_i32(dst);
797 tcg_temp_free(ttmp);
798 tcg_temp_free_i64(t1);
799 tcg_temp_free_i64(t2);
800 }
801 break;
802
803 case 0x09: /* l.rfe */
804 LOG_DIS("l.rfe\n");
805 {
806 #if defined(CONFIG_USER_ONLY)
807 return;
808 #else
809 if (dc->mem_idx == MMU_USER_IDX) {
810 gen_illegal_exception(dc);
811 return;
812 }
813 gen_helper_rfe(cpu_env);
814 dc->is_jmp = DISAS_UPDATE;
815 #endif
816 }
817 break;
818
819 case 0x1c: /* l.cust1 */
820 LOG_DIS("l.cust1\n");
821 break;
822
823 case 0x1d: /* l.cust2 */
824 LOG_DIS("l.cust2\n");
825 break;
826
827 case 0x1e: /* l.cust3 */
828 LOG_DIS("l.cust3\n");
829 break;
830
831 case 0x1f: /* l.cust4 */
832 LOG_DIS("l.cust4\n");
833 break;
834
835 case 0x3c: /* l.cust5 */
836 LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5);
837 break;
838
839 case 0x3d: /* l.cust6 */
840 LOG_DIS("l.cust6\n");
841 break;
842
843 case 0x3e: /* l.cust7 */
844 LOG_DIS("l.cust7\n");
845 break;
846
847 case 0x3f: /* l.cust8 */
848 LOG_DIS("l.cust8\n");
849 break;
850
851 /* not used yet, open it when we need or64. */
852 /*#ifdef TARGET_OPENRISC64
853 case 0x20: l.ld
854 LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
855 check_ob64s(dc);
856 mop = MO_TEQ;
857 goto do_load;
858 #endif*/
859
860 case 0x21: /* l.lwz */
861 LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
862 mop = MO_TEUL;
863 goto do_load;
864
865 case 0x22: /* l.lws */
866 LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
867 mop = MO_TESL;
868 goto do_load;
869
870 case 0x23: /* l.lbz */
871 LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
872 mop = MO_UB;
873 goto do_load;
874
875 case 0x24: /* l.lbs */
876 LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
877 mop = MO_SB;
878 goto do_load;
879
880 case 0x25: /* l.lhz */
881 LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
882 mop = MO_TEUW;
883 goto do_load;
884
885 case 0x26: /* l.lhs */
886 LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
887 mop = MO_TESW;
888 goto do_load;
889
890 do_load:
891 {
892 TCGv t0 = tcg_temp_new();
893 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
894 tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop);
895 tcg_temp_free(t0);
896 }
897 break;
898
899 case 0x27: /* l.addi */
900 LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
901 {
902 if (I16 == 0) {
903 tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
904 } else {
905 TCGLabel *lab = gen_new_label();
906 TCGv_i64 ta = tcg_temp_new_i64();
907 TCGv_i64 td = tcg_temp_local_new_i64();
908 TCGv_i32 res = tcg_temp_local_new_i32();
909 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
910 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
911 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
912 tcg_gen_extrl_i64_i32(res, td);
913 tcg_gen_shri_i64(td, td, 32);
914 tcg_gen_andi_i64(td, td, 0x3);
915 /* Jump to lab when no overflow. */
916 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
917 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
918 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
919 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
920 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
921 gen_exception(dc, EXCP_RANGE);
922 gen_set_label(lab);
923 tcg_gen_mov_i32(cpu_R[rd], res);
924 tcg_temp_free_i64(ta);
925 tcg_temp_free_i64(td);
926 tcg_temp_free_i32(res);
927 tcg_temp_free_i32(sr_ove);
928 }
929 }
930 break;
931
932 case 0x28: /* l.addic */
933 LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
934 {
935 TCGLabel *lab = gen_new_label();
936 TCGv_i64 ta = tcg_temp_new_i64();
937 TCGv_i64 td = tcg_temp_local_new_i64();
938 TCGv_i64 tcy = tcg_temp_local_new_i64();
939 TCGv_i32 res = tcg_temp_local_new_i32();
940 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
941 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
942 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
943 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
944 tcg_gen_shri_i32(sr_cy, sr_cy, 10);
945 tcg_gen_extu_i32_i64(tcy, sr_cy);
946 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
947 tcg_gen_add_i64(td, td, tcy);
948 tcg_gen_extrl_i64_i32(res, td);
949 tcg_gen_shri_i64(td, td, 32);
950 tcg_gen_andi_i64(td, td, 0x3);
951 /* Jump to lab when no overflow. */
952 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
953 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
954 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
955 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
956 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
957 gen_exception(dc, EXCP_RANGE);
958 gen_set_label(lab);
959 tcg_gen_mov_i32(cpu_R[rd], res);
960 tcg_temp_free_i64(ta);
961 tcg_temp_free_i64(td);
962 tcg_temp_free_i64(tcy);
963 tcg_temp_free_i32(res);
964 tcg_temp_free_i32(sr_cy);
965 tcg_temp_free_i32(sr_ove);
966 }
967 break;
968
969 case 0x29: /* l.andi */
970 LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16);
971 tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
972 break;
973
974 case 0x2a: /* l.ori */
975 LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16);
976 tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
977 break;
978
979 case 0x2b: /* l.xori */
980 LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16);
981 tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16));
982 break;
983
984 case 0x2c: /* l.muli */
985 LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16);
986 if (ra != 0 && I16 != 0) {
987 TCGv_i32 im = tcg_const_i32(I16);
988 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], im);
989 tcg_temp_free_i32(im);
990 } else {
991 tcg_gen_movi_tl(cpu_R[rd], 0x0);
992 }
993 break;
994
995 case 0x2d: /* l.mfspr */
996 LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16);
997 {
998 #if defined(CONFIG_USER_ONLY)
999 return;
1000 #else
1001 TCGv_i32 ti = tcg_const_i32(I16);
1002 if (dc->mem_idx == MMU_USER_IDX) {
1003 gen_illegal_exception(dc);
1004 return;
1005 }
1006 gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti);
1007 tcg_temp_free_i32(ti);
1008 #endif
1009 }
1010 break;
1011
1012 case 0x30: /* l.mtspr */
1013 LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1014 {
1015 #if defined(CONFIG_USER_ONLY)
1016 return;
1017 #else
1018 TCGv_i32 im = tcg_const_i32(tmp);
1019 if (dc->mem_idx == MMU_USER_IDX) {
1020 gen_illegal_exception(dc);
1021 return;
1022 }
1023 gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im);
1024 tcg_temp_free_i32(im);
1025 #endif
1026 }
1027 break;
1028
1029 /* not used yet, open it when we need or64. */
1030 /*#ifdef TARGET_OPENRISC64
1031 case 0x34: l.sd
1032 LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1033 check_ob64s(dc);
1034 mop = MO_TEQ;
1035 goto do_store;
1036 #endif*/
1037
1038 case 0x35: /* l.sw */
1039 LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1040 mop = MO_TEUL;
1041 goto do_store;
1042
1043 case 0x36: /* l.sb */
1044 LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1045 mop = MO_UB;
1046 goto do_store;
1047
1048 case 0x37: /* l.sh */
1049 LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1050 mop = MO_TEUW;
1051 goto do_store;
1052
1053 do_store:
1054 {
1055 TCGv t0 = tcg_temp_new();
1056 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1057 tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop);
1058 tcg_temp_free(t0);
1059 }
1060 break;
1061
1062 default:
1063 gen_illegal_exception(dc);
1064 break;
1065 }
1066 }
1067
1068 static void dec_mac(DisasContext *dc, uint32_t insn)
1069 {
1070 uint32_t op0;
1071 uint32_t ra, rb;
1072 op0 = extract32(insn, 0, 4);
1073 ra = extract32(insn, 16, 5);
1074 rb = extract32(insn, 11, 5);
1075
1076 switch (op0) {
1077 case 0x0001: /* l.mac */
1078 LOG_DIS("l.mac r%d, r%d\n", ra, rb);
1079 {
1080 TCGv_i32 t0 = tcg_temp_new_i32();
1081 TCGv_i64 t1 = tcg_temp_new_i64();
1082 TCGv_i64 t2 = tcg_temp_new_i64();
1083 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1084 tcg_gen_ext_i32_i64(t1, t0);
1085 tcg_gen_concat_i32_i64(t2, maclo, machi);
1086 tcg_gen_add_i64(t2, t2, t1);
1087 tcg_gen_extrl_i64_i32(maclo, t2);
1088 tcg_gen_shri_i64(t2, t2, 32);
1089 tcg_gen_extrl_i64_i32(machi, t2);
1090 tcg_temp_free_i32(t0);
1091 tcg_temp_free_i64(t1);
1092 tcg_temp_free_i64(t2);
1093 }
1094 break;
1095
1096 case 0x0002: /* l.msb */
1097 LOG_DIS("l.msb r%d, r%d\n", ra, rb);
1098 {
1099 TCGv_i32 t0 = tcg_temp_new_i32();
1100 TCGv_i64 t1 = tcg_temp_new_i64();
1101 TCGv_i64 t2 = tcg_temp_new_i64();
1102 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1103 tcg_gen_ext_i32_i64(t1, t0);
1104 tcg_gen_concat_i32_i64(t2, maclo, machi);
1105 tcg_gen_sub_i64(t2, t2, t1);
1106 tcg_gen_extrl_i64_i32(maclo, t2);
1107 tcg_gen_shri_i64(t2, t2, 32);
1108 tcg_gen_extrl_i64_i32(machi, t2);
1109 tcg_temp_free_i32(t0);
1110 tcg_temp_free_i64(t1);
1111 tcg_temp_free_i64(t2);
1112 }
1113 break;
1114
1115 default:
1116 gen_illegal_exception(dc);
1117 break;
1118 }
1119 }
1120
1121 static void dec_logic(DisasContext *dc, uint32_t insn)
1122 {
1123 uint32_t op0;
1124 uint32_t rd, ra, L6;
1125 op0 = extract32(insn, 6, 2);
1126 rd = extract32(insn, 21, 5);
1127 ra = extract32(insn, 16, 5);
1128 L6 = extract32(insn, 0, 6);
1129
1130 switch (op0) {
1131 case 0x00: /* l.slli */
1132 LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
1133 tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1134 break;
1135
1136 case 0x01: /* l.srli */
1137 LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
1138 tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1139 break;
1140
1141 case 0x02: /* l.srai */
1142 LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
1143 tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break;
1144
1145 case 0x03: /* l.rori */
1146 LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
1147 tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1148 break;
1149
1150 default:
1151 gen_illegal_exception(dc);
1152 break;
1153 }
1154 }
1155
1156 static void dec_M(DisasContext *dc, uint32_t insn)
1157 {
1158 uint32_t op0;
1159 uint32_t rd;
1160 uint32_t K16;
1161 op0 = extract32(insn, 16, 1);
1162 rd = extract32(insn, 21, 5);
1163 K16 = extract32(insn, 0, 16);
1164
1165 switch (op0) {
1166 case 0x0: /* l.movhi */
1167 LOG_DIS("l.movhi r%d, %d\n", rd, K16);
1168 tcg_gen_movi_tl(cpu_R[rd], (K16 << 16));
1169 break;
1170
1171 case 0x1: /* l.macrc */
1172 LOG_DIS("l.macrc r%d\n", rd);
1173 tcg_gen_mov_tl(cpu_R[rd], maclo);
1174 tcg_gen_movi_tl(maclo, 0x0);
1175 tcg_gen_movi_tl(machi, 0x0);
1176 break;
1177
1178 default:
1179 gen_illegal_exception(dc);
1180 break;
1181 }
1182 }
1183
1184 static void dec_comp(DisasContext *dc, uint32_t insn)
1185 {
1186 uint32_t op0;
1187 uint32_t ra, rb;
1188
1189 op0 = extract32(insn, 21, 5);
1190 ra = extract32(insn, 16, 5);
1191 rb = extract32(insn, 11, 5);
1192
1193 tcg_gen_movi_i32(env_btaken, 0x0);
1194 /* unsigned integers */
1195 tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]);
1196 tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]);
1197
1198 switch (op0) {
1199 case 0x0: /* l.sfeq */
1200 LOG_DIS("l.sfeq r%d, r%d\n", ra, rb);
1201 tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]);
1202 break;
1203
1204 case 0x1: /* l.sfne */
1205 LOG_DIS("l.sfne r%d, r%d\n", ra, rb);
1206 tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]);
1207 break;
1208
1209 case 0x2: /* l.sfgtu */
1210 LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb);
1211 tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1212 break;
1213
1214 case 0x3: /* l.sfgeu */
1215 LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb);
1216 tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1217 break;
1218
1219 case 0x4: /* l.sfltu */
1220 LOG_DIS("l.sfltu r%d, r%d\n", ra, rb);
1221 tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1222 break;
1223
1224 case 0x5: /* l.sfleu */
1225 LOG_DIS("l.sfleu r%d, r%d\n", ra, rb);
1226 tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1227 break;
1228
1229 case 0xa: /* l.sfgts */
1230 LOG_DIS("l.sfgts r%d, r%d\n", ra, rb);
1231 tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]);
1232 break;
1233
1234 case 0xb: /* l.sfges */
1235 LOG_DIS("l.sfges r%d, r%d\n", ra, rb);
1236 tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]);
1237 break;
1238
1239 case 0xc: /* l.sflts */
1240 LOG_DIS("l.sflts r%d, r%d\n", ra, rb);
1241 tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]);
1242 break;
1243
1244 case 0xd: /* l.sfles */
1245 LOG_DIS("l.sfles r%d, r%d\n", ra, rb);
1246 tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]);
1247 break;
1248
1249 default:
1250 gen_illegal_exception(dc);
1251 break;
1252 }
1253 wb_SR_F();
1254 }
1255
1256 static void dec_compi(DisasContext *dc, uint32_t insn)
1257 {
1258 uint32_t op0;
1259 uint32_t ra, I16;
1260
1261 op0 = extract32(insn, 21, 5);
1262 ra = extract32(insn, 16, 5);
1263 I16 = extract32(insn, 0, 16);
1264
1265 tcg_gen_movi_i32(env_btaken, 0x0);
1266 I16 = sign_extend(I16, 16);
1267
1268 switch (op0) {
1269 case 0x0: /* l.sfeqi */
1270 LOG_DIS("l.sfeqi r%d, %d\n", ra, I16);
1271 tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16);
1272 break;
1273
1274 case 0x1: /* l.sfnei */
1275 LOG_DIS("l.sfnei r%d, %d\n", ra, I16);
1276 tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16);
1277 break;
1278
1279 case 0x2: /* l.sfgtui */
1280 LOG_DIS("l.sfgtui r%d, %d\n", ra, I16);
1281 tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16);
1282 break;
1283
1284 case 0x3: /* l.sfgeui */
1285 LOG_DIS("l.sfgeui r%d, %d\n", ra, I16);
1286 tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16);
1287 break;
1288
1289 case 0x4: /* l.sfltui */
1290 LOG_DIS("l.sfltui r%d, %d\n", ra, I16);
1291 tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16);
1292 break;
1293
1294 case 0x5: /* l.sfleui */
1295 LOG_DIS("l.sfleui r%d, %d\n", ra, I16);
1296 tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16);
1297 break;
1298
1299 case 0xa: /* l.sfgtsi */
1300 LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16);
1301 tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16);
1302 break;
1303
1304 case 0xb: /* l.sfgesi */
1305 LOG_DIS("l.sfgesi r%d, %d\n", ra, I16);
1306 tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16);
1307 break;
1308
1309 case 0xc: /* l.sfltsi */
1310 LOG_DIS("l.sfltsi r%d, %d\n", ra, I16);
1311 tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16);
1312 break;
1313
1314 case 0xd: /* l.sflesi */
1315 LOG_DIS("l.sflesi r%d, %d\n", ra, I16);
1316 tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16);
1317 break;
1318
1319 default:
1320 gen_illegal_exception(dc);
1321 break;
1322 }
1323 wb_SR_F();
1324 }
1325
1326 static void dec_sys(DisasContext *dc, uint32_t insn)
1327 {
1328 uint32_t op0;
1329 #ifdef OPENRISC_DISAS
1330 uint32_t K16;
1331 #endif
1332 op0 = extract32(insn, 16, 10);
1333 #ifdef OPENRISC_DISAS
1334 K16 = extract32(insn, 0, 16);
1335 #endif
1336
1337 switch (op0) {
1338 case 0x000: /* l.sys */
1339 LOG_DIS("l.sys %d\n", K16);
1340 tcg_gen_movi_tl(cpu_pc, dc->pc);
1341 gen_exception(dc, EXCP_SYSCALL);
1342 dc->is_jmp = DISAS_UPDATE;
1343 break;
1344
1345 case 0x100: /* l.trap */
1346 LOG_DIS("l.trap %d\n", K16);
1347 #if defined(CONFIG_USER_ONLY)
1348 return;
1349 #else
1350 if (dc->mem_idx == MMU_USER_IDX) {
1351 gen_illegal_exception(dc);
1352 return;
1353 }
1354 tcg_gen_movi_tl(cpu_pc, dc->pc);
1355 gen_exception(dc, EXCP_TRAP);
1356 #endif
1357 break;
1358
1359 case 0x300: /* l.csync */
1360 LOG_DIS("l.csync\n");
1361 #if defined(CONFIG_USER_ONLY)
1362 return;
1363 #else
1364 if (dc->mem_idx == MMU_USER_IDX) {
1365 gen_illegal_exception(dc);
1366 return;
1367 }
1368 #endif
1369 break;
1370
1371 case 0x200: /* l.msync */
1372 LOG_DIS("l.msync\n");
1373 #if defined(CONFIG_USER_ONLY)
1374 return;
1375 #else
1376 if (dc->mem_idx == MMU_USER_IDX) {
1377 gen_illegal_exception(dc);
1378 return;
1379 }
1380 #endif
1381 break;
1382
1383 case 0x270: /* l.psync */
1384 LOG_DIS("l.psync\n");
1385 #if defined(CONFIG_USER_ONLY)
1386 return;
1387 #else
1388 if (dc->mem_idx == MMU_USER_IDX) {
1389 gen_illegal_exception(dc);
1390 return;
1391 }
1392 #endif
1393 break;
1394
1395 default:
1396 gen_illegal_exception(dc);
1397 break;
1398 }
1399 }
1400
1401 static void dec_float(DisasContext *dc, uint32_t insn)
1402 {
1403 uint32_t op0;
1404 uint32_t ra, rb, rd;
1405 op0 = extract32(insn, 0, 8);
1406 ra = extract32(insn, 16, 5);
1407 rb = extract32(insn, 11, 5);
1408 rd = extract32(insn, 21, 5);
1409
1410 switch (op0) {
1411 case 0x00: /* lf.add.s */
1412 LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb);
1413 gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1414 break;
1415
1416 case 0x01: /* lf.sub.s */
1417 LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb);
1418 gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1419 break;
1420
1421
1422 case 0x02: /* lf.mul.s */
1423 LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb);
1424 if (ra != 0 && rb != 0) {
1425 gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1426 } else {
1427 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1428 tcg_gen_movi_i32(cpu_R[rd], 0x0);
1429 }
1430 break;
1431
1432 case 0x03: /* lf.div.s */
1433 LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb);
1434 gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1435 break;
1436
1437 case 0x04: /* lf.itof.s */
1438 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1439 gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]);
1440 break;
1441
1442 case 0x05: /* lf.ftoi.s */
1443 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1444 gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]);
1445 break;
1446
1447 case 0x06: /* lf.rem.s */
1448 LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb);
1449 gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1450 break;
1451
1452 case 0x07: /* lf.madd.s */
1453 LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb);
1454 gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1455 break;
1456
1457 case 0x08: /* lf.sfeq.s */
1458 LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
1459 gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1460 break;
1461
1462 case 0x09: /* lf.sfne.s */
1463 LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
1464 gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1465 break;
1466
1467 case 0x0a: /* lf.sfgt.s */
1468 LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
1469 gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1470 break;
1471
1472 case 0x0b: /* lf.sfge.s */
1473 LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
1474 gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1475 break;
1476
1477 case 0x0c: /* lf.sflt.s */
1478 LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
1479 gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1480 break;
1481
1482 case 0x0d: /* lf.sfle.s */
1483 LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
1484 gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1485 break;
1486
1487 /* not used yet, open it when we need or64. */
1488 /*#ifdef TARGET_OPENRISC64
1489 case 0x10: lf.add.d
1490 LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
1491 check_of64s(dc);
1492 gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1493 break;
1494
1495 case 0x11: lf.sub.d
1496 LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
1497 check_of64s(dc);
1498 gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1499 break;
1500
1501 case 0x12: lf.mul.d
1502 LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
1503 check_of64s(dc);
1504 if (ra != 0 && rb != 0) {
1505 gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1506 } else {
1507 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1508 tcg_gen_movi_i64(cpu_R[rd], 0x0);
1509 }
1510 break;
1511
1512 case 0x13: lf.div.d
1513 LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
1514 check_of64s(dc);
1515 gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1516 break;
1517
1518 case 0x14: lf.itof.d
1519 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1520 check_of64s(dc);
1521 gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
1522 break;
1523
1524 case 0x15: lf.ftoi.d
1525 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1526 check_of64s(dc);
1527 gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
1528 break;
1529
1530 case 0x16: lf.rem.d
1531 LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
1532 check_of64s(dc);
1533 gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1534 break;
1535
1536 case 0x17: lf.madd.d
1537 LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
1538 check_of64s(dc);
1539 gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1540 break;
1541
1542 case 0x18: lf.sfeq.d
1543 LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
1544 check_of64s(dc);
1545 gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1546 break;
1547
1548 case 0x1a: lf.sfgt.d
1549 LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
1550 check_of64s(dc);
1551 gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1552 break;
1553
1554 case 0x1b: lf.sfge.d
1555 LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
1556 check_of64s(dc);
1557 gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1558 break;
1559
1560 case 0x19: lf.sfne.d
1561 LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
1562 check_of64s(dc);
1563 gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1564 break;
1565
1566 case 0x1c: lf.sflt.d
1567 LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
1568 check_of64s(dc);
1569 gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1570 break;
1571
1572 case 0x1d: lf.sfle.d
1573 LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
1574 check_of64s(dc);
1575 gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1576 break;
1577 #endif*/
1578
1579 default:
1580 gen_illegal_exception(dc);
1581 break;
1582 }
1583 wb_SR_F();
1584 }
1585
1586 static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
1587 {
1588 uint32_t op0;
1589 uint32_t insn;
1590 insn = cpu_ldl_code(&cpu->env, dc->pc);
1591 op0 = extract32(insn, 26, 6);
1592
1593 switch (op0) {
1594 case 0x06:
1595 dec_M(dc, insn);
1596 break;
1597
1598 case 0x08:
1599 dec_sys(dc, insn);
1600 break;
1601
1602 case 0x2e:
1603 dec_logic(dc, insn);
1604 break;
1605
1606 case 0x2f:
1607 dec_compi(dc, insn);
1608 break;
1609
1610 case 0x31:
1611 dec_mac(dc, insn);
1612 break;
1613
1614 case 0x32:
1615 dec_float(dc, insn);
1616 break;
1617
1618 case 0x38:
1619 dec_calc(dc, insn);
1620 break;
1621
1622 case 0x39:
1623 dec_comp(dc, insn);
1624 break;
1625
1626 default:
1627 dec_misc(dc, insn);
1628 break;
1629 }
1630 }
1631
1632 void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
1633 {
1634 OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
1635 CPUState *cs = CPU(cpu);
1636 struct DisasContext ctx, *dc = &ctx;
1637 uint32_t pc_start;
1638 uint32_t next_page_start;
1639 int num_insns;
1640 int max_insns;
1641
1642 pc_start = tb->pc;
1643 dc->tb = tb;
1644
1645 dc->is_jmp = DISAS_NEXT;
1646 dc->ppc = pc_start;
1647 dc->pc = pc_start;
1648 dc->flags = cpu->env.cpucfgr;
1649 dc->mem_idx = cpu_mmu_index(&cpu->env, false);
1650 dc->synced_flags = dc->tb_flags = tb->flags;
1651 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1652 dc->singlestep_enabled = cs->singlestep_enabled;
1653 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1654 qemu_log("-----------------------------------------\n");
1655 log_cpu_state(CPU(cpu), 0);
1656 }
1657
1658 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1659 num_insns = 0;
1660 max_insns = tb->cflags & CF_COUNT_MASK;
1661
1662 if (max_insns == 0) {
1663 max_insns = CF_COUNT_MASK;
1664 }
1665 if (max_insns > TCG_MAX_INSNS) {
1666 max_insns = TCG_MAX_INSNS;
1667 }
1668
1669 gen_tb_start(tb);
1670
1671 do {
1672 tcg_gen_insn_start(dc->pc);
1673 num_insns++;
1674
1675 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
1676 tcg_gen_movi_tl(cpu_pc, dc->pc);
1677 gen_exception(dc, EXCP_DEBUG);
1678 dc->is_jmp = DISAS_UPDATE;
1679 /* The address covered by the breakpoint must be included in
1680 [tb->pc, tb->pc + tb->size) in order to for it to be
1681 properly cleared -- thus we increment the PC here so that
1682 the logic setting tb->size below does the right thing. */
1683 dc->pc += 4;
1684 break;
1685 }
1686
1687 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
1688 gen_io_start();
1689 }
1690 dc->ppc = dc->pc - 4;
1691 dc->npc = dc->pc + 4;
1692 tcg_gen_movi_tl(cpu_ppc, dc->ppc);
1693 tcg_gen_movi_tl(cpu_npc, dc->npc);
1694 disas_openrisc_insn(dc, cpu);
1695 dc->pc = dc->npc;
1696 /* delay slot */
1697 if (dc->delayed_branch) {
1698 dc->delayed_branch--;
1699 if (!dc->delayed_branch) {
1700 dc->tb_flags &= ~D_FLAG;
1701 gen_sync_flags(dc);
1702 tcg_gen_mov_tl(cpu_pc, jmp_pc);
1703 tcg_gen_mov_tl(cpu_npc, jmp_pc);
1704 tcg_gen_movi_tl(jmp_pc, 0);
1705 tcg_gen_exit_tb(0);
1706 dc->is_jmp = DISAS_JUMP;
1707 break;
1708 }
1709 }
1710 } while (!dc->is_jmp
1711 && !tcg_op_buf_full()
1712 && !cs->singlestep_enabled
1713 && !singlestep
1714 && (dc->pc < next_page_start)
1715 && num_insns < max_insns);
1716
1717 if (tb->cflags & CF_LAST_IO) {
1718 gen_io_end();
1719 }
1720 if (dc->is_jmp == DISAS_NEXT) {
1721 dc->is_jmp = DISAS_UPDATE;
1722 tcg_gen_movi_tl(cpu_pc, dc->pc);
1723 }
1724 if (unlikely(cs->singlestep_enabled)) {
1725 if (dc->is_jmp == DISAS_NEXT) {
1726 tcg_gen_movi_tl(cpu_pc, dc->pc);
1727 }
1728 gen_exception(dc, EXCP_DEBUG);
1729 } else {
1730 switch (dc->is_jmp) {
1731 case DISAS_NEXT:
1732 gen_goto_tb(dc, 0, dc->pc);
1733 break;
1734 default:
1735 case DISAS_JUMP:
1736 break;
1737 case DISAS_UPDATE:
1738 /* indicate that the hash table must be used
1739 to find the next TB */
1740 tcg_gen_exit_tb(0);
1741 break;
1742 case DISAS_TB_JUMP:
1743 /* nothing more to generate */
1744 break;
1745 }
1746 }
1747
1748 gen_tb_end(tb, num_insns);
1749
1750 tb->size = dc->pc - pc_start;
1751 tb->icount = num_insns;
1752
1753 #ifdef DEBUG_DISAS
1754 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1755 qemu_log("\n");
1756 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
1757 qemu_log("\nisize=%d osize=%d\n",
1758 dc->pc - pc_start, tcg_op_buf_count());
1759 }
1760 #endif
1761 }
1762
1763 void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
1764 fprintf_function cpu_fprintf,
1765 int flags)
1766 {
1767 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
1768 CPUOpenRISCState *env = &cpu->env;
1769 int i;
1770
1771 cpu_fprintf(f, "PC=%08x\n", env->pc);
1772 for (i = 0; i < 32; ++i) {
1773 cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i],
1774 (i % 4) == 3 ? '\n' : ' ');
1775 }
1776 }
1777
1778 void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
1779 target_ulong *data)
1780 {
1781 env->pc = data[0];
1782 }