vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-ppc / cpu-qom.h
1 /*
2 * QEMU PowerPC CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20 #ifndef QEMU_PPC_CPU_QOM_H
21 #define QEMU_PPC_CPU_QOM_H
22
23 #include "qom/cpu.h"
24
25 #ifdef TARGET_PPC64
26 #define TYPE_POWERPC_CPU "powerpc64-cpu"
27 #elif defined(TARGET_PPCEMB)
28 #define TYPE_POWERPC_CPU "embedded-powerpc-cpu"
29 #else
30 #define TYPE_POWERPC_CPU "powerpc-cpu"
31 #endif
32
33 #define POWERPC_CPU_CLASS(klass) \
34 OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
35 #define POWERPC_CPU(obj) \
36 OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
37 #define POWERPC_CPU_GET_CLASS(obj) \
38 OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
39
40 typedef struct PowerPCCPU PowerPCCPU;
41 typedef struct CPUPPCState CPUPPCState;
42 typedef struct ppc_tb_t ppc_tb_t;
43 typedef struct ppc_dcr_t ppc_dcr_t;
44
45 /*****************************************************************************/
46 /* MMU model */
47 typedef enum powerpc_mmu_t powerpc_mmu_t;
48 enum powerpc_mmu_t {
49 POWERPC_MMU_UNKNOWN = 0x00000000,
50 /* Standard 32 bits PowerPC MMU */
51 POWERPC_MMU_32B = 0x00000001,
52 /* PowerPC 6xx MMU with software TLB */
53 POWERPC_MMU_SOFT_6xx = 0x00000002,
54 /* PowerPC 74xx MMU with software TLB */
55 POWERPC_MMU_SOFT_74xx = 0x00000003,
56 /* PowerPC 4xx MMU with software TLB */
57 POWERPC_MMU_SOFT_4xx = 0x00000004,
58 /* PowerPC 4xx MMU with software TLB and zones protections */
59 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
60 /* PowerPC MMU in real mode only */
61 POWERPC_MMU_REAL = 0x00000006,
62 /* Freescale MPC8xx MMU model */
63 POWERPC_MMU_MPC8xx = 0x00000007,
64 /* BookE MMU model */
65 POWERPC_MMU_BOOKE = 0x00000008,
66 /* BookE 2.06 MMU model */
67 POWERPC_MMU_BOOKE206 = 0x00000009,
68 /* PowerPC 601 MMU model (specific BATs format) */
69 POWERPC_MMU_601 = 0x0000000A,
70 #define POWERPC_MMU_64 0x00010000
71 #define POWERPC_MMU_1TSEG 0x00020000
72 #define POWERPC_MMU_AMR 0x00040000
73 /* 64 bits PowerPC MMU */
74 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
75 /* Architecture 2.03 and later (has LPCR) */
76 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
77 /* Architecture 2.06 variant */
78 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
79 | POWERPC_MMU_AMR | 0x00000003,
80 /* Architecture 2.06 "degraded" (no 1T segments) */
81 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
82 | 0x00000003,
83 /* Architecture 2.07 variant */
84 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
85 | POWERPC_MMU_AMR | 0x00000004,
86 /* Architecture 2.07 "degraded" (no 1T segments) */
87 POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
88 | 0x00000004,
89 };
90
91 /*****************************************************************************/
92 /* Exception model */
93 typedef enum powerpc_excp_t powerpc_excp_t;
94 enum powerpc_excp_t {
95 POWERPC_EXCP_UNKNOWN = 0,
96 /* Standard PowerPC exception model */
97 POWERPC_EXCP_STD,
98 /* PowerPC 40x exception model */
99 POWERPC_EXCP_40x,
100 /* PowerPC 601 exception model */
101 POWERPC_EXCP_601,
102 /* PowerPC 602 exception model */
103 POWERPC_EXCP_602,
104 /* PowerPC 603 exception model */
105 POWERPC_EXCP_603,
106 /* PowerPC 603e exception model */
107 POWERPC_EXCP_603E,
108 /* PowerPC G2 exception model */
109 POWERPC_EXCP_G2,
110 /* PowerPC 604 exception model */
111 POWERPC_EXCP_604,
112 /* PowerPC 7x0 exception model */
113 POWERPC_EXCP_7x0,
114 /* PowerPC 7x5 exception model */
115 POWERPC_EXCP_7x5,
116 /* PowerPC 74xx exception model */
117 POWERPC_EXCP_74xx,
118 /* BookE exception model */
119 POWERPC_EXCP_BOOKE,
120 /* PowerPC 970 exception model */
121 POWERPC_EXCP_970,
122 /* POWER7 exception model */
123 POWERPC_EXCP_POWER7,
124 /* POWER8 exception model */
125 POWERPC_EXCP_POWER8,
126 };
127
128 /*****************************************************************************/
129 /* Input pins model */
130 typedef enum powerpc_input_t powerpc_input_t;
131 enum powerpc_input_t {
132 PPC_FLAGS_INPUT_UNKNOWN = 0,
133 /* PowerPC 6xx bus */
134 PPC_FLAGS_INPUT_6xx,
135 /* BookE bus */
136 PPC_FLAGS_INPUT_BookE,
137 /* PowerPC 405 bus */
138 PPC_FLAGS_INPUT_405,
139 /* PowerPC 970 bus */
140 PPC_FLAGS_INPUT_970,
141 /* PowerPC POWER7 bus */
142 PPC_FLAGS_INPUT_POWER7,
143 /* PowerPC 401 bus */
144 PPC_FLAGS_INPUT_401,
145 /* Freescale RCPU bus */
146 PPC_FLAGS_INPUT_RCPU,
147 };
148
149 struct ppc_segment_page_sizes;
150
151 /**
152 * PowerPCCPUClass:
153 * @parent_realize: The parent class' realize handler.
154 * @parent_reset: The parent class' reset handler.
155 *
156 * A PowerPC CPU model.
157 */
158 typedef struct PowerPCCPUClass {
159 /*< private >*/
160 CPUClass parent_class;
161 /*< public >*/
162
163 DeviceRealize parent_realize;
164 void (*parent_reset)(CPUState *cpu);
165
166 uint32_t pvr;
167 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
168 uint64_t pcr_mask;
169 uint32_t svr;
170 uint64_t insns_flags;
171 uint64_t insns_flags2;
172 uint64_t msr_mask;
173 powerpc_mmu_t mmu_model;
174 powerpc_excp_t excp_model;
175 powerpc_input_t bus_model;
176 uint32_t flags;
177 int bfd_mach;
178 uint32_t l1_dcache_size, l1_icache_size;
179 const struct ppc_segment_page_sizes *sps;
180 void (*init_proc)(CPUPPCState *env);
181 int (*check_pow)(CPUPPCState *env);
182 int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
183 bool (*interrupts_big_endian)(PowerPCCPU *cpu);
184 } PowerPCCPUClass;
185
186 #ifndef CONFIG_USER_ONLY
187 typedef struct PPCTimebase {
188 uint64_t guest_timebase;
189 int64_t time_of_the_day_ns;
190 } PPCTimebase;
191
192 extern const struct VMStateDescription vmstate_ppc_timebase;
193
194 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
195 .name = (stringify(_field)), \
196 .version_id = (_version), \
197 .size = sizeof(PPCTimebase), \
198 .vmsd = &vmstate_ppc_timebase, \
199 .flags = VMS_STRUCT, \
200 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \
201 }
202 #endif
203
204 #endif