PPC: rename msync to msync_4xx
[qemu.git] / target-ppc / helper_regs.h
1 /*
2 * PowerPC emulation special registers manipulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #if !defined(__HELPER_REGS_H__)
21 #define __HELPER_REGS_H__
22
23 /* Swap temporary saved registers with GPRs */
24 static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
25 {
26 target_ulong tmp;
27
28 tmp = env->gpr[0];
29 env->gpr[0] = env->tgpr[0];
30 env->tgpr[0] = tmp;
31 tmp = env->gpr[1];
32 env->gpr[1] = env->tgpr[1];
33 env->tgpr[1] = tmp;
34 tmp = env->gpr[2];
35 env->gpr[2] = env->tgpr[2];
36 env->tgpr[2] = tmp;
37 tmp = env->gpr[3];
38 env->gpr[3] = env->tgpr[3];
39 env->tgpr[3] = tmp;
40 }
41
42 static inline void hreg_compute_mem_idx(CPUPPCState *env)
43 {
44 /* Precompute MMU index */
45 if (msr_pr == 0 && msr_hv != 0) {
46 env->mmu_idx = 2;
47 } else {
48 env->mmu_idx = 1 - msr_pr;
49 }
50 }
51
52 static inline void hreg_compute_hflags(CPUPPCState *env)
53 {
54 target_ulong hflags_mask;
55
56 /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
57 hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
58 (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
59 (1 << MSR_LE);
60 hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
61 hreg_compute_mem_idx(env);
62 env->hflags = env->msr & hflags_mask;
63 /* Merge with hflags coming from other registers */
64 env->hflags |= env->hflags_nmsr;
65 }
66
67 static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
68 int alter_hv)
69 {
70 int excp;
71
72 excp = 0;
73 value &= env->msr_mask;
74 #if !defined (CONFIG_USER_ONLY)
75 if (!alter_hv) {
76 /* mtmsr cannot alter the hypervisor state */
77 value &= ~MSR_HVB;
78 value |= env->msr & MSR_HVB;
79 }
80 if (((value >> MSR_IR) & 1) != msr_ir ||
81 ((value >> MSR_DR) & 1) != msr_dr) {
82 /* Flush all tlb when changing translation mode */
83 tlb_flush(env, 1);
84 excp = POWERPC_EXCP_NONE;
85 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
86 }
87 if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
88 ((value ^ env->msr) & (1 << MSR_TGPR)))) {
89 /* Swap temporary saved registers with GPRs */
90 hreg_swap_gpr_tgpr(env);
91 }
92 if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
93 /* Change the exception prefix on PowerPC 601 */
94 env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
95 }
96 #endif
97 env->msr = value;
98 hreg_compute_hflags(env);
99 #if !defined (CONFIG_USER_ONLY)
100 if (unlikely(msr_pow == 1)) {
101 if ((*env->check_pow)(env)) {
102 env->halted = 1;
103 excp = EXCP_HALTED;
104 }
105 }
106 #endif
107
108 return excp;
109 }
110
111 #endif /* !defined(__HELPER_REGS_H__) */