target-ppc: Add missing 'static' and 'const' attributes
[qemu.git] / target-ppc / machine.c
1 #include "hw/hw.h"
2 #include "hw/boards.h"
3 #include "sysemu/kvm.h"
4 #include "helper_regs.h"
5
6 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
7 {
8 PowerPCCPU *cpu = opaque;
9 CPUPPCState *env = &cpu->env;
10 unsigned int i, j;
11 target_ulong sdr1;
12 uint32_t fpscr;
13 target_ulong xer;
14
15 for (i = 0; i < 32; i++)
16 qemu_get_betls(f, &env->gpr[i]);
17 #if !defined(TARGET_PPC64)
18 for (i = 0; i < 32; i++)
19 qemu_get_betls(f, &env->gprh[i]);
20 #endif
21 qemu_get_betls(f, &env->lr);
22 qemu_get_betls(f, &env->ctr);
23 for (i = 0; i < 8; i++)
24 qemu_get_be32s(f, &env->crf[i]);
25 qemu_get_betls(f, &xer);
26 cpu_write_xer(env, xer);
27 qemu_get_betls(f, &env->reserve_addr);
28 qemu_get_betls(f, &env->msr);
29 for (i = 0; i < 4; i++)
30 qemu_get_betls(f, &env->tgpr[i]);
31 for (i = 0; i < 32; i++) {
32 union {
33 float64 d;
34 uint64_t l;
35 } u;
36 u.l = qemu_get_be64(f);
37 env->fpr[i] = u.d;
38 }
39 qemu_get_be32s(f, &fpscr);
40 env->fpscr = fpscr;
41 qemu_get_sbe32s(f, &env->access_type);
42 #if defined(TARGET_PPC64)
43 qemu_get_betls(f, &env->spr[SPR_ASR]);
44 qemu_get_sbe32s(f, &env->slb_nr);
45 #endif
46 qemu_get_betls(f, &sdr1);
47 for (i = 0; i < 32; i++)
48 qemu_get_betls(f, &env->sr[i]);
49 for (i = 0; i < 2; i++)
50 for (j = 0; j < 8; j++)
51 qemu_get_betls(f, &env->DBAT[i][j]);
52 for (i = 0; i < 2; i++)
53 for (j = 0; j < 8; j++)
54 qemu_get_betls(f, &env->IBAT[i][j]);
55 qemu_get_sbe32s(f, &env->nb_tlb);
56 qemu_get_sbe32s(f, &env->tlb_per_way);
57 qemu_get_sbe32s(f, &env->nb_ways);
58 qemu_get_sbe32s(f, &env->last_way);
59 qemu_get_sbe32s(f, &env->id_tlbs);
60 qemu_get_sbe32s(f, &env->nb_pids);
61 if (env->tlb.tlb6) {
62 // XXX assumes 6xx
63 for (i = 0; i < env->nb_tlb; i++) {
64 qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
65 qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
66 qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
67 }
68 }
69 for (i = 0; i < 4; i++)
70 qemu_get_betls(f, &env->pb[i]);
71 for (i = 0; i < 1024; i++)
72 qemu_get_betls(f, &env->spr[i]);
73 if (!env->external_htab) {
74 ppc_store_sdr1(env, sdr1);
75 }
76 qemu_get_be32s(f, &env->vscr);
77 qemu_get_be64s(f, &env->spe_acc);
78 qemu_get_be32s(f, &env->spe_fscr);
79 qemu_get_betls(f, &env->msr_mask);
80 qemu_get_be32s(f, &env->flags);
81 qemu_get_sbe32s(f, &env->error_code);
82 qemu_get_be32s(f, &env->pending_interrupts);
83 qemu_get_be32s(f, &env->irq_input_state);
84 for (i = 0; i < POWERPC_EXCP_NB; i++)
85 qemu_get_betls(f, &env->excp_vectors[i]);
86 qemu_get_betls(f, &env->excp_prefix);
87 qemu_get_betls(f, &env->ivor_mask);
88 qemu_get_betls(f, &env->ivpr_mask);
89 qemu_get_betls(f, &env->hreset_vector);
90 qemu_get_betls(f, &env->nip);
91 qemu_get_betls(f, &env->hflags);
92 qemu_get_betls(f, &env->hflags_nmsr);
93 qemu_get_sbe32s(f, &env->mmu_idx);
94 qemu_get_sbe32(f); /* Discard unused power_mode */
95
96 return 0;
97 }
98
99 static int get_avr(QEMUFile *f, void *pv, size_t size)
100 {
101 ppc_avr_t *v = pv;
102
103 v->u64[0] = qemu_get_be64(f);
104 v->u64[1] = qemu_get_be64(f);
105
106 return 0;
107 }
108
109 static void put_avr(QEMUFile *f, void *pv, size_t size)
110 {
111 ppc_avr_t *v = pv;
112
113 qemu_put_be64(f, v->u64[0]);
114 qemu_put_be64(f, v->u64[1]);
115 }
116
117 static const VMStateInfo vmstate_info_avr = {
118 .name = "avr",
119 .get = get_avr,
120 .put = put_avr,
121 };
122
123 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
124 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
125
126 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \
127 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
128
129 static void cpu_pre_save(void *opaque)
130 {
131 PowerPCCPU *cpu = opaque;
132 CPUPPCState *env = &cpu->env;
133 int i;
134
135 env->spr[SPR_LR] = env->lr;
136 env->spr[SPR_CTR] = env->ctr;
137 env->spr[SPR_XER] = env->xer;
138 #if defined(TARGET_PPC64)
139 env->spr[SPR_CFAR] = env->cfar;
140 #endif
141 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
142
143 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
144 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
145 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
146 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
147 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
148 }
149 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
150 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
151 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
152 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
153 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
154 }
155 }
156
157 static int cpu_post_load(void *opaque, int version_id)
158 {
159 PowerPCCPU *cpu = opaque;
160 CPUPPCState *env = &cpu->env;
161 int i;
162
163 env->lr = env->spr[SPR_LR];
164 env->ctr = env->spr[SPR_CTR];
165 env->xer = env->spr[SPR_XER];
166 #if defined(TARGET_PPC64)
167 env->cfar = env->spr[SPR_CFAR];
168 #endif
169 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
170
171 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
172 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
173 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
174 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
175 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
176 }
177 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
178 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
179 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
180 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
181 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
182 }
183
184 if (!env->external_htab) {
185 /* Restore htab_base and htab_mask variables */
186 ppc_store_sdr1(env, env->spr[SPR_SDR1]);
187 }
188 hreg_compute_hflags(env);
189 hreg_compute_mem_idx(env);
190
191 return 0;
192 }
193
194 static bool fpu_needed(void *opaque)
195 {
196 PowerPCCPU *cpu = opaque;
197
198 return (cpu->env.insns_flags & PPC_FLOAT);
199 }
200
201 static const VMStateDescription vmstate_fpu = {
202 .name = "cpu/fpu",
203 .version_id = 1,
204 .minimum_version_id = 1,
205 .minimum_version_id_old = 1,
206 .fields = (VMStateField []) {
207 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
208 VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
209 VMSTATE_END_OF_LIST()
210 },
211 };
212
213 static bool altivec_needed(void *opaque)
214 {
215 PowerPCCPU *cpu = opaque;
216
217 return (cpu->env.insns_flags & PPC_ALTIVEC);
218 }
219
220 static const VMStateDescription vmstate_altivec = {
221 .name = "cpu/altivec",
222 .version_id = 1,
223 .minimum_version_id = 1,
224 .minimum_version_id_old = 1,
225 .fields = (VMStateField []) {
226 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
227 VMSTATE_UINT32(env.vscr, PowerPCCPU),
228 VMSTATE_END_OF_LIST()
229 },
230 };
231
232 static bool vsx_needed(void *opaque)
233 {
234 PowerPCCPU *cpu = opaque;
235
236 return (cpu->env.insns_flags2 & PPC2_VSX);
237 }
238
239 static const VMStateDescription vmstate_vsx = {
240 .name = "cpu/vsx",
241 .version_id = 1,
242 .minimum_version_id = 1,
243 .minimum_version_id_old = 1,
244 .fields = (VMStateField []) {
245 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
246 VMSTATE_END_OF_LIST()
247 },
248 };
249
250 static bool sr_needed(void *opaque)
251 {
252 #ifdef TARGET_PPC64
253 PowerPCCPU *cpu = opaque;
254
255 return !(cpu->env.mmu_model & POWERPC_MMU_64);
256 #else
257 return true;
258 #endif
259 }
260
261 static const VMStateDescription vmstate_sr = {
262 .name = "cpu/sr",
263 .version_id = 1,
264 .minimum_version_id = 1,
265 .minimum_version_id_old = 1,
266 .fields = (VMStateField []) {
267 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
268 VMSTATE_END_OF_LIST()
269 },
270 };
271
272 #ifdef TARGET_PPC64
273 static int get_slbe(QEMUFile *f, void *pv, size_t size)
274 {
275 ppc_slb_t *v = pv;
276
277 v->esid = qemu_get_be64(f);
278 v->vsid = qemu_get_be64(f);
279
280 return 0;
281 }
282
283 static void put_slbe(QEMUFile *f, void *pv, size_t size)
284 {
285 ppc_slb_t *v = pv;
286
287 qemu_put_be64(f, v->esid);
288 qemu_put_be64(f, v->vsid);
289 }
290
291 static const VMStateInfo vmstate_info_slbe = {
292 .name = "slbe",
293 .get = get_slbe,
294 .put = put_slbe,
295 };
296
297 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
298 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
299
300 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \
301 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
302
303 static bool slb_needed(void *opaque)
304 {
305 PowerPCCPU *cpu = opaque;
306
307 /* We don't support any of the old segment table based 64-bit CPUs */
308 return (cpu->env.mmu_model & POWERPC_MMU_64);
309 }
310
311 static const VMStateDescription vmstate_slb = {
312 .name = "cpu/slb",
313 .version_id = 1,
314 .minimum_version_id = 1,
315 .minimum_version_id_old = 1,
316 .fields = (VMStateField []) {
317 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
318 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
319 VMSTATE_END_OF_LIST()
320 }
321 };
322 #endif /* TARGET_PPC64 */
323
324 static const VMStateDescription vmstate_tlb6xx_entry = {
325 .name = "cpu/tlb6xx_entry",
326 .version_id = 1,
327 .minimum_version_id = 1,
328 .minimum_version_id_old = 1,
329 .fields = (VMStateField []) {
330 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
331 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
332 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
333 VMSTATE_END_OF_LIST()
334 },
335 };
336
337 static bool tlb6xx_needed(void *opaque)
338 {
339 PowerPCCPU *cpu = opaque;
340 CPUPPCState *env = &cpu->env;
341
342 return env->nb_tlb && (env->tlb_type == TLB_6XX);
343 }
344
345 static const VMStateDescription vmstate_tlb6xx = {
346 .name = "cpu/tlb6xx",
347 .version_id = 1,
348 .minimum_version_id = 1,
349 .minimum_version_id_old = 1,
350 .fields = (VMStateField []) {
351 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
352 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
353 env.nb_tlb,
354 vmstate_tlb6xx_entry,
355 ppc6xx_tlb_t),
356 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
357 VMSTATE_END_OF_LIST()
358 }
359 };
360
361 static const VMStateDescription vmstate_tlbemb_entry = {
362 .name = "cpu/tlbemb_entry",
363 .version_id = 1,
364 .minimum_version_id = 1,
365 .minimum_version_id_old = 1,
366 .fields = (VMStateField []) {
367 VMSTATE_UINT64(RPN, ppcemb_tlb_t),
368 VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
369 VMSTATE_UINTTL(PID, ppcemb_tlb_t),
370 VMSTATE_UINTTL(size, ppcemb_tlb_t),
371 VMSTATE_UINT32(prot, ppcemb_tlb_t),
372 VMSTATE_UINT32(attr, ppcemb_tlb_t),
373 VMSTATE_END_OF_LIST()
374 },
375 };
376
377 static bool tlbemb_needed(void *opaque)
378 {
379 PowerPCCPU *cpu = opaque;
380 CPUPPCState *env = &cpu->env;
381
382 return env->nb_tlb && (env->tlb_type == TLB_EMB);
383 }
384
385 static bool pbr403_needed(void *opaque)
386 {
387 PowerPCCPU *cpu = opaque;
388 uint32_t pvr = cpu->env.spr[SPR_PVR];
389
390 return (pvr & 0xffff0000) == 0x00200000;
391 }
392
393 static const VMStateDescription vmstate_pbr403 = {
394 .name = "cpu/pbr403",
395 .version_id = 1,
396 .minimum_version_id = 1,
397 .minimum_version_id_old = 1,
398 .fields = (VMStateField []) {
399 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
400 VMSTATE_END_OF_LIST()
401 },
402 };
403
404 static const VMStateDescription vmstate_tlbemb = {
405 .name = "cpu/tlb6xx",
406 .version_id = 1,
407 .minimum_version_id = 1,
408 .minimum_version_id_old = 1,
409 .fields = (VMStateField []) {
410 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
411 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
412 env.nb_tlb,
413 vmstate_tlbemb_entry,
414 ppcemb_tlb_t),
415 /* 403 protection registers */
416 VMSTATE_END_OF_LIST()
417 },
418 .subsections = (VMStateSubsection []) {
419 {
420 .vmsd = &vmstate_pbr403,
421 .needed = pbr403_needed,
422 } , {
423 /* empty */
424 }
425 }
426 };
427
428 static const VMStateDescription vmstate_tlbmas_entry = {
429 .name = "cpu/tlbmas_entry",
430 .version_id = 1,
431 .minimum_version_id = 1,
432 .minimum_version_id_old = 1,
433 .fields = (VMStateField []) {
434 VMSTATE_UINT32(mas8, ppcmas_tlb_t),
435 VMSTATE_UINT32(mas1, ppcmas_tlb_t),
436 VMSTATE_UINT64(mas2, ppcmas_tlb_t),
437 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
438 VMSTATE_END_OF_LIST()
439 },
440 };
441
442 static bool tlbmas_needed(void *opaque)
443 {
444 PowerPCCPU *cpu = opaque;
445 CPUPPCState *env = &cpu->env;
446
447 return env->nb_tlb && (env->tlb_type == TLB_MAS);
448 }
449
450 static const VMStateDescription vmstate_tlbmas = {
451 .name = "cpu/tlbmas",
452 .version_id = 1,
453 .minimum_version_id = 1,
454 .minimum_version_id_old = 1,
455 .fields = (VMStateField []) {
456 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
457 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
458 env.nb_tlb,
459 vmstate_tlbmas_entry,
460 ppcmas_tlb_t),
461 VMSTATE_END_OF_LIST()
462 }
463 };
464
465 const VMStateDescription vmstate_ppc_cpu = {
466 .name = "cpu",
467 .version_id = 5,
468 .minimum_version_id = 5,
469 .minimum_version_id_old = 4,
470 .load_state_old = cpu_load_old,
471 .pre_save = cpu_pre_save,
472 .post_load = cpu_post_load,
473 .fields = (VMStateField []) {
474 /* Verify we haven't changed the pvr */
475 VMSTATE_UINTTL_EQUAL(env.spr[SPR_PVR], PowerPCCPU),
476
477 /* User mode architected state */
478 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
479 #if !defined(TARGET_PPC64)
480 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
481 #endif
482 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
483 VMSTATE_UINTTL(env.nip, PowerPCCPU),
484
485 /* SPRs */
486 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
487 VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
488
489 /* Reservation */
490 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
491
492 /* Supervisor mode architected state */
493 VMSTATE_UINTTL(env.msr, PowerPCCPU),
494
495 /* Internal state */
496 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
497 /* FIXME: access_type? */
498
499 /* Sanity checking */
500 VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
501 VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
502 VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
503 VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
504 VMSTATE_END_OF_LIST()
505 },
506 .subsections = (VMStateSubsection []) {
507 {
508 .vmsd = &vmstate_fpu,
509 .needed = fpu_needed,
510 } , {
511 .vmsd = &vmstate_altivec,
512 .needed = altivec_needed,
513 } , {
514 .vmsd = &vmstate_vsx,
515 .needed = vsx_needed,
516 } , {
517 .vmsd = &vmstate_sr,
518 .needed = sr_needed,
519 } , {
520 #ifdef TARGET_PPC64
521 .vmsd = &vmstate_slb,
522 .needed = slb_needed,
523 } , {
524 #endif /* TARGET_PPC64 */
525 .vmsd = &vmstate_tlb6xx,
526 .needed = tlb6xx_needed,
527 } , {
528 .vmsd = &vmstate_tlbemb,
529 .needed = tlbemb_needed,
530 } , {
531 .vmsd = &vmstate_tlbmas,
532 .needed = tlbmas_needed,
533 } , {
534 /* empty */
535 }
536 }
537 };