trap signals for "-serial mon:stdio"
[qemu.git] / target-ppc / machine.c
1 #include "hw/hw.h"
2 #include "hw/boards.h"
3 #include "sysemu/kvm.h"
4
5 void cpu_save(QEMUFile *f, void *opaque)
6 {
7 CPUPPCState *env = (CPUPPCState *)opaque;
8 unsigned int i, j;
9 uint32_t fpscr;
10 target_ulong xer;
11
12 for (i = 0; i < 32; i++)
13 qemu_put_betls(f, &env->gpr[i]);
14 #if !defined(TARGET_PPC64)
15 for (i = 0; i < 32; i++)
16 qemu_put_betls(f, &env->gprh[i]);
17 #endif
18 qemu_put_betls(f, &env->lr);
19 qemu_put_betls(f, &env->ctr);
20 for (i = 0; i < 8; i++)
21 qemu_put_be32s(f, &env->crf[i]);
22 xer = cpu_read_xer(env);
23 qemu_put_betls(f, &xer);
24 qemu_put_betls(f, &env->reserve_addr);
25 qemu_put_betls(f, &env->msr);
26 for (i = 0; i < 4; i++)
27 qemu_put_betls(f, &env->tgpr[i]);
28 for (i = 0; i < 32; i++) {
29 union {
30 float64 d;
31 uint64_t l;
32 } u;
33 u.d = env->fpr[i];
34 qemu_put_be64(f, u.l);
35 }
36 fpscr = env->fpscr;
37 qemu_put_be32s(f, &fpscr);
38 qemu_put_sbe32s(f, &env->access_type);
39 #if defined(TARGET_PPC64)
40 qemu_put_betls(f, &env->spr[SPR_ASR]);
41 qemu_put_sbe32s(f, &env->slb_nr);
42 #endif
43 qemu_put_betls(f, &env->spr[SPR_SDR1]);
44 for (i = 0; i < 32; i++)
45 qemu_put_betls(f, &env->sr[i]);
46 for (i = 0; i < 2; i++)
47 for (j = 0; j < 8; j++)
48 qemu_put_betls(f, &env->DBAT[i][j]);
49 for (i = 0; i < 2; i++)
50 for (j = 0; j < 8; j++)
51 qemu_put_betls(f, &env->IBAT[i][j]);
52 qemu_put_sbe32s(f, &env->nb_tlb);
53 qemu_put_sbe32s(f, &env->tlb_per_way);
54 qemu_put_sbe32s(f, &env->nb_ways);
55 qemu_put_sbe32s(f, &env->last_way);
56 qemu_put_sbe32s(f, &env->id_tlbs);
57 qemu_put_sbe32s(f, &env->nb_pids);
58 if (env->tlb.tlb6) {
59 // XXX assumes 6xx
60 for (i = 0; i < env->nb_tlb; i++) {
61 qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
62 qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
63 qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
64 }
65 }
66 for (i = 0; i < 4; i++)
67 qemu_put_betls(f, &env->pb[i]);
68 for (i = 0; i < 1024; i++)
69 qemu_put_betls(f, &env->spr[i]);
70 qemu_put_be32s(f, &env->vscr);
71 qemu_put_be64s(f, &env->spe_acc);
72 qemu_put_be32s(f, &env->spe_fscr);
73 qemu_put_betls(f, &env->msr_mask);
74 qemu_put_be32s(f, &env->flags);
75 qemu_put_sbe32s(f, &env->error_code);
76 qemu_put_be32s(f, &env->pending_interrupts);
77 qemu_put_be32s(f, &env->irq_input_state);
78 for (i = 0; i < POWERPC_EXCP_NB; i++)
79 qemu_put_betls(f, &env->excp_vectors[i]);
80 qemu_put_betls(f, &env->excp_prefix);
81 qemu_put_betls(f, &env->ivor_mask);
82 qemu_put_betls(f, &env->ivpr_mask);
83 qemu_put_betls(f, &env->hreset_vector);
84 qemu_put_betls(f, &env->nip);
85 qemu_put_betls(f, &env->hflags);
86 qemu_put_betls(f, &env->hflags_nmsr);
87 qemu_put_sbe32s(f, &env->mmu_idx);
88 qemu_put_sbe32(f, 0);
89 }
90
91 int cpu_load(QEMUFile *f, void *opaque, int version_id)
92 {
93 CPUPPCState *env = (CPUPPCState *)opaque;
94 unsigned int i, j;
95 target_ulong sdr1;
96 uint32_t fpscr;
97 target_ulong xer;
98
99 for (i = 0; i < 32; i++)
100 qemu_get_betls(f, &env->gpr[i]);
101 #if !defined(TARGET_PPC64)
102 for (i = 0; i < 32; i++)
103 qemu_get_betls(f, &env->gprh[i]);
104 #endif
105 qemu_get_betls(f, &env->lr);
106 qemu_get_betls(f, &env->ctr);
107 for (i = 0; i < 8; i++)
108 qemu_get_be32s(f, &env->crf[i]);
109 qemu_get_betls(f, &xer);
110 cpu_write_xer(env, xer);
111 qemu_get_betls(f, &env->reserve_addr);
112 qemu_get_betls(f, &env->msr);
113 for (i = 0; i < 4; i++)
114 qemu_get_betls(f, &env->tgpr[i]);
115 for (i = 0; i < 32; i++) {
116 union {
117 float64 d;
118 uint64_t l;
119 } u;
120 u.l = qemu_get_be64(f);
121 env->fpr[i] = u.d;
122 }
123 qemu_get_be32s(f, &fpscr);
124 env->fpscr = fpscr;
125 qemu_get_sbe32s(f, &env->access_type);
126 #if defined(TARGET_PPC64)
127 qemu_get_betls(f, &env->spr[SPR_ASR]);
128 qemu_get_sbe32s(f, &env->slb_nr);
129 #endif
130 qemu_get_betls(f, &sdr1);
131 for (i = 0; i < 32; i++)
132 qemu_get_betls(f, &env->sr[i]);
133 for (i = 0; i < 2; i++)
134 for (j = 0; j < 8; j++)
135 qemu_get_betls(f, &env->DBAT[i][j]);
136 for (i = 0; i < 2; i++)
137 for (j = 0; j < 8; j++)
138 qemu_get_betls(f, &env->IBAT[i][j]);
139 qemu_get_sbe32s(f, &env->nb_tlb);
140 qemu_get_sbe32s(f, &env->tlb_per_way);
141 qemu_get_sbe32s(f, &env->nb_ways);
142 qemu_get_sbe32s(f, &env->last_way);
143 qemu_get_sbe32s(f, &env->id_tlbs);
144 qemu_get_sbe32s(f, &env->nb_pids);
145 if (env->tlb.tlb6) {
146 // XXX assumes 6xx
147 for (i = 0; i < env->nb_tlb; i++) {
148 qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
149 qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
150 qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
151 }
152 }
153 for (i = 0; i < 4; i++)
154 qemu_get_betls(f, &env->pb[i]);
155 for (i = 0; i < 1024; i++)
156 qemu_get_betls(f, &env->spr[i]);
157 ppc_store_sdr1(env, sdr1);
158 qemu_get_be32s(f, &env->vscr);
159 qemu_get_be64s(f, &env->spe_acc);
160 qemu_get_be32s(f, &env->spe_fscr);
161 qemu_get_betls(f, &env->msr_mask);
162 qemu_get_be32s(f, &env->flags);
163 qemu_get_sbe32s(f, &env->error_code);
164 qemu_get_be32s(f, &env->pending_interrupts);
165 qemu_get_be32s(f, &env->irq_input_state);
166 for (i = 0; i < POWERPC_EXCP_NB; i++)
167 qemu_get_betls(f, &env->excp_vectors[i]);
168 qemu_get_betls(f, &env->excp_prefix);
169 qemu_get_betls(f, &env->ivor_mask);
170 qemu_get_betls(f, &env->ivpr_mask);
171 qemu_get_betls(f, &env->hreset_vector);
172 qemu_get_betls(f, &env->nip);
173 qemu_get_betls(f, &env->hflags);
174 qemu_get_betls(f, &env->hflags_nmsr);
175 qemu_get_sbe32s(f, &env->mmu_idx);
176 qemu_get_sbe32(f); /* Discard unused power_mode */
177
178 return 0;
179 }