cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / target-ppc / misc_helper.c
1 /*
2 * Miscellaneous PowerPC emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "cpu.h"
20 #include "helper.h"
21
22 #include "helper_regs.h"
23
24 /*****************************************************************************/
25 /* SPR accesses */
26 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
27 {
28 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
29 env->spr[sprn]);
30 }
31
32 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
33 {
34 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
35 env->spr[sprn]);
36 }
37 #if !defined(CONFIG_USER_ONLY)
38
39 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
40 {
41 if (!env->external_htab) {
42 ppc_store_sdr1(env, val);
43 }
44 }
45
46 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
47 {
48 target_ulong hid0;
49
50 hid0 = env->spr[SPR_HID0];
51 if ((val ^ hid0) & 0x00000008) {
52 /* Change current endianness */
53 env->hflags &= ~(1 << MSR_LE);
54 env->hflags_nmsr &= ~(1 << MSR_LE);
55 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
56 env->hflags |= env->hflags_nmsr;
57 qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
58 val & 0x8 ? 'l' : 'b', env->hflags);
59 }
60 env->spr[SPR_HID0] = (uint32_t)val;
61 }
62
63 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
64 {
65 PowerPCCPU *cpu = ppc_env_get_cpu(env);
66
67 if (likely(env->pb[num] != value)) {
68 env->pb[num] = value;
69 /* Should be optimized */
70 tlb_flush(CPU(cpu), 1);
71 }
72 }
73
74 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
75 {
76 store_40x_dbcr0(env, val);
77 }
78
79 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
80 {
81 store_40x_sler(env, val);
82 }
83 #endif
84 /*****************************************************************************/
85 /* PowerPC 601 specific instructions (POWER bridge) */
86
87 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
88 {
89 switch (arg) {
90 case 0x0CUL:
91 /* Instruction cache line size */
92 return env->icache_line_size;
93 break;
94 case 0x0DUL:
95 /* Data cache line size */
96 return env->dcache_line_size;
97 break;
98 case 0x0EUL:
99 /* Minimum cache line size */
100 return (env->icache_line_size < env->dcache_line_size) ?
101 env->icache_line_size : env->dcache_line_size;
102 break;
103 case 0x0FUL:
104 /* Maximum cache line size */
105 return (env->icache_line_size > env->dcache_line_size) ?
106 env->icache_line_size : env->dcache_line_size;
107 break;
108 default:
109 /* Undefined */
110 return 0;
111 break;
112 }
113 }
114
115 /*****************************************************************************/
116 /* Special registers manipulation */
117
118 /* GDBstub can read and write MSR... */
119 void ppc_store_msr(CPUPPCState *env, target_ulong value)
120 {
121 hreg_store_msr(env, value, 0);
122 }