vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-ppc / misc_helper.c
1 /*
2 * Miscellaneous PowerPC emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/exec-all.h"
22 #include "exec/helper-proto.h"
23
24 #include "helper_regs.h"
25
26 /*****************************************************************************/
27 /* SPR accesses */
28 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
29 {
30 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
31 env->spr[sprn]);
32 }
33
34 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
35 {
36 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
37 env->spr[sprn]);
38 }
39
40 #ifdef TARGET_PPC64
41 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
42 uint32_t sprn, uint32_t cause)
43 {
44 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
45
46 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
47 cause &= FSCR_IC_MASK;
48 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
49
50 helper_raise_exception_err(env, POWERPC_EXCP_FU, 0);
51 }
52 #endif
53
54 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
55 uint32_t sprn, uint32_t cause)
56 {
57 #ifdef TARGET_PPC64
58 if (env->spr[SPR_FSCR] & (1ULL << bit)) {
59 /* Facility is enabled, continue */
60 return;
61 }
62 raise_fu_exception(env, bit, sprn, cause);
63 #endif
64 }
65
66 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
67 uint32_t sprn, uint32_t cause)
68 {
69 #ifdef TARGET_PPC64
70 if (env->msr & (1ULL << bit)) {
71 /* Facility is enabled, continue */
72 return;
73 }
74 raise_fu_exception(env, bit, sprn, cause);
75 #endif
76 }
77
78 #if !defined(CONFIG_USER_ONLY)
79
80 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
81 {
82 PowerPCCPU *cpu = ppc_env_get_cpu(env);
83
84 if (!env->external_htab) {
85 if (env->spr[SPR_SDR1] != val) {
86 ppc_store_sdr1(env, val);
87 tlb_flush(CPU(cpu), 1);
88 }
89 }
90 }
91
92 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
93 {
94 target_ulong hid0;
95
96 hid0 = env->spr[SPR_HID0];
97 if ((val ^ hid0) & 0x00000008) {
98 /* Change current endianness */
99 env->hflags &= ~(1 << MSR_LE);
100 env->hflags_nmsr &= ~(1 << MSR_LE);
101 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
102 env->hflags |= env->hflags_nmsr;
103 qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
104 val & 0x8 ? 'l' : 'b', env->hflags);
105 }
106 env->spr[SPR_HID0] = (uint32_t)val;
107 }
108
109 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
110 {
111 PowerPCCPU *cpu = ppc_env_get_cpu(env);
112
113 if (likely(env->pb[num] != value)) {
114 env->pb[num] = value;
115 /* Should be optimized */
116 tlb_flush(CPU(cpu), 1);
117 }
118 }
119
120 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
121 {
122 store_40x_dbcr0(env, val);
123 }
124
125 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
126 {
127 store_40x_sler(env, val);
128 }
129 #endif
130 /*****************************************************************************/
131 /* PowerPC 601 specific instructions (POWER bridge) */
132
133 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
134 {
135 switch (arg) {
136 case 0x0CUL:
137 /* Instruction cache line size */
138 return env->icache_line_size;
139 break;
140 case 0x0DUL:
141 /* Data cache line size */
142 return env->dcache_line_size;
143 break;
144 case 0x0EUL:
145 /* Minimum cache line size */
146 return (env->icache_line_size < env->dcache_line_size) ?
147 env->icache_line_size : env->dcache_line_size;
148 break;
149 case 0x0FUL:
150 /* Maximum cache line size */
151 return (env->icache_line_size > env->dcache_line_size) ?
152 env->icache_line_size : env->dcache_line_size;
153 break;
154 default:
155 /* Undefined */
156 return 0;
157 break;
158 }
159 }
160
161 /*****************************************************************************/
162 /* Special registers manipulation */
163
164 /* GDBstub can read and write MSR... */
165 void ppc_store_msr(CPUPPCState *env, target_ulong value)
166 {
167 hreg_store_msr(env, value, 0);
168 }