nbd: Don't use *_to_cpup() functions
[qemu.git] / target-ppc / mmu-hash64.c
1 /*
2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "qemu/error-report.h"
26 #include "sysemu/kvm.h"
27 #include "qemu/error-report.h"
28 #include "kvm_ppc.h"
29 #include "mmu-hash64.h"
30 #include "exec/log.h"
31
32 //#define DEBUG_SLB
33
34 #ifdef DEBUG_SLB
35 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
36 #else
37 # define LOG_SLB(...) do { } while (0)
38 #endif
39
40 /*
41 * Used to indicate that a CPU has its hash page table (HPT) managed
42 * within the host kernel
43 */
44 #define MMU_HASH64_KVM_MANAGED_HPT ((void *)-1)
45
46 /*
47 * SLB handling
48 */
49
50 static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
51 {
52 CPUPPCState *env = &cpu->env;
53 uint64_t esid_256M, esid_1T;
54 int n;
55
56 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
57
58 esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
59 esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
60
61 for (n = 0; n < env->slb_nr; n++) {
62 ppc_slb_t *slb = &env->slb[n];
63
64 LOG_SLB("%s: slot %d %016" PRIx64 " %016"
65 PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
66 /* We check for 1T matches on all MMUs here - if the MMU
67 * doesn't have 1T segment support, we will have prevented 1T
68 * entries from being inserted in the slbmte code. */
69 if (((slb->esid == esid_256M) &&
70 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
71 || ((slb->esid == esid_1T) &&
72 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
73 return slb;
74 }
75 }
76
77 return NULL;
78 }
79
80 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
81 {
82 CPUPPCState *env = &cpu->env;
83 int i;
84 uint64_t slbe, slbv;
85
86 cpu_synchronize_state(CPU(cpu));
87
88 cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
89 for (i = 0; i < env->slb_nr; i++) {
90 slbe = env->slb[i].esid;
91 slbv = env->slb[i].vsid;
92 if (slbe == 0 && slbv == 0) {
93 continue;
94 }
95 cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
96 i, slbe, slbv);
97 }
98 }
99
100 void helper_slbia(CPUPPCState *env)
101 {
102 int n;
103
104 /* XXX: Warning: slbia never invalidates the first segment */
105 for (n = 1; n < env->slb_nr; n++) {
106 ppc_slb_t *slb = &env->slb[n];
107
108 if (slb->esid & SLB_ESID_V) {
109 slb->esid &= ~SLB_ESID_V;
110 /* XXX: given the fact that segment size is 256 MB or 1TB,
111 * and we still don't have a tlb_flush_mask(env, n, mask)
112 * in QEMU, we just invalidate all TLBs
113 */
114 env->tlb_need_flush = 1;
115 }
116 }
117 }
118
119 void helper_slbie(CPUPPCState *env, target_ulong addr)
120 {
121 PowerPCCPU *cpu = ppc_env_get_cpu(env);
122 ppc_slb_t *slb;
123
124 slb = slb_lookup(cpu, addr);
125 if (!slb) {
126 return;
127 }
128
129 if (slb->esid & SLB_ESID_V) {
130 slb->esid &= ~SLB_ESID_V;
131
132 /* XXX: given the fact that segment size is 256 MB or 1TB,
133 * and we still don't have a tlb_flush_mask(env, n, mask)
134 * in QEMU, we just invalidate all TLBs
135 */
136 env->tlb_need_flush = 1;
137 }
138 }
139
140 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
141 target_ulong esid, target_ulong vsid)
142 {
143 CPUPPCState *env = &cpu->env;
144 ppc_slb_t *slb = &env->slb[slot];
145 const struct ppc_one_seg_page_size *sps = NULL;
146 int i;
147
148 if (slot >= env->slb_nr) {
149 return -1; /* Bad slot number */
150 }
151 if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
152 return -1; /* Reserved bits set */
153 }
154 if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
155 return -1; /* Bad segment size */
156 }
157 if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
158 return -1; /* 1T segment on MMU that doesn't support it */
159 }
160
161 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
162 const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
163
164 if (!sps1->page_shift) {
165 break;
166 }
167
168 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
169 sps = sps1;
170 break;
171 }
172 }
173
174 if (!sps) {
175 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
176 " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
177 slot, esid, vsid);
178 return -1;
179 }
180
181 slb->esid = esid;
182 slb->vsid = vsid;
183 slb->sps = sps;
184
185 LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
186 " %016" PRIx64 "\n", __func__, slot, esid, vsid,
187 slb->esid, slb->vsid);
188
189 return 0;
190 }
191
192 static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
193 target_ulong *rt)
194 {
195 CPUPPCState *env = &cpu->env;
196 int slot = rb & 0xfff;
197 ppc_slb_t *slb = &env->slb[slot];
198
199 if (slot >= env->slb_nr) {
200 return -1;
201 }
202
203 *rt = slb->esid;
204 return 0;
205 }
206
207 static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
208 target_ulong *rt)
209 {
210 CPUPPCState *env = &cpu->env;
211 int slot = rb & 0xfff;
212 ppc_slb_t *slb = &env->slb[slot];
213
214 if (slot >= env->slb_nr) {
215 return -1;
216 }
217
218 *rt = slb->vsid;
219 return 0;
220 }
221
222 static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
223 target_ulong *rt)
224 {
225 CPUPPCState *env = &cpu->env;
226 ppc_slb_t *slb;
227
228 if (!msr_is_64bit(env, env->msr)) {
229 rb &= 0xffffffff;
230 }
231 slb = slb_lookup(cpu, rb);
232 if (slb == NULL) {
233 *rt = (target_ulong)-1ul;
234 } else {
235 *rt = slb->vsid;
236 }
237 return 0;
238 }
239
240 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
241 {
242 PowerPCCPU *cpu = ppc_env_get_cpu(env);
243
244 if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
245 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
246 POWERPC_EXCP_INVAL);
247 }
248 }
249
250 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
251 {
252 PowerPCCPU *cpu = ppc_env_get_cpu(env);
253 target_ulong rt = 0;
254
255 if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
256 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
257 POWERPC_EXCP_INVAL);
258 }
259 return rt;
260 }
261
262 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
263 {
264 PowerPCCPU *cpu = ppc_env_get_cpu(env);
265 target_ulong rt = 0;
266
267 if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
268 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
269 POWERPC_EXCP_INVAL);
270 }
271 return rt;
272 }
273
274 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
275 {
276 PowerPCCPU *cpu = ppc_env_get_cpu(env);
277 target_ulong rt = 0;
278
279 if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
280 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
281 POWERPC_EXCP_INVAL);
282 }
283 return rt;
284 }
285
286 /*
287 * 64-bit hash table MMU handling
288 */
289 void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
290 Error **errp)
291 {
292 CPUPPCState *env = &cpu->env;
293 target_ulong htabsize = value & SDR_64_HTABSIZE;
294
295 env->spr[SPR_SDR1] = value;
296 if (htabsize > 28) {
297 error_setg(errp,
298 "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
299 htabsize);
300 htabsize = 28;
301 }
302 env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1;
303 env->htab_base = value & SDR_64_HTABORG;
304 }
305
306 void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
307 Error **errp)
308 {
309 CPUPPCState *env = &cpu->env;
310 Error *local_err = NULL;
311
312 if (hpt) {
313 env->external_htab = hpt;
314 } else {
315 env->external_htab = MMU_HASH64_KVM_MANAGED_HPT;
316 }
317 ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
318 &local_err);
319 if (local_err) {
320 error_propagate(errp, local_err);
321 return;
322 }
323
324 /* Not strictly necessary, but makes it clearer that an external
325 * htab is in use when debugging */
326 env->htab_base = -1;
327
328 if (kvm_enabled()) {
329 if (kvmppc_put_books_sregs(cpu) < 0) {
330 error_setg(errp, "Unable to update SDR1 in KVM");
331 }
332 }
333 }
334
335 static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
336 ppc_slb_t *slb, ppc_hash_pte64_t pte)
337 {
338 CPUPPCState *env = &cpu->env;
339 unsigned pp, key;
340 /* Some pp bit combinations have undefined behaviour, so default
341 * to no access in those cases */
342 int prot = 0;
343
344 key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
345 : (slb->vsid & SLB_VSID_KS));
346 pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
347
348 if (key == 0) {
349 switch (pp) {
350 case 0x0:
351 case 0x1:
352 case 0x2:
353 prot = PAGE_READ | PAGE_WRITE;
354 break;
355
356 case 0x3:
357 case 0x6:
358 prot = PAGE_READ;
359 break;
360 }
361 } else {
362 switch (pp) {
363 case 0x0:
364 case 0x6:
365 prot = 0;
366 break;
367
368 case 0x1:
369 case 0x3:
370 prot = PAGE_READ;
371 break;
372
373 case 0x2:
374 prot = PAGE_READ | PAGE_WRITE;
375 break;
376 }
377 }
378
379 /* No execute if either noexec or guarded bits set */
380 if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)
381 || (slb->vsid & SLB_VSID_N)) {
382 prot |= PAGE_EXEC;
383 }
384
385 return prot;
386 }
387
388 static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
389 {
390 CPUPPCState *env = &cpu->env;
391 int key, amrbits;
392 int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
393
394 /* Only recent MMUs implement Virtual Page Class Key Protection */
395 if (!(env->mmu_model & POWERPC_MMU_AMR)) {
396 return prot;
397 }
398
399 key = HPTE64_R_KEY(pte.pte1);
400 amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
401
402 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
403 /* env->spr[SPR_AMR]); */
404
405 /*
406 * A store is permitted if the AMR bit is 0. Remove write
407 * protection if it is set.
408 */
409 if (amrbits & 0x2) {
410 prot &= ~PAGE_WRITE;
411 }
412 /*
413 * A load is permitted if the AMR bit is 0. Remove read
414 * protection if it is set.
415 */
416 if (amrbits & 0x1) {
417 prot &= ~PAGE_READ;
418 }
419
420 return prot;
421 }
422
423 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index)
424 {
425 uint64_t token = 0;
426 hwaddr pte_offset;
427
428 pte_offset = pte_index * HASH_PTE_SIZE_64;
429 if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
430 /*
431 * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
432 */
433 token = kvmppc_hash64_read_pteg(cpu, pte_index);
434 } else if (cpu->env.external_htab) {
435 /*
436 * HTAB is controlled by QEMU. Just point to the internally
437 * accessible PTEG.
438 */
439 token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset;
440 } else if (cpu->env.htab_base) {
441 token = cpu->env.htab_base + pte_offset;
442 }
443 return token;
444 }
445
446 void ppc_hash64_stop_access(PowerPCCPU *cpu, uint64_t token)
447 {
448 if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
449 kvmppc_hash64_free_pteg(token);
450 }
451 }
452
453 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
454 bool secondary, target_ulong ptem,
455 ppc_hash_pte64_t *pte)
456 {
457 CPUPPCState *env = &cpu->env;
458 int i;
459 uint64_t token;
460 target_ulong pte0, pte1;
461 target_ulong pte_index;
462
463 pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP;
464 token = ppc_hash64_start_access(cpu, pte_index);
465 if (!token) {
466 return -1;
467 }
468 for (i = 0; i < HPTES_PER_GROUP; i++) {
469 pte0 = ppc_hash64_load_hpte0(cpu, token, i);
470 pte1 = ppc_hash64_load_hpte1(cpu, token, i);
471
472 if ((pte0 & HPTE64_V_VALID)
473 && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
474 && HPTE64_V_COMPARE(pte0, ptem)) {
475 pte->pte0 = pte0;
476 pte->pte1 = pte1;
477 ppc_hash64_stop_access(cpu, token);
478 return (pte_index + i) * HASH_PTE_SIZE_64;
479 }
480 }
481 ppc_hash64_stop_access(cpu, token);
482 /*
483 * We didn't find a valid entry.
484 */
485 return -1;
486 }
487
488 static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
489 ppc_slb_t *slb, target_ulong eaddr,
490 ppc_hash_pte64_t *pte)
491 {
492 CPUPPCState *env = &cpu->env;
493 hwaddr pte_offset;
494 hwaddr hash;
495 uint64_t vsid, epnmask, epn, ptem;
496
497 /* The SLB store path should prevent any bad page size encodings
498 * getting in there, so: */
499 assert(slb->sps);
500
501 epnmask = ~((1ULL << slb->sps->page_shift) - 1);
502
503 if (slb->vsid & SLB_VSID_B) {
504 /* 1TB segment */
505 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
506 epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
507 hash = vsid ^ (vsid << 25) ^ (epn >> slb->sps->page_shift);
508 } else {
509 /* 256M segment */
510 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
511 epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
512 hash = vsid ^ (epn >> slb->sps->page_shift);
513 }
514 ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
515
516 /* Page address translation */
517 qemu_log_mask(CPU_LOG_MMU,
518 "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
519 " hash " TARGET_FMT_plx "\n",
520 env->htab_base, env->htab_mask, hash);
521
522 /* Primary PTEG lookup */
523 qemu_log_mask(CPU_LOG_MMU,
524 "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
525 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
526 " hash=" TARGET_FMT_plx "\n",
527 env->htab_base, env->htab_mask, vsid, ptem, hash);
528 pte_offset = ppc_hash64_pteg_search(cpu, hash, 0, ptem, pte);
529
530 if (pte_offset == -1) {
531 /* Secondary PTEG lookup */
532 qemu_log_mask(CPU_LOG_MMU,
533 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
534 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
535 " hash=" TARGET_FMT_plx "\n", env->htab_base,
536 env->htab_mask, vsid, ptem, ~hash);
537
538 pte_offset = ppc_hash64_pteg_search(cpu, ~hash, 1, ptem, pte);
539 }
540
541 return pte_offset;
542 }
543
544 static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
545 uint64_t pte0, uint64_t pte1)
546 {
547 int i;
548
549 if (!(pte0 & HPTE64_V_LARGE)) {
550 if (sps->page_shift != 12) {
551 /* 4kiB page in a non 4kiB segment */
552 return 0;
553 }
554 /* Normal 4kiB page */
555 return 12;
556 }
557
558 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
559 const struct ppc_one_page_size *ps = &sps->enc[i];
560 uint64_t mask;
561
562 if (!ps->page_shift) {
563 break;
564 }
565
566 if (ps->page_shift == 12) {
567 /* L bit is set so this can't be a 4kiB page */
568 continue;
569 }
570
571 mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
572
573 if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
574 return ps->page_shift;
575 }
576 }
577
578 return 0; /* Bad page size encoding */
579 }
580
581 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
582 uint64_t pte0, uint64_t pte1,
583 unsigned *seg_page_shift)
584 {
585 CPUPPCState *env = &cpu->env;
586 int i;
587
588 if (!(pte0 & HPTE64_V_LARGE)) {
589 *seg_page_shift = 12;
590 return 12;
591 }
592
593 /*
594 * The encodings in env->sps need to be carefully chosen so that
595 * this gives an unambiguous result.
596 */
597 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
598 const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
599 unsigned shift;
600
601 if (!sps->page_shift) {
602 break;
603 }
604
605 shift = hpte_page_shift(sps, pte0, pte1);
606 if (shift) {
607 *seg_page_shift = sps->page_shift;
608 return shift;
609 }
610 }
611
612 *seg_page_shift = 0;
613 return 0;
614 }
615
616 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
617 int rwx, int mmu_idx)
618 {
619 CPUState *cs = CPU(cpu);
620 CPUPPCState *env = &cpu->env;
621 ppc_slb_t *slb;
622 unsigned apshift;
623 hwaddr pte_offset;
624 ppc_hash_pte64_t pte;
625 int pp_prot, amr_prot, prot;
626 uint64_t new_pte1;
627 const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
628 hwaddr raddr;
629
630 assert((rwx == 0) || (rwx == 1) || (rwx == 2));
631
632 /* 1. Handle real mode accesses */
633 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
634 /* Translation is off */
635 /* In real mode the top 4 effective address bits are ignored */
636 raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
637 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
638 PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
639 TARGET_PAGE_SIZE);
640 return 0;
641 }
642
643 /* 2. Translation is on, so look up the SLB */
644 slb = slb_lookup(cpu, eaddr);
645
646 if (!slb) {
647 if (rwx == 2) {
648 cs->exception_index = POWERPC_EXCP_ISEG;
649 env->error_code = 0;
650 } else {
651 cs->exception_index = POWERPC_EXCP_DSEG;
652 env->error_code = 0;
653 env->spr[SPR_DAR] = eaddr;
654 }
655 return 1;
656 }
657
658 /* 3. Check for segment level no-execute violation */
659 if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
660 cs->exception_index = POWERPC_EXCP_ISI;
661 env->error_code = 0x10000000;
662 return 1;
663 }
664
665 /* 4. Locate the PTE in the hash table */
666 pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte);
667 if (pte_offset == -1) {
668 if (rwx == 2) {
669 cs->exception_index = POWERPC_EXCP_ISI;
670 env->error_code = 0x40000000;
671 } else {
672 cs->exception_index = POWERPC_EXCP_DSI;
673 env->error_code = 0;
674 env->spr[SPR_DAR] = eaddr;
675 if (rwx == 1) {
676 env->spr[SPR_DSISR] = 0x42000000;
677 } else {
678 env->spr[SPR_DSISR] = 0x40000000;
679 }
680 }
681 return 1;
682 }
683 qemu_log_mask(CPU_LOG_MMU,
684 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
685
686 /* Validate page size encoding */
687 apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
688 if (!apshift) {
689 error_report("Bad page size encoding in HPTE 0x%"PRIx64" - 0x%"PRIx64
690 " @ 0x%"HWADDR_PRIx, pte.pte0, pte.pte1, pte_offset);
691 /* Not entirely sure what the right action here, but machine
692 * check seems reasonable */
693 cs->exception_index = POWERPC_EXCP_MCHECK;
694 env->error_code = 0;
695 return 1;
696 }
697
698 /* 5. Check access permissions */
699
700 pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
701 amr_prot = ppc_hash64_amr_prot(cpu, pte);
702 prot = pp_prot & amr_prot;
703
704 if ((need_prot[rwx] & ~prot) != 0) {
705 /* Access right violation */
706 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
707 if (rwx == 2) {
708 cs->exception_index = POWERPC_EXCP_ISI;
709 env->error_code = 0x08000000;
710 } else {
711 target_ulong dsisr = 0;
712
713 cs->exception_index = POWERPC_EXCP_DSI;
714 env->error_code = 0;
715 env->spr[SPR_DAR] = eaddr;
716 if (need_prot[rwx] & ~pp_prot) {
717 dsisr |= 0x08000000;
718 }
719 if (rwx == 1) {
720 dsisr |= 0x02000000;
721 }
722 if (need_prot[rwx] & ~amr_prot) {
723 dsisr |= 0x00200000;
724 }
725 env->spr[SPR_DSISR] = dsisr;
726 }
727 return 1;
728 }
729
730 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
731
732 /* 6. Update PTE referenced and changed bits if necessary */
733
734 new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
735 if (rwx == 1) {
736 new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
737 } else {
738 /* Treat the page as read-only for now, so that a later write
739 * will pass through this function again to set the C bit */
740 prot &= ~PAGE_WRITE;
741 }
742
743 if (new_pte1 != pte.pte1) {
744 ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64,
745 pte.pte0, new_pte1);
746 }
747
748 /* 7. Determine the real address from the PTE */
749
750 raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
751
752 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
753 prot, mmu_idx, 1ULL << apshift);
754
755 return 0;
756 }
757
758 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
759 {
760 CPUPPCState *env = &cpu->env;
761 ppc_slb_t *slb;
762 hwaddr pte_offset;
763 ppc_hash_pte64_t pte;
764 unsigned apshift;
765
766 if (msr_dr == 0) {
767 /* In real mode the top 4 effective address bits are ignored */
768 return addr & 0x0FFFFFFFFFFFFFFFULL;
769 }
770
771 slb = slb_lookup(cpu, addr);
772 if (!slb) {
773 return -1;
774 }
775
776 pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte);
777 if (pte_offset == -1) {
778 return -1;
779 }
780
781 apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
782 if (!apshift) {
783 return -1;
784 }
785
786 return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
787 & TARGET_PAGE_MASK;
788 }
789
790 void ppc_hash64_store_hpte(PowerPCCPU *cpu,
791 target_ulong pte_index,
792 target_ulong pte0, target_ulong pte1)
793 {
794 CPUPPCState *env = &cpu->env;
795
796 if (env->external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
797 kvmppc_hash64_write_pte(env, pte_index, pte0, pte1);
798 return;
799 }
800
801 pte_index *= HASH_PTE_SIZE_64;
802 if (env->external_htab) {
803 stq_p(env->external_htab + pte_index, pte0);
804 stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
805 } else {
806 stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0);
807 stq_phys(CPU(cpu)->as,
808 env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1);
809 }
810 }
811
812 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
813 target_ulong pte_index,
814 target_ulong pte0, target_ulong pte1)
815 {
816 /*
817 * XXX: given the fact that there are too many segments to
818 * invalidate, and we still don't have a tlb_flush_mask(env, n,
819 * mask) in QEMU, we just invalidate all TLBs
820 */
821 tlb_flush(CPU(cpu), 1);
822 }