2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "qemu/error-report.h"
26 #include "sysemu/kvm.h"
27 #include "qemu/error-report.h"
29 #include "mmu-hash64.h"
35 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
37 # define LOG_SLB(...) do { } while (0)
41 * Used to indicate that a CPU has its hash page table (HPT) managed
42 * within the host kernel
44 #define MMU_HASH64_KVM_MANAGED_HPT ((void *)-1)
50 static ppc_slb_t
*slb_lookup(PowerPCCPU
*cpu
, target_ulong eaddr
)
52 CPUPPCState
*env
= &cpu
->env
;
53 uint64_t esid_256M
, esid_1T
;
56 LOG_SLB("%s: eaddr " TARGET_FMT_lx
"\n", __func__
, eaddr
);
58 esid_256M
= (eaddr
& SEGMENT_MASK_256M
) | SLB_ESID_V
;
59 esid_1T
= (eaddr
& SEGMENT_MASK_1T
) | SLB_ESID_V
;
61 for (n
= 0; n
< env
->slb_nr
; n
++) {
62 ppc_slb_t
*slb
= &env
->slb
[n
];
64 LOG_SLB("%s: slot %d %016" PRIx64
" %016"
65 PRIx64
"\n", __func__
, n
, slb
->esid
, slb
->vsid
);
66 /* We check for 1T matches on all MMUs here - if the MMU
67 * doesn't have 1T segment support, we will have prevented 1T
68 * entries from being inserted in the slbmte code. */
69 if (((slb
->esid
== esid_256M
) &&
70 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_256M
))
71 || ((slb
->esid
== esid_1T
) &&
72 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_1T
))) {
80 void dump_slb(FILE *f
, fprintf_function cpu_fprintf
, PowerPCCPU
*cpu
)
82 CPUPPCState
*env
= &cpu
->env
;
86 cpu_synchronize_state(CPU(cpu
));
88 cpu_fprintf(f
, "SLB\tESID\t\t\tVSID\n");
89 for (i
= 0; i
< env
->slb_nr
; i
++) {
90 slbe
= env
->slb
[i
].esid
;
91 slbv
= env
->slb
[i
].vsid
;
92 if (slbe
== 0 && slbv
== 0) {
95 cpu_fprintf(f
, "%d\t0x%016" PRIx64
"\t0x%016" PRIx64
"\n",
100 void helper_slbia(CPUPPCState
*env
)
104 /* XXX: Warning: slbia never invalidates the first segment */
105 for (n
= 1; n
< env
->slb_nr
; n
++) {
106 ppc_slb_t
*slb
= &env
->slb
[n
];
108 if (slb
->esid
& SLB_ESID_V
) {
109 slb
->esid
&= ~SLB_ESID_V
;
110 /* XXX: given the fact that segment size is 256 MB or 1TB,
111 * and we still don't have a tlb_flush_mask(env, n, mask)
112 * in QEMU, we just invalidate all TLBs
114 env
->tlb_need_flush
= 1;
119 void helper_slbie(CPUPPCState
*env
, target_ulong addr
)
121 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
124 slb
= slb_lookup(cpu
, addr
);
129 if (slb
->esid
& SLB_ESID_V
) {
130 slb
->esid
&= ~SLB_ESID_V
;
132 /* XXX: given the fact that segment size is 256 MB or 1TB,
133 * and we still don't have a tlb_flush_mask(env, n, mask)
134 * in QEMU, we just invalidate all TLBs
136 env
->tlb_need_flush
= 1;
140 int ppc_store_slb(PowerPCCPU
*cpu
, target_ulong slot
,
141 target_ulong esid
, target_ulong vsid
)
143 CPUPPCState
*env
= &cpu
->env
;
144 ppc_slb_t
*slb
= &env
->slb
[slot
];
145 const struct ppc_one_seg_page_size
*sps
= NULL
;
148 if (slot
>= env
->slb_nr
) {
149 return -1; /* Bad slot number */
151 if (esid
& ~(SLB_ESID_ESID
| SLB_ESID_V
)) {
152 return -1; /* Reserved bits set */
154 if (vsid
& (SLB_VSID_B
& ~SLB_VSID_B_1T
)) {
155 return -1; /* Bad segment size */
157 if ((vsid
& SLB_VSID_B
) && !(env
->mmu_model
& POWERPC_MMU_1TSEG
)) {
158 return -1; /* 1T segment on MMU that doesn't support it */
161 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
162 const struct ppc_one_seg_page_size
*sps1
= &env
->sps
.sps
[i
];
164 if (!sps1
->page_shift
) {
168 if ((vsid
& SLB_VSID_LLP_MASK
) == sps1
->slb_enc
) {
175 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
176 " esid 0x"TARGET_FMT_lx
" vsid 0x"TARGET_FMT_lx
,
185 LOG_SLB("%s: %d " TARGET_FMT_lx
" - " TARGET_FMT_lx
" => %016" PRIx64
186 " %016" PRIx64
"\n", __func__
, slot
, esid
, vsid
,
187 slb
->esid
, slb
->vsid
);
192 static int ppc_load_slb_esid(PowerPCCPU
*cpu
, target_ulong rb
,
195 CPUPPCState
*env
= &cpu
->env
;
196 int slot
= rb
& 0xfff;
197 ppc_slb_t
*slb
= &env
->slb
[slot
];
199 if (slot
>= env
->slb_nr
) {
207 static int ppc_load_slb_vsid(PowerPCCPU
*cpu
, target_ulong rb
,
210 CPUPPCState
*env
= &cpu
->env
;
211 int slot
= rb
& 0xfff;
212 ppc_slb_t
*slb
= &env
->slb
[slot
];
214 if (slot
>= env
->slb_nr
) {
222 void helper_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
224 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
226 if (ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
) < 0) {
227 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
232 target_ulong
helper_load_slb_esid(CPUPPCState
*env
, target_ulong rb
)
234 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
237 if (ppc_load_slb_esid(cpu
, rb
, &rt
) < 0) {
238 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
244 target_ulong
helper_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
246 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
249 if (ppc_load_slb_vsid(cpu
, rb
, &rt
) < 0) {
250 helper_raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
257 * 64-bit hash table MMU handling
259 void ppc_hash64_set_sdr1(PowerPCCPU
*cpu
, target_ulong value
,
262 CPUPPCState
*env
= &cpu
->env
;
263 target_ulong htabsize
= value
& SDR_64_HTABSIZE
;
265 env
->spr
[SPR_SDR1
] = value
;
268 "Invalid HTABSIZE 0x" TARGET_FMT_lx
" stored in SDR1",
272 env
->htab_mask
= (1ULL << (htabsize
+ 18 - 7)) - 1;
273 env
->htab_base
= value
& SDR_64_HTABORG
;
276 void ppc_hash64_set_external_hpt(PowerPCCPU
*cpu
, void *hpt
, int shift
,
279 CPUPPCState
*env
= &cpu
->env
;
280 Error
*local_err
= NULL
;
283 env
->external_htab
= hpt
;
285 env
->external_htab
= MMU_HASH64_KVM_MANAGED_HPT
;
287 ppc_hash64_set_sdr1(cpu
, (target_ulong
)(uintptr_t)hpt
| (shift
- 18),
290 error_propagate(errp
, local_err
);
294 /* Not strictly necessary, but makes it clearer that an external
295 * htab is in use when debugging */
299 if (kvmppc_put_books_sregs(cpu
) < 0) {
300 error_setg(errp
, "Unable to update SDR1 in KVM");
305 static int ppc_hash64_pte_prot(PowerPCCPU
*cpu
,
306 ppc_slb_t
*slb
, ppc_hash_pte64_t pte
)
308 CPUPPCState
*env
= &cpu
->env
;
310 /* Some pp bit combinations have undefined behaviour, so default
311 * to no access in those cases */
314 key
= !!(msr_pr ?
(slb
->vsid
& SLB_VSID_KP
)
315 : (slb
->vsid
& SLB_VSID_KS
));
316 pp
= (pte
.pte1
& HPTE64_R_PP
) | ((pte
.pte1
& HPTE64_R_PP0
) >> 61);
323 prot
= PAGE_READ
| PAGE_WRITE
;
344 prot
= PAGE_READ
| PAGE_WRITE
;
349 /* No execute if either noexec or guarded bits set */
350 if (!(pte
.pte1
& HPTE64_R_N
) || (pte
.pte1
& HPTE64_R_G
)
351 || (slb
->vsid
& SLB_VSID_N
)) {
358 static int ppc_hash64_amr_prot(PowerPCCPU
*cpu
, ppc_hash_pte64_t pte
)
360 CPUPPCState
*env
= &cpu
->env
;
362 int prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
364 /* Only recent MMUs implement Virtual Page Class Key Protection */
365 if (!(env
->mmu_model
& POWERPC_MMU_AMR
)) {
369 key
= HPTE64_R_KEY(pte
.pte1
);
370 amrbits
= (env
->spr
[SPR_AMR
] >> 2*(31 - key
)) & 0x3;
372 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
373 /* env->spr[SPR_AMR]); */
376 * A store is permitted if the AMR bit is 0. Remove write
377 * protection if it is set.
383 * A load is permitted if the AMR bit is 0. Remove read
384 * protection if it is set.
393 uint64_t ppc_hash64_start_access(PowerPCCPU
*cpu
, target_ulong pte_index
)
398 pte_offset
= pte_index
* HASH_PTE_SIZE_64
;
399 if (cpu
->env
.external_htab
== MMU_HASH64_KVM_MANAGED_HPT
) {
401 * HTAB is controlled by KVM. Fetch the PTEG into a new buffer.
403 token
= kvmppc_hash64_read_pteg(cpu
, pte_index
);
404 } else if (cpu
->env
.external_htab
) {
406 * HTAB is controlled by QEMU. Just point to the internally
409 token
= (uint64_t)(uintptr_t) cpu
->env
.external_htab
+ pte_offset
;
410 } else if (cpu
->env
.htab_base
) {
411 token
= cpu
->env
.htab_base
+ pte_offset
;
416 void ppc_hash64_stop_access(PowerPCCPU
*cpu
, uint64_t token
)
418 if (cpu
->env
.external_htab
== MMU_HASH64_KVM_MANAGED_HPT
) {
419 kvmppc_hash64_free_pteg(token
);
423 static hwaddr
ppc_hash64_pteg_search(PowerPCCPU
*cpu
, hwaddr hash
,
424 bool secondary
, target_ulong ptem
,
425 ppc_hash_pte64_t
*pte
)
427 CPUPPCState
*env
= &cpu
->env
;
430 target_ulong pte0
, pte1
;
431 target_ulong pte_index
;
433 pte_index
= (hash
& env
->htab_mask
) * HPTES_PER_GROUP
;
434 token
= ppc_hash64_start_access(cpu
, pte_index
);
438 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
439 pte0
= ppc_hash64_load_hpte0(cpu
, token
, i
);
440 pte1
= ppc_hash64_load_hpte1(cpu
, token
, i
);
442 if ((pte0
& HPTE64_V_VALID
)
443 && (secondary
== !!(pte0
& HPTE64_V_SECONDARY
))
444 && HPTE64_V_COMPARE(pte0
, ptem
)) {
447 ppc_hash64_stop_access(cpu
, token
);
448 return (pte_index
+ i
) * HASH_PTE_SIZE_64
;
451 ppc_hash64_stop_access(cpu
, token
);
453 * We didn't find a valid entry.
458 static hwaddr
ppc_hash64_htab_lookup(PowerPCCPU
*cpu
,
459 ppc_slb_t
*slb
, target_ulong eaddr
,
460 ppc_hash_pte64_t
*pte
)
462 CPUPPCState
*env
= &cpu
->env
;
465 uint64_t vsid
, epnmask
, epn
, ptem
;
467 /* The SLB store path should prevent any bad page size encodings
468 * getting in there, so: */
471 epnmask
= ~((1ULL << slb
->sps
->page_shift
) - 1);
473 if (slb
->vsid
& SLB_VSID_B
) {
475 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT_1T
;
476 epn
= (eaddr
& ~SEGMENT_MASK_1T
) & epnmask
;
477 hash
= vsid
^ (vsid
<< 25) ^ (epn
>> slb
->sps
->page_shift
);
480 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT
;
481 epn
= (eaddr
& ~SEGMENT_MASK_256M
) & epnmask
;
482 hash
= vsid
^ (epn
>> slb
->sps
->page_shift
);
484 ptem
= (slb
->vsid
& SLB_VSID_PTEM
) | ((epn
>> 16) & HPTE64_V_AVPN
);
486 /* Page address translation */
487 qemu_log_mask(CPU_LOG_MMU
,
488 "htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
489 " hash " TARGET_FMT_plx
"\n",
490 env
->htab_base
, env
->htab_mask
, hash
);
492 /* Primary PTEG lookup */
493 qemu_log_mask(CPU_LOG_MMU
,
494 "0 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
495 " vsid=" TARGET_FMT_lx
" ptem=" TARGET_FMT_lx
496 " hash=" TARGET_FMT_plx
"\n",
497 env
->htab_base
, env
->htab_mask
, vsid
, ptem
, hash
);
498 pte_offset
= ppc_hash64_pteg_search(cpu
, hash
, 0, ptem
, pte
);
500 if (pte_offset
== -1) {
501 /* Secondary PTEG lookup */
502 qemu_log_mask(CPU_LOG_MMU
,
503 "1 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
504 " vsid=" TARGET_FMT_lx
" api=" TARGET_FMT_lx
505 " hash=" TARGET_FMT_plx
"\n", env
->htab_base
,
506 env
->htab_mask
, vsid
, ptem
, ~hash
);
508 pte_offset
= ppc_hash64_pteg_search(cpu
, ~hash
, 1, ptem
, pte
);
514 static unsigned hpte_page_shift(const struct ppc_one_seg_page_size
*sps
,
515 uint64_t pte0
, uint64_t pte1
)
519 if (!(pte0
& HPTE64_V_LARGE
)) {
520 if (sps
->page_shift
!= 12) {
521 /* 4kiB page in a non 4kiB segment */
524 /* Normal 4kiB page */
528 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
529 const struct ppc_one_page_size
*ps
= &sps
->enc
[i
];
532 if (!ps
->page_shift
) {
536 if (ps
->page_shift
== 12) {
537 /* L bit is set so this can't be a 4kiB page */
541 mask
= ((1ULL << ps
->page_shift
) - 1) & HPTE64_R_RPN
;
543 if ((pte1
& mask
) == (ps
->pte_enc
<< HPTE64_R_RPN_SHIFT
)) {
544 return ps
->page_shift
;
548 return 0; /* Bad page size encoding */
551 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU
*cpu
,
552 uint64_t pte0
, uint64_t pte1
,
553 unsigned *seg_page_shift
)
555 CPUPPCState
*env
= &cpu
->env
;
558 if (!(pte0
& HPTE64_V_LARGE
)) {
559 *seg_page_shift
= 12;
564 * The encodings in env->sps need to be carefully chosen so that
565 * this gives an unambiguous result.
567 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
568 const struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
571 if (!sps
->page_shift
) {
575 shift
= hpte_page_shift(sps
, pte0
, pte1
);
577 *seg_page_shift
= sps
->page_shift
;
586 int ppc_hash64_handle_mmu_fault(PowerPCCPU
*cpu
, vaddr eaddr
,
587 int rwx
, int mmu_idx
)
589 CPUState
*cs
= CPU(cpu
);
590 CPUPPCState
*env
= &cpu
->env
;
594 ppc_hash_pte64_t pte
;
595 int pp_prot
, amr_prot
, prot
;
597 const int need_prot
[] = {PAGE_READ
, PAGE_WRITE
, PAGE_EXEC
};
600 assert((rwx
== 0) || (rwx
== 1) || (rwx
== 2));
602 /* 1. Handle real mode accesses */
603 if (((rwx
== 2) && (msr_ir
== 0)) || ((rwx
!= 2) && (msr_dr
== 0))) {
604 /* Translation is off */
605 /* In real mode the top 4 effective address bits are ignored */
606 raddr
= eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
607 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
608 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
, mmu_idx
,
613 /* 2. Translation is on, so look up the SLB */
614 slb
= slb_lookup(cpu
, eaddr
);
618 cs
->exception_index
= POWERPC_EXCP_ISEG
;
621 cs
->exception_index
= POWERPC_EXCP_DSEG
;
623 env
->spr
[SPR_DAR
] = eaddr
;
628 /* 3. Check for segment level no-execute violation */
629 if ((rwx
== 2) && (slb
->vsid
& SLB_VSID_N
)) {
630 cs
->exception_index
= POWERPC_EXCP_ISI
;
631 env
->error_code
= 0x10000000;
635 /* 4. Locate the PTE in the hash table */
636 pte_offset
= ppc_hash64_htab_lookup(cpu
, slb
, eaddr
, &pte
);
637 if (pte_offset
== -1) {
639 cs
->exception_index
= POWERPC_EXCP_ISI
;
640 env
->error_code
= 0x40000000;
642 cs
->exception_index
= POWERPC_EXCP_DSI
;
644 env
->spr
[SPR_DAR
] = eaddr
;
646 env
->spr
[SPR_DSISR
] = 0x42000000;
648 env
->spr
[SPR_DSISR
] = 0x40000000;
653 qemu_log_mask(CPU_LOG_MMU
,
654 "found PTE at offset %08" HWADDR_PRIx
"\n", pte_offset
);
656 /* Validate page size encoding */
657 apshift
= hpte_page_shift(slb
->sps
, pte
.pte0
, pte
.pte1
);
659 error_report("Bad page size encoding in HPTE 0x%"PRIx64
" - 0x%"PRIx64
660 " @ 0x%"HWADDR_PRIx
, pte
.pte0
, pte
.pte1
, pte_offset
);
661 /* Not entirely sure what the right action here, but machine
662 * check seems reasonable */
663 cs
->exception_index
= POWERPC_EXCP_MCHECK
;
668 /* 5. Check access permissions */
670 pp_prot
= ppc_hash64_pte_prot(cpu
, slb
, pte
);
671 amr_prot
= ppc_hash64_amr_prot(cpu
, pte
);
672 prot
= pp_prot
& amr_prot
;
674 if ((need_prot
[rwx
] & ~prot
) != 0) {
675 /* Access right violation */
676 qemu_log_mask(CPU_LOG_MMU
, "PTE access rejected\n");
678 cs
->exception_index
= POWERPC_EXCP_ISI
;
679 env
->error_code
= 0x08000000;
681 target_ulong dsisr
= 0;
683 cs
->exception_index
= POWERPC_EXCP_DSI
;
685 env
->spr
[SPR_DAR
] = eaddr
;
686 if (need_prot
[rwx
] & ~pp_prot
) {
692 if (need_prot
[rwx
] & ~amr_prot
) {
695 env
->spr
[SPR_DSISR
] = dsisr
;
700 qemu_log_mask(CPU_LOG_MMU
, "PTE access granted !\n");
702 /* 6. Update PTE referenced and changed bits if necessary */
704 new_pte1
= pte
.pte1
| HPTE64_R_R
; /* set referenced bit */
706 new_pte1
|= HPTE64_R_C
; /* set changed (dirty) bit */
708 /* Treat the page as read-only for now, so that a later write
709 * will pass through this function again to set the C bit */
713 if (new_pte1
!= pte
.pte1
) {
714 ppc_hash64_store_hpte(cpu
, pte_offset
/ HASH_PTE_SIZE_64
,
718 /* 7. Determine the real address from the PTE */
720 raddr
= deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, eaddr
);
722 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
723 prot
, mmu_idx
, 1ULL << apshift
);
728 hwaddr
ppc_hash64_get_phys_page_debug(PowerPCCPU
*cpu
, target_ulong addr
)
730 CPUPPCState
*env
= &cpu
->env
;
733 ppc_hash_pte64_t pte
;
737 /* In real mode the top 4 effective address bits are ignored */
738 return addr
& 0x0FFFFFFFFFFFFFFFULL
;
741 slb
= slb_lookup(cpu
, addr
);
746 pte_offset
= ppc_hash64_htab_lookup(cpu
, slb
, addr
, &pte
);
747 if (pte_offset
== -1) {
751 apshift
= hpte_page_shift(slb
->sps
, pte
.pte0
, pte
.pte1
);
756 return deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, addr
)
760 void ppc_hash64_store_hpte(PowerPCCPU
*cpu
,
761 target_ulong pte_index
,
762 target_ulong pte0
, target_ulong pte1
)
764 CPUPPCState
*env
= &cpu
->env
;
766 if (env
->external_htab
== MMU_HASH64_KVM_MANAGED_HPT
) {
767 kvmppc_hash64_write_pte(env
, pte_index
, pte0
, pte1
);
771 pte_index
*= HASH_PTE_SIZE_64
;
772 if (env
->external_htab
) {
773 stq_p(env
->external_htab
+ pte_index
, pte0
);
774 stq_p(env
->external_htab
+ pte_index
+ HASH_PTE_SIZE_64
/ 2, pte1
);
776 stq_phys(CPU(cpu
)->as
, env
->htab_base
+ pte_index
, pte0
);
777 stq_phys(CPU(cpu
)->as
,
778 env
->htab_base
+ pte_index
+ HASH_PTE_SIZE_64
/ 2, pte1
);
782 void ppc_hash64_tlb_flush_hpte(PowerPCCPU
*cpu
,
783 target_ulong pte_index
,
784 target_ulong pte0
, target_ulong pte1
)
787 * XXX: given the fact that there are too many segments to
788 * invalidate, and we still don't have a tlb_flush_mask(env, n,
789 * mask) in QEMU, we just invalidate all TLBs
791 tlb_flush(CPU(cpu
), 1);