trap signals for "-serial mon:stdio"
[qemu.git] / target-ppc / mmu-hash64.h
1 #if !defined (__MMU_HASH64_H__)
2 #define __MMU_HASH64_H__
3
4 #ifndef CONFIG_USER_ONLY
5
6 #ifdef TARGET_PPC64
7 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
8 int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
9 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
10 int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
11 int mmu_idx);
12 #endif
13
14 /*
15 * SLB definitions
16 */
17
18 /* Bits in the SLB ESID word */
19 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
20 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
21
22 /* Bits in the SLB VSID word */
23 #define SLB_VSID_SHIFT 12
24 #define SLB_VSID_SHIFT_1T 24
25 #define SLB_VSID_SSIZE_SHIFT 62
26 #define SLB_VSID_B 0xc000000000000000ULL
27 #define SLB_VSID_B_256M 0x0000000000000000ULL
28 #define SLB_VSID_B_1T 0x4000000000000000ULL
29 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
30 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
31 #define SLB_VSID_KS 0x0000000000000800ULL
32 #define SLB_VSID_KP 0x0000000000000400ULL
33 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
34 #define SLB_VSID_L 0x0000000000000100ULL
35 #define SLB_VSID_C 0x0000000000000080ULL /* class */
36 #define SLB_VSID_LP 0x0000000000000030ULL
37 #define SLB_VSID_ATTR 0x0000000000000FFFULL
38
39 /*
40 * Hash page table definitions
41 */
42
43 #define HPTES_PER_GROUP 8
44 #define HASH_PTE_SIZE_64 16
45 #define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
46
47 #define HPTE64_V_SSIZE_SHIFT 62
48 #define HPTE64_V_AVPN_SHIFT 7
49 #define HPTE64_V_AVPN 0x3fffffffffffff80ULL
50 #define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
51 #define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80ULL))
52 #define HPTE64_V_LARGE 0x0000000000000004ULL
53 #define HPTE64_V_SECONDARY 0x0000000000000002ULL
54 #define HPTE64_V_VALID 0x0000000000000001ULL
55
56 #define HPTE64_R_PP0 0x8000000000000000ULL
57 #define HPTE64_R_TS 0x4000000000000000ULL
58 #define HPTE64_R_KEY_HI 0x3000000000000000ULL
59 #define HPTE64_R_RPN_SHIFT 12
60 #define HPTE64_R_RPN 0x0ffffffffffff000ULL
61 #define HPTE64_R_FLAGS 0x00000000000003ffULL
62 #define HPTE64_R_PP 0x0000000000000003ULL
63 #define HPTE64_R_N 0x0000000000000004ULL
64 #define HPTE64_R_G 0x0000000000000008ULL
65 #define HPTE64_R_M 0x0000000000000010ULL
66 #define HPTE64_R_I 0x0000000000000020ULL
67 #define HPTE64_R_W 0x0000000000000040ULL
68 #define HPTE64_R_WIMG 0x0000000000000078ULL
69 #define HPTE64_R_C 0x0000000000000080ULL
70 #define HPTE64_R_R 0x0000000000000100ULL
71 #define HPTE64_R_KEY_LO 0x0000000000000e00ULL
72 #define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 60) | \
73 (((x) & HPTE64_R_KEY_LO) >> 9))
74
75 #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
76 #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
77
78 static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
79 hwaddr pte_offset)
80 {
81 if (env->external_htab) {
82 return ldq_p(env->external_htab + pte_offset);
83 } else {
84 return ldq_phys(env->htab_base + pte_offset);
85 }
86 }
87
88 static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
89 hwaddr pte_offset)
90 {
91 if (env->external_htab) {
92 return ldq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2);
93 } else {
94 return ldq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
95 }
96 }
97
98 static inline void ppc_hash64_store_hpte0(CPUPPCState *env,
99 hwaddr pte_offset, target_ulong pte0)
100 {
101 if (env->external_htab) {
102 stq_p(env->external_htab + pte_offset, pte0);
103 } else {
104 stq_phys(env->htab_base + pte_offset, pte0);
105 }
106 }
107
108 static inline void ppc_hash64_store_hpte1(CPUPPCState *env,
109 hwaddr pte_offset, target_ulong pte1)
110 {
111 if (env->external_htab) {
112 stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1);
113 } else {
114 stq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
115 }
116 }
117
118 typedef struct {
119 uint64_t pte0, pte1;
120 } ppc_hash_pte64_t;
121
122 #endif /* CONFIG_USER_ONLY */
123
124 #endif /* !defined (__MMU_HASH64_H__) */