vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-ppc / mmu-hash64.h
1 #if !defined (__MMU_HASH64_H__)
2 #define __MMU_HASH64_H__
3
4 #ifndef CONFIG_USER_ONLY
5
6 #ifdef TARGET_PPC64
7 void ppc_hash64_check_page_sizes(PowerPCCPU *cpu, Error **errp);
8 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu);
9 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
10 target_ulong esid, target_ulong vsid);
11 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
12 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,
13 int mmu_idx);
14 void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong index,
15 target_ulong pte0, target_ulong pte1);
16 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
17 target_ulong pte_index,
18 target_ulong pte0, target_ulong pte1);
19 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
20 uint64_t pte0, uint64_t pte1,
21 unsigned *seg_page_shift);
22 #endif
23
24 /*
25 * SLB definitions
26 */
27
28 /* Bits in the SLB ESID word */
29 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
30 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
31
32 /* Bits in the SLB VSID word */
33 #define SLB_VSID_SHIFT 12
34 #define SLB_VSID_SHIFT_1T 24
35 #define SLB_VSID_SSIZE_SHIFT 62
36 #define SLB_VSID_B 0xc000000000000000ULL
37 #define SLB_VSID_B_256M 0x0000000000000000ULL
38 #define SLB_VSID_B_1T 0x4000000000000000ULL
39 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
40 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
41 #define SLB_VSID_KS 0x0000000000000800ULL
42 #define SLB_VSID_KP 0x0000000000000400ULL
43 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
44 #define SLB_VSID_L 0x0000000000000100ULL
45 #define SLB_VSID_C 0x0000000000000080ULL /* class */
46 #define SLB_VSID_LP 0x0000000000000030ULL
47 #define SLB_VSID_ATTR 0x0000000000000FFFULL
48 #define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
49 #define SLB_VSID_4K 0x0000000000000000ULL
50 #define SLB_VSID_64K 0x0000000000000110ULL
51 #define SLB_VSID_16M 0x0000000000000100ULL
52 #define SLB_VSID_16G 0x0000000000000120ULL
53
54 /*
55 * Hash page table definitions
56 */
57
58 #define HPTES_PER_GROUP 8
59 #define HASH_PTE_SIZE_64 16
60 #define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
61
62 #define HPTE64_V_SSIZE_SHIFT 62
63 #define HPTE64_V_AVPN_SHIFT 7
64 #define HPTE64_V_AVPN 0x3fffffffffffff80ULL
65 #define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
66 #define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80ULL))
67 #define HPTE64_V_LARGE 0x0000000000000004ULL
68 #define HPTE64_V_SECONDARY 0x0000000000000002ULL
69 #define HPTE64_V_VALID 0x0000000000000001ULL
70
71 #define HPTE64_R_PP0 0x8000000000000000ULL
72 #define HPTE64_R_TS 0x4000000000000000ULL
73 #define HPTE64_R_KEY_HI 0x3000000000000000ULL
74 #define HPTE64_R_RPN_SHIFT 12
75 #define HPTE64_R_RPN 0x0ffffffffffff000ULL
76 #define HPTE64_R_FLAGS 0x00000000000003ffULL
77 #define HPTE64_R_PP 0x0000000000000003ULL
78 #define HPTE64_R_N 0x0000000000000004ULL
79 #define HPTE64_R_G 0x0000000000000008ULL
80 #define HPTE64_R_M 0x0000000000000010ULL
81 #define HPTE64_R_I 0x0000000000000020ULL
82 #define HPTE64_R_W 0x0000000000000040ULL
83 #define HPTE64_R_WIMG 0x0000000000000078ULL
84 #define HPTE64_R_C 0x0000000000000080ULL
85 #define HPTE64_R_R 0x0000000000000100ULL
86 #define HPTE64_R_KEY_LO 0x0000000000000e00ULL
87 #define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 60) | \
88 (((x) & HPTE64_R_KEY_LO) >> 9))
89
90 #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
91 #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
92
93 void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
94 Error **errp);
95 void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
96 Error **errp);
97
98 uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index);
99 void ppc_hash64_stop_access(PowerPCCPU *cpu, uint64_t token);
100
101 static inline target_ulong ppc_hash64_load_hpte0(PowerPCCPU *cpu,
102 uint64_t token, int index)
103 {
104 CPUPPCState *env = &cpu->env;
105 uint64_t addr;
106
107 addr = token + (index * HASH_PTE_SIZE_64);
108 if (env->external_htab) {
109 return ldq_p((const void *)(uintptr_t)addr);
110 } else {
111 return ldq_phys(CPU(cpu)->as, addr);
112 }
113 }
114
115 static inline target_ulong ppc_hash64_load_hpte1(PowerPCCPU *cpu,
116 uint64_t token, int index)
117 {
118 CPUPPCState *env = &cpu->env;
119 uint64_t addr;
120
121 addr = token + (index * HASH_PTE_SIZE_64) + HASH_PTE_SIZE_64/2;
122 if (env->external_htab) {
123 return ldq_p((const void *)(uintptr_t)addr);
124 } else {
125 return ldq_phys(CPU(cpu)->as, addr);
126 }
127 }
128
129 typedef struct {
130 uint64_t pte0, pte1;
131 } ppc_hash_pte64_t;
132
133 #endif /* CONFIG_USER_ONLY */
134
135 #endif /* !defined (__MMU_HASH64_H__) */