exec: Make ldl_*_phys input an AddressSpace
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Destination */
391 EXTRACT_HELPER(rD, 21, 5);
392 /* Source */
393 EXTRACT_HELPER(rS, 21, 5);
394 /* First operand */
395 EXTRACT_HELPER(rA, 16, 5);
396 /* Second operand */
397 EXTRACT_HELPER(rB, 11, 5);
398 /* Third operand */
399 EXTRACT_HELPER(rC, 6, 5);
400 /*** Get CRn ***/
401 EXTRACT_HELPER(crfD, 23, 3);
402 EXTRACT_HELPER(crfS, 18, 3);
403 EXTRACT_HELPER(crbD, 21, 5);
404 EXTRACT_HELPER(crbA, 16, 5);
405 EXTRACT_HELPER(crbB, 11, 5);
406 /* SPR / TBL */
407 EXTRACT_HELPER(_SPR, 11, 10);
408 static inline uint32_t SPR(uint32_t opcode)
409 {
410 uint32_t sprn = _SPR(opcode);
411
412 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
413 }
414 /*** Get constants ***/
415 EXTRACT_HELPER(IMM, 12, 8);
416 /* 16 bits signed immediate value */
417 EXTRACT_SHELPER(SIMM, 0, 16);
418 /* 16 bits unsigned immediate value */
419 EXTRACT_HELPER(UIMM, 0, 16);
420 /* 5 bits signed immediate value */
421 EXTRACT_HELPER(SIMM5, 16, 5);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(UIMM5, 16, 5);
424 /* Bit count */
425 EXTRACT_HELPER(NB, 11, 5);
426 /* Shift count */
427 EXTRACT_HELPER(SH, 11, 5);
428 /* Vector shift count */
429 EXTRACT_HELPER(VSH, 6, 4);
430 /* Mask start */
431 EXTRACT_HELPER(MB, 6, 5);
432 /* Mask end */
433 EXTRACT_HELPER(ME, 1, 5);
434 /* Trap operand */
435 EXTRACT_HELPER(TO, 21, 5);
436
437 EXTRACT_HELPER(CRM, 12, 8);
438 EXTRACT_HELPER(SR, 16, 4);
439
440 /* mtfsf/mtfsfi */
441 EXTRACT_HELPER(FPBF, 23, 3);
442 EXTRACT_HELPER(FPIMM, 12, 4);
443 EXTRACT_HELPER(FPL, 25, 1);
444 EXTRACT_HELPER(FPFLM, 17, 8);
445 EXTRACT_HELPER(FPW, 16, 1);
446
447 /*** Jump target decoding ***/
448 /* Displacement */
449 EXTRACT_SHELPER(d, 0, 16);
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* Create a mask between <start> and <end> bits */
469 static inline target_ulong MASK(uint32_t start, uint32_t end)
470 {
471 target_ulong ret;
472
473 #if defined(TARGET_PPC64)
474 if (likely(start == 0)) {
475 ret = UINT64_MAX << (63 - end);
476 } else if (likely(end == 63)) {
477 ret = UINT64_MAX >> start;
478 }
479 #else
480 if (likely(start == 0)) {
481 ret = UINT32_MAX << (31 - end);
482 } else if (likely(end == 31)) {
483 ret = UINT32_MAX >> start;
484 }
485 #endif
486 else {
487 ret = (((target_ulong)(-1ULL)) >> (start)) ^
488 (((target_ulong)(-1ULL) >> (end)) >> 1);
489 if (unlikely(start > end))
490 return ~ret;
491 }
492
493 return ret;
494 }
495
496 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
497 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
498 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
499 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
500 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
501 EXTRACT_HELPER(DM, 8, 2);
502 EXTRACT_HELPER(UIM, 16, 2);
503 EXTRACT_HELPER(SHW, 8, 2);
504 /*****************************************************************************/
505 /* PowerPC instructions table */
506
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
509 { \
510 .opc1 = op1, \
511 .opc2 = op2, \
512 .opc3 = op3, \
513 .pad = { 0, }, \
514 .handler = { \
515 .inval1 = invl, \
516 .type = _typ, \
517 .type2 = _typ2, \
518 .handler = &gen_##name, \
519 .oname = stringify(name), \
520 }, \
521 .oname = stringify(name), \
522 }
523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl1, \
531 .inval2 = invl2, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = onam, \
551 }, \
552 .oname = onam, \
553 }
554 #else
555 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl1, \
577 .inval2 = invl2, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = onam, \
597 }
598 #endif
599
600 /* SPR load/store helpers */
601 static inline void gen_load_spr(TCGv t, int reg)
602 {
603 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
604 }
605
606 static inline void gen_store_spr(int reg, TCGv t)
607 {
608 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
609 }
610
611 /* Invalid instruction */
612 static void gen_invalid(DisasContext *ctx)
613 {
614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
615 }
616
617 static opc_handler_t invalid_handler = {
618 .inval1 = 0xFFFFFFFF,
619 .inval2 = 0xFFFFFFFF,
620 .type = PPC_NONE,
621 .type2 = PPC_NONE,
622 .handler = gen_invalid,
623 };
624
625 /*** Integer comparison ***/
626
627 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0 = tcg_temp_new();
630 TCGv_i32 t1 = tcg_temp_new_i32();
631
632 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
633
634 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
635 tcg_gen_trunc_tl_i32(t1, t0);
636 tcg_gen_shli_i32(t1, t1, CRF_LT);
637 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
638
639 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
640 tcg_gen_trunc_tl_i32(t1, t0);
641 tcg_gen_shli_i32(t1, t1, CRF_GT);
642 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
643
644 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
645 tcg_gen_trunc_tl_i32(t1, t0);
646 tcg_gen_shli_i32(t1, t1, CRF_EQ);
647 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
648
649 tcg_temp_free(t0);
650 tcg_temp_free_i32(t1);
651 }
652
653 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
654 {
655 TCGv t0 = tcg_const_tl(arg1);
656 gen_op_cmp(arg0, t0, s, crf);
657 tcg_temp_free(t0);
658 }
659
660 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
661 {
662 TCGv t0, t1;
663 t0 = tcg_temp_new();
664 t1 = tcg_temp_new();
665 if (s) {
666 tcg_gen_ext32s_tl(t0, arg0);
667 tcg_gen_ext32s_tl(t1, arg1);
668 } else {
669 tcg_gen_ext32u_tl(t0, arg0);
670 tcg_gen_ext32u_tl(t1, arg1);
671 }
672 gen_op_cmp(t0, t1, s, crf);
673 tcg_temp_free(t1);
674 tcg_temp_free(t0);
675 }
676
677 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
678 {
679 TCGv t0 = tcg_const_tl(arg1);
680 gen_op_cmp32(arg0, t0, s, crf);
681 tcg_temp_free(t0);
682 }
683
684 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
685 {
686 if (NARROW_MODE(ctx)) {
687 gen_op_cmpi32(reg, 0, 1, 0);
688 } else {
689 gen_op_cmpi(reg, 0, 1, 0);
690 }
691 }
692
693 /* cmp */
694 static void gen_cmp(DisasContext *ctx)
695 {
696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 1, crfD(ctx->opcode));
699 } else {
700 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
701 1, crfD(ctx->opcode));
702 }
703 }
704
705 /* cmpi */
706 static void gen_cmpi(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
710 1, crfD(ctx->opcode));
711 } else {
712 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
713 1, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpl */
718 static void gen_cmpl(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
722 0, crfD(ctx->opcode));
723 } else {
724 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
725 0, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmpli */
730 static void gen_cmpli(DisasContext *ctx)
731 {
732 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
733 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
734 0, crfD(ctx->opcode));
735 } else {
736 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
737 0, crfD(ctx->opcode));
738 }
739 }
740
741 /* isel (PowerPC 2.03 specification) */
742 static void gen_isel(DisasContext *ctx)
743 {
744 int l1, l2;
745 uint32_t bi = rC(ctx->opcode);
746 uint32_t mask;
747 TCGv_i32 t0;
748
749 l1 = gen_new_label();
750 l2 = gen_new_label();
751
752 mask = 1 << (3 - (bi & 0x03));
753 t0 = tcg_temp_new_i32();
754 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
755 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
756 if (rA(ctx->opcode) == 0)
757 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
758 else
759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
760 tcg_gen_br(l2);
761 gen_set_label(l1);
762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
763 gen_set_label(l2);
764 tcg_temp_free_i32(t0);
765 }
766
767 /* cmpb: PowerPC 2.05 specification */
768 static void gen_cmpb(DisasContext *ctx)
769 {
770 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
771 cpu_gpr[rB(ctx->opcode)]);
772 }
773
774 /*** Integer arithmetic ***/
775
776 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
777 TCGv arg1, TCGv arg2, int sub)
778 {
779 TCGv t0 = tcg_temp_new();
780
781 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
782 tcg_gen_xor_tl(t0, arg1, arg2);
783 if (sub) {
784 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
785 } else {
786 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
787 }
788 tcg_temp_free(t0);
789 if (NARROW_MODE(ctx)) {
790 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
791 }
792 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
793 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
794 }
795
796 /* Common add function */
797 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
798 TCGv arg2, bool add_ca, bool compute_ca,
799 bool compute_ov, bool compute_rc0)
800 {
801 TCGv t0 = ret;
802
803 if (compute_ca || compute_ov) {
804 t0 = tcg_temp_new();
805 }
806
807 if (compute_ca) {
808 if (NARROW_MODE(ctx)) {
809 /* Caution: a non-obvious corner case of the spec is that we
810 must produce the *entire* 64-bit addition, but produce the
811 carry into bit 32. */
812 TCGv t1 = tcg_temp_new();
813 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
814 tcg_gen_add_tl(t0, arg1, arg2);
815 if (add_ca) {
816 tcg_gen_add_tl(t0, t0, cpu_ca);
817 }
818 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
819 tcg_temp_free(t1);
820 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
821 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
822 } else {
823 TCGv zero = tcg_const_tl(0);
824 if (add_ca) {
825 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
826 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
827 } else {
828 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
829 }
830 tcg_temp_free(zero);
831 }
832 } else {
833 tcg_gen_add_tl(t0, arg1, arg2);
834 if (add_ca) {
835 tcg_gen_add_tl(t0, t0, cpu_ca);
836 }
837 }
838
839 if (compute_ov) {
840 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
841 }
842 if (unlikely(compute_rc0)) {
843 gen_set_Rc0(ctx, t0);
844 }
845
846 if (!TCGV_EQUAL(t0, ret)) {
847 tcg_gen_mov_tl(ret, t0);
848 tcg_temp_free(t0);
849 }
850 }
851 /* Add functions with two operands */
852 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
853 static void glue(gen_, name)(DisasContext *ctx) \
854 { \
855 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
856 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
857 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
858 }
859 /* Add functions with one operand and one immediate */
860 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
861 add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 TCGv t0 = tcg_const_tl(const_val); \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], t0, \
867 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 tcg_temp_free(t0); \
869 }
870
871 /* add add. addo addo. */
872 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
873 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
874 /* addc addc. addco addco. */
875 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
876 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
877 /* adde adde. addeo addeo. */
878 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
879 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
880 /* addme addme. addmeo addmeo. */
881 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
882 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
883 /* addze addze. addzeo addzeo.*/
884 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
885 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
886 /* addi */
887 static void gen_addi(DisasContext *ctx)
888 {
889 target_long simm = SIMM(ctx->opcode);
890
891 if (rA(ctx->opcode) == 0) {
892 /* li case */
893 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
894 } else {
895 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
896 cpu_gpr[rA(ctx->opcode)], simm);
897 }
898 }
899 /* addic addic.*/
900 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
901 {
902 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
903 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
904 c, 0, 1, 0, compute_rc0);
905 tcg_temp_free(c);
906 }
907
908 static void gen_addic(DisasContext *ctx)
909 {
910 gen_op_addic(ctx, 0);
911 }
912
913 static void gen_addic_(DisasContext *ctx)
914 {
915 gen_op_addic(ctx, 1);
916 }
917
918 /* addis */
919 static void gen_addis(DisasContext *ctx)
920 {
921 target_long simm = SIMM(ctx->opcode);
922
923 if (rA(ctx->opcode) == 0) {
924 /* lis case */
925 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
926 } else {
927 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
928 cpu_gpr[rA(ctx->opcode)], simm << 16);
929 }
930 }
931
932 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
933 TCGv arg2, int sign, int compute_ov)
934 {
935 int l1 = gen_new_label();
936 int l2 = gen_new_label();
937 TCGv_i32 t0 = tcg_temp_local_new_i32();
938 TCGv_i32 t1 = tcg_temp_local_new_i32();
939
940 tcg_gen_trunc_tl_i32(t0, arg1);
941 tcg_gen_trunc_tl_i32(t1, arg2);
942 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
943 if (sign) {
944 int l3 = gen_new_label();
945 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
946 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
947 gen_set_label(l3);
948 tcg_gen_div_i32(t0, t0, t1);
949 } else {
950 tcg_gen_divu_i32(t0, t0, t1);
951 }
952 if (compute_ov) {
953 tcg_gen_movi_tl(cpu_ov, 0);
954 }
955 tcg_gen_br(l2);
956 gen_set_label(l1);
957 if (sign) {
958 tcg_gen_sari_i32(t0, t0, 31);
959 } else {
960 tcg_gen_movi_i32(t0, 0);
961 }
962 if (compute_ov) {
963 tcg_gen_movi_tl(cpu_ov, 1);
964 tcg_gen_movi_tl(cpu_so, 1);
965 }
966 gen_set_label(l2);
967 tcg_gen_extu_i32_tl(ret, t0);
968 tcg_temp_free_i32(t0);
969 tcg_temp_free_i32(t1);
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, ret);
972 }
973 /* Div functions */
974 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
975 static void glue(gen_, name)(DisasContext *ctx) \
976 { \
977 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 sign, compute_ov); \
980 }
981 /* divwu divwu. divwuo divwuo. */
982 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
983 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
984 /* divw divw. divwo divwo. */
985 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
986 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
987 #if defined(TARGET_PPC64)
988 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
989 TCGv arg2, int sign, int compute_ov)
990 {
991 int l1 = gen_new_label();
992 int l2 = gen_new_label();
993
994 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
995 if (sign) {
996 int l3 = gen_new_label();
997 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
998 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
999 gen_set_label(l3);
1000 tcg_gen_div_i64(ret, arg1, arg2);
1001 } else {
1002 tcg_gen_divu_i64(ret, arg1, arg2);
1003 }
1004 if (compute_ov) {
1005 tcg_gen_movi_tl(cpu_ov, 0);
1006 }
1007 tcg_gen_br(l2);
1008 gen_set_label(l1);
1009 if (sign) {
1010 tcg_gen_sari_i64(ret, arg1, 63);
1011 } else {
1012 tcg_gen_movi_i64(ret, 0);
1013 }
1014 if (compute_ov) {
1015 tcg_gen_movi_tl(cpu_ov, 1);
1016 tcg_gen_movi_tl(cpu_so, 1);
1017 }
1018 gen_set_label(l2);
1019 if (unlikely(Rc(ctx->opcode) != 0))
1020 gen_set_Rc0(ctx, ret);
1021 }
1022 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1023 static void glue(gen_, name)(DisasContext *ctx) \
1024 { \
1025 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1026 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1027 sign, compute_ov); \
1028 }
1029 /* divwu divwu. divwuo divwuo. */
1030 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1031 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1032 /* divw divw. divwo divwo. */
1033 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1034 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1035 #endif
1036
1037 /* mulhw mulhw. */
1038 static void gen_mulhw(DisasContext *ctx)
1039 {
1040 TCGv_i32 t0 = tcg_temp_new_i32();
1041 TCGv_i32 t1 = tcg_temp_new_i32();
1042
1043 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1044 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1045 tcg_gen_muls2_i32(t0, t1, t0, t1);
1046 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1047 tcg_temp_free_i32(t0);
1048 tcg_temp_free_i32(t1);
1049 if (unlikely(Rc(ctx->opcode) != 0))
1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1051 }
1052
1053 /* mulhwu mulhwu. */
1054 static void gen_mulhwu(DisasContext *ctx)
1055 {
1056 TCGv_i32 t0 = tcg_temp_new_i32();
1057 TCGv_i32 t1 = tcg_temp_new_i32();
1058
1059 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1060 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1061 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1062 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1063 tcg_temp_free_i32(t0);
1064 tcg_temp_free_i32(t1);
1065 if (unlikely(Rc(ctx->opcode) != 0))
1066 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1067 }
1068
1069 /* mullw mullw. */
1070 static void gen_mullw(DisasContext *ctx)
1071 {
1072 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1073 cpu_gpr[rB(ctx->opcode)]);
1074 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1075 if (unlikely(Rc(ctx->opcode) != 0))
1076 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1077 }
1078
1079 /* mullwo mullwo. */
1080 static void gen_mullwo(DisasContext *ctx)
1081 {
1082 TCGv_i32 t0 = tcg_temp_new_i32();
1083 TCGv_i32 t1 = tcg_temp_new_i32();
1084
1085 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1086 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1087 tcg_gen_muls2_i32(t0, t1, t0, t1);
1088 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1089
1090 tcg_gen_sari_i32(t0, t0, 31);
1091 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1092 tcg_gen_extu_i32_tl(cpu_ov, t0);
1093 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1094
1095 tcg_temp_free_i32(t0);
1096 tcg_temp_free_i32(t1);
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1099 }
1100
1101 /* mulli */
1102 static void gen_mulli(DisasContext *ctx)
1103 {
1104 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1105 SIMM(ctx->opcode));
1106 }
1107
1108 #if defined(TARGET_PPC64)
1109 /* mulhd mulhd. */
1110 static void gen_mulhd(DisasContext *ctx)
1111 {
1112 TCGv lo = tcg_temp_new();
1113 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1115 tcg_temp_free(lo);
1116 if (unlikely(Rc(ctx->opcode) != 0)) {
1117 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1118 }
1119 }
1120
1121 /* mulhdu mulhdu. */
1122 static void gen_mulhdu(DisasContext *ctx)
1123 {
1124 TCGv lo = tcg_temp_new();
1125 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1126 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1127 tcg_temp_free(lo);
1128 if (unlikely(Rc(ctx->opcode) != 0)) {
1129 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1130 }
1131 }
1132
1133 /* mulld mulld. */
1134 static void gen_mulld(DisasContext *ctx)
1135 {
1136 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1137 cpu_gpr[rB(ctx->opcode)]);
1138 if (unlikely(Rc(ctx->opcode) != 0))
1139 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1140 }
1141
1142 /* mulldo mulldo. */
1143 static void gen_mulldo(DisasContext *ctx)
1144 {
1145 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1146 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1147 if (unlikely(Rc(ctx->opcode) != 0)) {
1148 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1149 }
1150 }
1151 #endif
1152
1153 /* Common subf function */
1154 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1155 TCGv arg2, bool add_ca, bool compute_ca,
1156 bool compute_ov, bool compute_rc0)
1157 {
1158 TCGv t0 = ret;
1159
1160 if (compute_ca || compute_ov) {
1161 t0 = tcg_temp_new();
1162 }
1163
1164 if (compute_ca) {
1165 /* dest = ~arg1 + arg2 [+ ca]. */
1166 if (NARROW_MODE(ctx)) {
1167 /* Caution: a non-obvious corner case of the spec is that we
1168 must produce the *entire* 64-bit addition, but produce the
1169 carry into bit 32. */
1170 TCGv inv1 = tcg_temp_new();
1171 TCGv t1 = tcg_temp_new();
1172 tcg_gen_not_tl(inv1, arg1);
1173 if (add_ca) {
1174 tcg_gen_add_tl(t0, arg2, cpu_ca);
1175 } else {
1176 tcg_gen_addi_tl(t0, arg2, 1);
1177 }
1178 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1179 tcg_gen_add_tl(t0, t0, inv1);
1180 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1181 tcg_temp_free(t1);
1182 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1183 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1184 } else if (add_ca) {
1185 TCGv zero, inv1 = tcg_temp_new();
1186 tcg_gen_not_tl(inv1, arg1);
1187 zero = tcg_const_tl(0);
1188 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1189 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1190 tcg_temp_free(zero);
1191 tcg_temp_free(inv1);
1192 } else {
1193 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1194 tcg_gen_sub_tl(t0, arg2, arg1);
1195 }
1196 } else if (add_ca) {
1197 /* Since we're ignoring carry-out, we can simplify the
1198 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1199 tcg_gen_sub_tl(t0, arg2, arg1);
1200 tcg_gen_add_tl(t0, t0, cpu_ca);
1201 tcg_gen_subi_tl(t0, t0, 1);
1202 } else {
1203 tcg_gen_sub_tl(t0, arg2, arg1);
1204 }
1205
1206 if (compute_ov) {
1207 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1208 }
1209 if (unlikely(compute_rc0)) {
1210 gen_set_Rc0(ctx, t0);
1211 }
1212
1213 if (!TCGV_EQUAL(t0, ret)) {
1214 tcg_gen_mov_tl(ret, t0);
1215 tcg_temp_free(t0);
1216 }
1217 }
1218 /* Sub functions with Two operands functions */
1219 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1220 static void glue(gen_, name)(DisasContext *ctx) \
1221 { \
1222 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1223 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1224 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1225 }
1226 /* Sub functions with one operand and one immediate */
1227 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1228 add_ca, compute_ca, compute_ov) \
1229 static void glue(gen_, name)(DisasContext *ctx) \
1230 { \
1231 TCGv t0 = tcg_const_tl(const_val); \
1232 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1233 cpu_gpr[rA(ctx->opcode)], t0, \
1234 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1235 tcg_temp_free(t0); \
1236 }
1237 /* subf subf. subfo subfo. */
1238 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1239 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1240 /* subfc subfc. subfco subfco. */
1241 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1242 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1243 /* subfe subfe. subfeo subfo. */
1244 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1245 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1246 /* subfme subfme. subfmeo subfmeo. */
1247 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1248 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1249 /* subfze subfze. subfzeo subfzeo.*/
1250 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1251 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1252
1253 /* subfic */
1254 static void gen_subfic(DisasContext *ctx)
1255 {
1256 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1257 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1258 c, 0, 1, 0, 0);
1259 tcg_temp_free(c);
1260 }
1261
1262 /* neg neg. nego nego. */
1263 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1264 {
1265 TCGv zero = tcg_const_tl(0);
1266 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1267 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1268 tcg_temp_free(zero);
1269 }
1270
1271 static void gen_neg(DisasContext *ctx)
1272 {
1273 gen_op_arith_neg(ctx, 0);
1274 }
1275
1276 static void gen_nego(DisasContext *ctx)
1277 {
1278 gen_op_arith_neg(ctx, 1);
1279 }
1280
1281 /*** Integer logical ***/
1282 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1283 static void glue(gen_, name)(DisasContext *ctx) \
1284 { \
1285 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1286 cpu_gpr[rB(ctx->opcode)]); \
1287 if (unlikely(Rc(ctx->opcode) != 0)) \
1288 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1289 }
1290
1291 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1292 static void glue(gen_, name)(DisasContext *ctx) \
1293 { \
1294 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1295 if (unlikely(Rc(ctx->opcode) != 0)) \
1296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1297 }
1298
1299 /* and & and. */
1300 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1301 /* andc & andc. */
1302 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1303
1304 /* andi. */
1305 static void gen_andi_(DisasContext *ctx)
1306 {
1307 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1308 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1309 }
1310
1311 /* andis. */
1312 static void gen_andis_(DisasContext *ctx)
1313 {
1314 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1315 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1316 }
1317
1318 /* cntlzw */
1319 static void gen_cntlzw(DisasContext *ctx)
1320 {
1321 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1322 if (unlikely(Rc(ctx->opcode) != 0))
1323 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1324 }
1325 /* eqv & eqv. */
1326 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1327 /* extsb & extsb. */
1328 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1329 /* extsh & extsh. */
1330 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1331 /* nand & nand. */
1332 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1333 /* nor & nor. */
1334 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1335
1336 /* or & or. */
1337 static void gen_or(DisasContext *ctx)
1338 {
1339 int rs, ra, rb;
1340
1341 rs = rS(ctx->opcode);
1342 ra = rA(ctx->opcode);
1343 rb = rB(ctx->opcode);
1344 /* Optimisation for mr. ri case */
1345 if (rs != ra || rs != rb) {
1346 if (rs != rb)
1347 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1348 else
1349 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1350 if (unlikely(Rc(ctx->opcode) != 0))
1351 gen_set_Rc0(ctx, cpu_gpr[ra]);
1352 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1353 gen_set_Rc0(ctx, cpu_gpr[rs]);
1354 #if defined(TARGET_PPC64)
1355 } else {
1356 int prio = 0;
1357
1358 switch (rs) {
1359 case 1:
1360 /* Set process priority to low */
1361 prio = 2;
1362 break;
1363 case 6:
1364 /* Set process priority to medium-low */
1365 prio = 3;
1366 break;
1367 case 2:
1368 /* Set process priority to normal */
1369 prio = 4;
1370 break;
1371 #if !defined(CONFIG_USER_ONLY)
1372 case 31:
1373 if (ctx->mem_idx > 0) {
1374 /* Set process priority to very low */
1375 prio = 1;
1376 }
1377 break;
1378 case 5:
1379 if (ctx->mem_idx > 0) {
1380 /* Set process priority to medium-hight */
1381 prio = 5;
1382 }
1383 break;
1384 case 3:
1385 if (ctx->mem_idx > 0) {
1386 /* Set process priority to high */
1387 prio = 6;
1388 }
1389 break;
1390 case 7:
1391 if (ctx->mem_idx > 1) {
1392 /* Set process priority to very high */
1393 prio = 7;
1394 }
1395 break;
1396 #endif
1397 default:
1398 /* nop */
1399 break;
1400 }
1401 if (prio) {
1402 TCGv t0 = tcg_temp_new();
1403 gen_load_spr(t0, SPR_PPR);
1404 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1405 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1406 gen_store_spr(SPR_PPR, t0);
1407 tcg_temp_free(t0);
1408 }
1409 #endif
1410 }
1411 }
1412 /* orc & orc. */
1413 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1414
1415 /* xor & xor. */
1416 static void gen_xor(DisasContext *ctx)
1417 {
1418 /* Optimisation for "set to zero" case */
1419 if (rS(ctx->opcode) != rB(ctx->opcode))
1420 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1421 else
1422 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1423 if (unlikely(Rc(ctx->opcode) != 0))
1424 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1425 }
1426
1427 /* ori */
1428 static void gen_ori(DisasContext *ctx)
1429 {
1430 target_ulong uimm = UIMM(ctx->opcode);
1431
1432 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1433 /* NOP */
1434 /* XXX: should handle special NOPs for POWER series */
1435 return;
1436 }
1437 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1438 }
1439
1440 /* oris */
1441 static void gen_oris(DisasContext *ctx)
1442 {
1443 target_ulong uimm = UIMM(ctx->opcode);
1444
1445 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1446 /* NOP */
1447 return;
1448 }
1449 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1450 }
1451
1452 /* xori */
1453 static void gen_xori(DisasContext *ctx)
1454 {
1455 target_ulong uimm = UIMM(ctx->opcode);
1456
1457 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1458 /* NOP */
1459 return;
1460 }
1461 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1462 }
1463
1464 /* xoris */
1465 static void gen_xoris(DisasContext *ctx)
1466 {
1467 target_ulong uimm = UIMM(ctx->opcode);
1468
1469 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1470 /* NOP */
1471 return;
1472 }
1473 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1474 }
1475
1476 /* popcntb : PowerPC 2.03 specification */
1477 static void gen_popcntb(DisasContext *ctx)
1478 {
1479 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1480 }
1481
1482 static void gen_popcntw(DisasContext *ctx)
1483 {
1484 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1485 }
1486
1487 #if defined(TARGET_PPC64)
1488 /* popcntd: PowerPC 2.06 specification */
1489 static void gen_popcntd(DisasContext *ctx)
1490 {
1491 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1492 }
1493 #endif
1494
1495 /* prtyw: PowerPC 2.05 specification */
1496 static void gen_prtyw(DisasContext *ctx)
1497 {
1498 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1499 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1500 TCGv t0 = tcg_temp_new();
1501 tcg_gen_shri_tl(t0, rs, 16);
1502 tcg_gen_xor_tl(ra, rs, t0);
1503 tcg_gen_shri_tl(t0, ra, 8);
1504 tcg_gen_xor_tl(ra, ra, t0);
1505 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1506 tcg_temp_free(t0);
1507 }
1508
1509 #if defined(TARGET_PPC64)
1510 /* prtyd: PowerPC 2.05 specification */
1511 static void gen_prtyd(DisasContext *ctx)
1512 {
1513 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1514 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1515 TCGv t0 = tcg_temp_new();
1516 tcg_gen_shri_tl(t0, rs, 32);
1517 tcg_gen_xor_tl(ra, rs, t0);
1518 tcg_gen_shri_tl(t0, ra, 16);
1519 tcg_gen_xor_tl(ra, ra, t0);
1520 tcg_gen_shri_tl(t0, ra, 8);
1521 tcg_gen_xor_tl(ra, ra, t0);
1522 tcg_gen_andi_tl(ra, ra, 1);
1523 tcg_temp_free(t0);
1524 }
1525 #endif
1526
1527 #if defined(TARGET_PPC64)
1528 /* extsw & extsw. */
1529 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1530
1531 /* cntlzd */
1532 static void gen_cntlzd(DisasContext *ctx)
1533 {
1534 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1535 if (unlikely(Rc(ctx->opcode) != 0))
1536 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1537 }
1538 #endif
1539
1540 /*** Integer rotate ***/
1541
1542 /* rlwimi & rlwimi. */
1543 static void gen_rlwimi(DisasContext *ctx)
1544 {
1545 uint32_t mb, me, sh;
1546
1547 mb = MB(ctx->opcode);
1548 me = ME(ctx->opcode);
1549 sh = SH(ctx->opcode);
1550 if (likely(sh == 0 && mb == 0 && me == 31)) {
1551 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1552 } else {
1553 target_ulong mask;
1554 TCGv t1;
1555 TCGv t0 = tcg_temp_new();
1556 #if defined(TARGET_PPC64)
1557 TCGv_i32 t2 = tcg_temp_new_i32();
1558 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1559 tcg_gen_rotli_i32(t2, t2, sh);
1560 tcg_gen_extu_i32_i64(t0, t2);
1561 tcg_temp_free_i32(t2);
1562 #else
1563 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1564 #endif
1565 #if defined(TARGET_PPC64)
1566 mb += 32;
1567 me += 32;
1568 #endif
1569 mask = MASK(mb, me);
1570 t1 = tcg_temp_new();
1571 tcg_gen_andi_tl(t0, t0, mask);
1572 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1573 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1574 tcg_temp_free(t0);
1575 tcg_temp_free(t1);
1576 }
1577 if (unlikely(Rc(ctx->opcode) != 0))
1578 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1579 }
1580
1581 /* rlwinm & rlwinm. */
1582 static void gen_rlwinm(DisasContext *ctx)
1583 {
1584 uint32_t mb, me, sh;
1585
1586 sh = SH(ctx->opcode);
1587 mb = MB(ctx->opcode);
1588 me = ME(ctx->opcode);
1589
1590 if (likely(mb == 0 && me == (31 - sh))) {
1591 if (likely(sh == 0)) {
1592 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1593 } else {
1594 TCGv t0 = tcg_temp_new();
1595 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1596 tcg_gen_shli_tl(t0, t0, sh);
1597 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1598 tcg_temp_free(t0);
1599 }
1600 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1601 TCGv t0 = tcg_temp_new();
1602 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1603 tcg_gen_shri_tl(t0, t0, mb);
1604 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1605 tcg_temp_free(t0);
1606 } else {
1607 TCGv t0 = tcg_temp_new();
1608 #if defined(TARGET_PPC64)
1609 TCGv_i32 t1 = tcg_temp_new_i32();
1610 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1611 tcg_gen_rotli_i32(t1, t1, sh);
1612 tcg_gen_extu_i32_i64(t0, t1);
1613 tcg_temp_free_i32(t1);
1614 #else
1615 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1616 #endif
1617 #if defined(TARGET_PPC64)
1618 mb += 32;
1619 me += 32;
1620 #endif
1621 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1622 tcg_temp_free(t0);
1623 }
1624 if (unlikely(Rc(ctx->opcode) != 0))
1625 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1626 }
1627
1628 /* rlwnm & rlwnm. */
1629 static void gen_rlwnm(DisasContext *ctx)
1630 {
1631 uint32_t mb, me;
1632 TCGv t0;
1633 #if defined(TARGET_PPC64)
1634 TCGv_i32 t1, t2;
1635 #endif
1636
1637 mb = MB(ctx->opcode);
1638 me = ME(ctx->opcode);
1639 t0 = tcg_temp_new();
1640 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1641 #if defined(TARGET_PPC64)
1642 t1 = tcg_temp_new_i32();
1643 t2 = tcg_temp_new_i32();
1644 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1645 tcg_gen_trunc_i64_i32(t2, t0);
1646 tcg_gen_rotl_i32(t1, t1, t2);
1647 tcg_gen_extu_i32_i64(t0, t1);
1648 tcg_temp_free_i32(t1);
1649 tcg_temp_free_i32(t2);
1650 #else
1651 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1652 #endif
1653 if (unlikely(mb != 0 || me != 31)) {
1654 #if defined(TARGET_PPC64)
1655 mb += 32;
1656 me += 32;
1657 #endif
1658 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1659 } else {
1660 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1661 }
1662 tcg_temp_free(t0);
1663 if (unlikely(Rc(ctx->opcode) != 0))
1664 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1665 }
1666
1667 #if defined(TARGET_PPC64)
1668 #define GEN_PPC64_R2(name, opc1, opc2) \
1669 static void glue(gen_, name##0)(DisasContext *ctx) \
1670 { \
1671 gen_##name(ctx, 0); \
1672 } \
1673 \
1674 static void glue(gen_, name##1)(DisasContext *ctx) \
1675 { \
1676 gen_##name(ctx, 1); \
1677 }
1678 #define GEN_PPC64_R4(name, opc1, opc2) \
1679 static void glue(gen_, name##0)(DisasContext *ctx) \
1680 { \
1681 gen_##name(ctx, 0, 0); \
1682 } \
1683 \
1684 static void glue(gen_, name##1)(DisasContext *ctx) \
1685 { \
1686 gen_##name(ctx, 0, 1); \
1687 } \
1688 \
1689 static void glue(gen_, name##2)(DisasContext *ctx) \
1690 { \
1691 gen_##name(ctx, 1, 0); \
1692 } \
1693 \
1694 static void glue(gen_, name##3)(DisasContext *ctx) \
1695 { \
1696 gen_##name(ctx, 1, 1); \
1697 }
1698
1699 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1700 uint32_t sh)
1701 {
1702 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1703 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1704 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1705 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1706 } else {
1707 TCGv t0 = tcg_temp_new();
1708 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1709 if (likely(mb == 0 && me == 63)) {
1710 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1711 } else {
1712 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1713 }
1714 tcg_temp_free(t0);
1715 }
1716 if (unlikely(Rc(ctx->opcode) != 0))
1717 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1718 }
1719 /* rldicl - rldicl. */
1720 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1721 {
1722 uint32_t sh, mb;
1723
1724 sh = SH(ctx->opcode) | (shn << 5);
1725 mb = MB(ctx->opcode) | (mbn << 5);
1726 gen_rldinm(ctx, mb, 63, sh);
1727 }
1728 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1729 /* rldicr - rldicr. */
1730 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1731 {
1732 uint32_t sh, me;
1733
1734 sh = SH(ctx->opcode) | (shn << 5);
1735 me = MB(ctx->opcode) | (men << 5);
1736 gen_rldinm(ctx, 0, me, sh);
1737 }
1738 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1739 /* rldic - rldic. */
1740 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1741 {
1742 uint32_t sh, mb;
1743
1744 sh = SH(ctx->opcode) | (shn << 5);
1745 mb = MB(ctx->opcode) | (mbn << 5);
1746 gen_rldinm(ctx, mb, 63 - sh, sh);
1747 }
1748 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1749
1750 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1751 {
1752 TCGv t0;
1753
1754 t0 = tcg_temp_new();
1755 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1756 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1757 if (unlikely(mb != 0 || me != 63)) {
1758 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1759 } else {
1760 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1761 }
1762 tcg_temp_free(t0);
1763 if (unlikely(Rc(ctx->opcode) != 0))
1764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1765 }
1766
1767 /* rldcl - rldcl. */
1768 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1769 {
1770 uint32_t mb;
1771
1772 mb = MB(ctx->opcode) | (mbn << 5);
1773 gen_rldnm(ctx, mb, 63);
1774 }
1775 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1776 /* rldcr - rldcr. */
1777 static inline void gen_rldcr(DisasContext *ctx, int men)
1778 {
1779 uint32_t me;
1780
1781 me = MB(ctx->opcode) | (men << 5);
1782 gen_rldnm(ctx, 0, me);
1783 }
1784 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1785 /* rldimi - rldimi. */
1786 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1787 {
1788 uint32_t sh, mb, me;
1789
1790 sh = SH(ctx->opcode) | (shn << 5);
1791 mb = MB(ctx->opcode) | (mbn << 5);
1792 me = 63 - sh;
1793 if (unlikely(sh == 0 && mb == 0)) {
1794 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1795 } else {
1796 TCGv t0, t1;
1797 target_ulong mask;
1798
1799 t0 = tcg_temp_new();
1800 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1801 t1 = tcg_temp_new();
1802 mask = MASK(mb, me);
1803 tcg_gen_andi_tl(t0, t0, mask);
1804 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1805 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1806 tcg_temp_free(t0);
1807 tcg_temp_free(t1);
1808 }
1809 if (unlikely(Rc(ctx->opcode) != 0))
1810 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1811 }
1812 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1813 #endif
1814
1815 /*** Integer shift ***/
1816
1817 /* slw & slw. */
1818 static void gen_slw(DisasContext *ctx)
1819 {
1820 TCGv t0, t1;
1821
1822 t0 = tcg_temp_new();
1823 /* AND rS with a mask that is 0 when rB >= 0x20 */
1824 #if defined(TARGET_PPC64)
1825 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1826 tcg_gen_sari_tl(t0, t0, 0x3f);
1827 #else
1828 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1829 tcg_gen_sari_tl(t0, t0, 0x1f);
1830 #endif
1831 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1832 t1 = tcg_temp_new();
1833 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1834 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1835 tcg_temp_free(t1);
1836 tcg_temp_free(t0);
1837 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1838 if (unlikely(Rc(ctx->opcode) != 0))
1839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1840 }
1841
1842 /* sraw & sraw. */
1843 static void gen_sraw(DisasContext *ctx)
1844 {
1845 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1846 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1847 if (unlikely(Rc(ctx->opcode) != 0))
1848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1849 }
1850
1851 /* srawi & srawi. */
1852 static void gen_srawi(DisasContext *ctx)
1853 {
1854 int sh = SH(ctx->opcode);
1855 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1856 TCGv src = cpu_gpr[rS(ctx->opcode)];
1857 if (sh == 0) {
1858 tcg_gen_mov_tl(dst, src);
1859 tcg_gen_movi_tl(cpu_ca, 0);
1860 } else {
1861 TCGv t0;
1862 tcg_gen_ext32s_tl(dst, src);
1863 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1864 t0 = tcg_temp_new();
1865 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1866 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1867 tcg_temp_free(t0);
1868 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1869 tcg_gen_sari_tl(dst, dst, sh);
1870 }
1871 if (unlikely(Rc(ctx->opcode) != 0)) {
1872 gen_set_Rc0(ctx, dst);
1873 }
1874 }
1875
1876 /* srw & srw. */
1877 static void gen_srw(DisasContext *ctx)
1878 {
1879 TCGv t0, t1;
1880
1881 t0 = tcg_temp_new();
1882 /* AND rS with a mask that is 0 when rB >= 0x20 */
1883 #if defined(TARGET_PPC64)
1884 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1885 tcg_gen_sari_tl(t0, t0, 0x3f);
1886 #else
1887 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1888 tcg_gen_sari_tl(t0, t0, 0x1f);
1889 #endif
1890 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1891 tcg_gen_ext32u_tl(t0, t0);
1892 t1 = tcg_temp_new();
1893 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1894 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1895 tcg_temp_free(t1);
1896 tcg_temp_free(t0);
1897 if (unlikely(Rc(ctx->opcode) != 0))
1898 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1899 }
1900
1901 #if defined(TARGET_PPC64)
1902 /* sld & sld. */
1903 static void gen_sld(DisasContext *ctx)
1904 {
1905 TCGv t0, t1;
1906
1907 t0 = tcg_temp_new();
1908 /* AND rS with a mask that is 0 when rB >= 0x40 */
1909 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1910 tcg_gen_sari_tl(t0, t0, 0x3f);
1911 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1912 t1 = tcg_temp_new();
1913 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1914 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1915 tcg_temp_free(t1);
1916 tcg_temp_free(t0);
1917 if (unlikely(Rc(ctx->opcode) != 0))
1918 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1919 }
1920
1921 /* srad & srad. */
1922 static void gen_srad(DisasContext *ctx)
1923 {
1924 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1925 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1926 if (unlikely(Rc(ctx->opcode) != 0))
1927 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1928 }
1929 /* sradi & sradi. */
1930 static inline void gen_sradi(DisasContext *ctx, int n)
1931 {
1932 int sh = SH(ctx->opcode) + (n << 5);
1933 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1934 TCGv src = cpu_gpr[rS(ctx->opcode)];
1935 if (sh == 0) {
1936 tcg_gen_mov_tl(dst, src);
1937 tcg_gen_movi_tl(cpu_ca, 0);
1938 } else {
1939 TCGv t0;
1940 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1941 t0 = tcg_temp_new();
1942 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1943 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1944 tcg_temp_free(t0);
1945 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1946 tcg_gen_sari_tl(dst, src, sh);
1947 }
1948 if (unlikely(Rc(ctx->opcode) != 0)) {
1949 gen_set_Rc0(ctx, dst);
1950 }
1951 }
1952
1953 static void gen_sradi0(DisasContext *ctx)
1954 {
1955 gen_sradi(ctx, 0);
1956 }
1957
1958 static void gen_sradi1(DisasContext *ctx)
1959 {
1960 gen_sradi(ctx, 1);
1961 }
1962
1963 /* srd & srd. */
1964 static void gen_srd(DisasContext *ctx)
1965 {
1966 TCGv t0, t1;
1967
1968 t0 = tcg_temp_new();
1969 /* AND rS with a mask that is 0 when rB >= 0x40 */
1970 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1971 tcg_gen_sari_tl(t0, t0, 0x3f);
1972 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1973 t1 = tcg_temp_new();
1974 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1975 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1976 tcg_temp_free(t1);
1977 tcg_temp_free(t0);
1978 if (unlikely(Rc(ctx->opcode) != 0))
1979 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1980 }
1981 #endif
1982
1983 /*** Floating-Point arithmetic ***/
1984 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1985 static void gen_f##name(DisasContext *ctx) \
1986 { \
1987 if (unlikely(!ctx->fpu_enabled)) { \
1988 gen_exception(ctx, POWERPC_EXCP_FPU); \
1989 return; \
1990 } \
1991 /* NIP cannot be restored if the memory exception comes from an helper */ \
1992 gen_update_nip(ctx, ctx->nip - 4); \
1993 gen_reset_fpstatus(); \
1994 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1995 cpu_fpr[rA(ctx->opcode)], \
1996 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1997 if (isfloat) { \
1998 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1999 cpu_fpr[rD(ctx->opcode)]); \
2000 } \
2001 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2002 Rc(ctx->opcode) != 0); \
2003 }
2004
2005 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2006 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2007 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2008
2009 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2010 static void gen_f##name(DisasContext *ctx) \
2011 { \
2012 if (unlikely(!ctx->fpu_enabled)) { \
2013 gen_exception(ctx, POWERPC_EXCP_FPU); \
2014 return; \
2015 } \
2016 /* NIP cannot be restored if the memory exception comes from an helper */ \
2017 gen_update_nip(ctx, ctx->nip - 4); \
2018 gen_reset_fpstatus(); \
2019 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2020 cpu_fpr[rA(ctx->opcode)], \
2021 cpu_fpr[rB(ctx->opcode)]); \
2022 if (isfloat) { \
2023 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2024 cpu_fpr[rD(ctx->opcode)]); \
2025 } \
2026 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2027 set_fprf, Rc(ctx->opcode) != 0); \
2028 }
2029 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2030 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2031 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2032
2033 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2034 static void gen_f##name(DisasContext *ctx) \
2035 { \
2036 if (unlikely(!ctx->fpu_enabled)) { \
2037 gen_exception(ctx, POWERPC_EXCP_FPU); \
2038 return; \
2039 } \
2040 /* NIP cannot be restored if the memory exception comes from an helper */ \
2041 gen_update_nip(ctx, ctx->nip - 4); \
2042 gen_reset_fpstatus(); \
2043 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2044 cpu_fpr[rA(ctx->opcode)], \
2045 cpu_fpr[rC(ctx->opcode)]); \
2046 if (isfloat) { \
2047 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2048 cpu_fpr[rD(ctx->opcode)]); \
2049 } \
2050 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2051 set_fprf, Rc(ctx->opcode) != 0); \
2052 }
2053 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2054 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2055 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2056
2057 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2058 static void gen_f##name(DisasContext *ctx) \
2059 { \
2060 if (unlikely(!ctx->fpu_enabled)) { \
2061 gen_exception(ctx, POWERPC_EXCP_FPU); \
2062 return; \
2063 } \
2064 /* NIP cannot be restored if the memory exception comes from an helper */ \
2065 gen_update_nip(ctx, ctx->nip - 4); \
2066 gen_reset_fpstatus(); \
2067 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rB(ctx->opcode)]); \
2069 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2070 set_fprf, Rc(ctx->opcode) != 0); \
2071 }
2072
2073 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2074 static void gen_f##name(DisasContext *ctx) \
2075 { \
2076 if (unlikely(!ctx->fpu_enabled)) { \
2077 gen_exception(ctx, POWERPC_EXCP_FPU); \
2078 return; \
2079 } \
2080 /* NIP cannot be restored if the memory exception comes from an helper */ \
2081 gen_update_nip(ctx, ctx->nip - 4); \
2082 gen_reset_fpstatus(); \
2083 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2084 cpu_fpr[rB(ctx->opcode)]); \
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2086 set_fprf, Rc(ctx->opcode) != 0); \
2087 }
2088
2089 /* fadd - fadds */
2090 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2091 /* fdiv - fdivs */
2092 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2093 /* fmul - fmuls */
2094 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2095
2096 /* fre */
2097 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2098
2099 /* fres */
2100 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2101
2102 /* frsqrte */
2103 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2104
2105 /* frsqrtes */
2106 static void gen_frsqrtes(DisasContext *ctx)
2107 {
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2116 cpu_fpr[rB(ctx->opcode)]);
2117 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2118 cpu_fpr[rD(ctx->opcode)]);
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2120 }
2121
2122 /* fsel */
2123 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2124 /* fsub - fsubs */
2125 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2126 /* Optional: */
2127
2128 /* fsqrt */
2129 static void gen_fsqrt(DisasContext *ctx)
2130 {
2131 if (unlikely(!ctx->fpu_enabled)) {
2132 gen_exception(ctx, POWERPC_EXCP_FPU);
2133 return;
2134 }
2135 /* NIP cannot be restored if the memory exception comes from an helper */
2136 gen_update_nip(ctx, ctx->nip - 4);
2137 gen_reset_fpstatus();
2138 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2139 cpu_fpr[rB(ctx->opcode)]);
2140 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2141 }
2142
2143 static void gen_fsqrts(DisasContext *ctx)
2144 {
2145 if (unlikely(!ctx->fpu_enabled)) {
2146 gen_exception(ctx, POWERPC_EXCP_FPU);
2147 return;
2148 }
2149 /* NIP cannot be restored if the memory exception comes from an helper */
2150 gen_update_nip(ctx, ctx->nip - 4);
2151 gen_reset_fpstatus();
2152 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2153 cpu_fpr[rB(ctx->opcode)]);
2154 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2155 cpu_fpr[rD(ctx->opcode)]);
2156 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2157 }
2158
2159 /*** Floating-Point multiply-and-add ***/
2160 /* fmadd - fmadds */
2161 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2162 /* fmsub - fmsubs */
2163 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2164 /* fnmadd - fnmadds */
2165 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2166 /* fnmsub - fnmsubs */
2167 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2168
2169 /*** Floating-Point round & convert ***/
2170 /* fctiw */
2171 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2172 /* fctiwz */
2173 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2174 /* frsp */
2175 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2176 #if defined(TARGET_PPC64)
2177 /* fcfid */
2178 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2179 /* fctid */
2180 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2181 /* fctidz */
2182 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2183 #endif
2184
2185 /* frin */
2186 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2187 /* friz */
2188 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2189 /* frip */
2190 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2191 /* frim */
2192 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2193
2194 /*** Floating-Point compare ***/
2195
2196 /* fcmpo */
2197 static void gen_fcmpo(DisasContext *ctx)
2198 {
2199 TCGv_i32 crf;
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 /* NIP cannot be restored if the memory exception comes from an helper */
2205 gen_update_nip(ctx, ctx->nip - 4);
2206 gen_reset_fpstatus();
2207 crf = tcg_const_i32(crfD(ctx->opcode));
2208 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2209 cpu_fpr[rB(ctx->opcode)], crf);
2210 tcg_temp_free_i32(crf);
2211 gen_helper_float_check_status(cpu_env);
2212 }
2213
2214 /* fcmpu */
2215 static void gen_fcmpu(DisasContext *ctx)
2216 {
2217 TCGv_i32 crf;
2218 if (unlikely(!ctx->fpu_enabled)) {
2219 gen_exception(ctx, POWERPC_EXCP_FPU);
2220 return;
2221 }
2222 /* NIP cannot be restored if the memory exception comes from an helper */
2223 gen_update_nip(ctx, ctx->nip - 4);
2224 gen_reset_fpstatus();
2225 crf = tcg_const_i32(crfD(ctx->opcode));
2226 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2227 cpu_fpr[rB(ctx->opcode)], crf);
2228 tcg_temp_free_i32(crf);
2229 gen_helper_float_check_status(cpu_env);
2230 }
2231
2232 /*** Floating-point move ***/
2233 /* fabs */
2234 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2235 static void gen_fabs(DisasContext *ctx)
2236 {
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2242 ~(1ULL << 63));
2243 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2244 }
2245
2246 /* fmr - fmr. */
2247 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2248 static void gen_fmr(DisasContext *ctx)
2249 {
2250 if (unlikely(!ctx->fpu_enabled)) {
2251 gen_exception(ctx, POWERPC_EXCP_FPU);
2252 return;
2253 }
2254 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2255 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2256 }
2257
2258 /* fnabs */
2259 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2260 static void gen_fnabs(DisasContext *ctx)
2261 {
2262 if (unlikely(!ctx->fpu_enabled)) {
2263 gen_exception(ctx, POWERPC_EXCP_FPU);
2264 return;
2265 }
2266 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2267 1ULL << 63);
2268 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2269 }
2270
2271 /* fneg */
2272 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2273 static void gen_fneg(DisasContext *ctx)
2274 {
2275 if (unlikely(!ctx->fpu_enabled)) {
2276 gen_exception(ctx, POWERPC_EXCP_FPU);
2277 return;
2278 }
2279 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2280 1ULL << 63);
2281 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2282 }
2283
2284 /* fcpsgn: PowerPC 2.05 specification */
2285 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2286 static void gen_fcpsgn(DisasContext *ctx)
2287 {
2288 if (unlikely(!ctx->fpu_enabled)) {
2289 gen_exception(ctx, POWERPC_EXCP_FPU);
2290 return;
2291 }
2292 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2293 cpu_fpr[rB(ctx->opcode)], 0, 63);
2294 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2295 }
2296
2297 /*** Floating-Point status & ctrl register ***/
2298
2299 /* mcrfs */
2300 static void gen_mcrfs(DisasContext *ctx)
2301 {
2302 TCGv tmp = tcg_temp_new();
2303 int bfa;
2304
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 bfa = 4 * (7 - crfS(ctx->opcode));
2310 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2311 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2312 tcg_temp_free(tmp);
2313 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2314 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2315 }
2316
2317 /* mffs */
2318 static void gen_mffs(DisasContext *ctx)
2319 {
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_reset_fpstatus();
2325 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2326 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2327 }
2328
2329 /* mtfsb0 */
2330 static void gen_mtfsb0(DisasContext *ctx)
2331 {
2332 uint8_t crb;
2333
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 crb = 31 - crbD(ctx->opcode);
2339 gen_reset_fpstatus();
2340 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2341 TCGv_i32 t0;
2342 /* NIP cannot be restored if the memory exception comes from an helper */
2343 gen_update_nip(ctx, ctx->nip - 4);
2344 t0 = tcg_const_i32(crb);
2345 gen_helper_fpscr_clrbit(cpu_env, t0);
2346 tcg_temp_free_i32(t0);
2347 }
2348 if (unlikely(Rc(ctx->opcode) != 0)) {
2349 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2350 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2351 }
2352 }
2353
2354 /* mtfsb1 */
2355 static void gen_mtfsb1(DisasContext *ctx)
2356 {
2357 uint8_t crb;
2358
2359 if (unlikely(!ctx->fpu_enabled)) {
2360 gen_exception(ctx, POWERPC_EXCP_FPU);
2361 return;
2362 }
2363 crb = 31 - crbD(ctx->opcode);
2364 gen_reset_fpstatus();
2365 /* XXX: we pretend we can only do IEEE floating-point computations */
2366 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2367 TCGv_i32 t0;
2368 /* NIP cannot be restored if the memory exception comes from an helper */
2369 gen_update_nip(ctx, ctx->nip - 4);
2370 t0 = tcg_const_i32(crb);
2371 gen_helper_fpscr_setbit(cpu_env, t0);
2372 tcg_temp_free_i32(t0);
2373 }
2374 if (unlikely(Rc(ctx->opcode) != 0)) {
2375 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2376 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2377 }
2378 /* We can raise a differed exception */
2379 gen_helper_float_check_status(cpu_env);
2380 }
2381
2382 /* mtfsf */
2383 static void gen_mtfsf(DisasContext *ctx)
2384 {
2385 TCGv_i32 t0;
2386 int flm, l, w;
2387
2388 if (unlikely(!ctx->fpu_enabled)) {
2389 gen_exception(ctx, POWERPC_EXCP_FPU);
2390 return;
2391 }
2392 flm = FPFLM(ctx->opcode);
2393 l = FPL(ctx->opcode);
2394 w = FPW(ctx->opcode);
2395 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2396 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2397 return;
2398 }
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx, ctx->nip - 4);
2401 gen_reset_fpstatus();
2402 if (l) {
2403 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2404 } else {
2405 t0 = tcg_const_i32(flm << (w * 8));
2406 }
2407 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2408 tcg_temp_free_i32(t0);
2409 if (unlikely(Rc(ctx->opcode) != 0)) {
2410 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2411 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2412 }
2413 /* We can raise a differed exception */
2414 gen_helper_float_check_status(cpu_env);
2415 }
2416
2417 /* mtfsfi */
2418 static void gen_mtfsfi(DisasContext *ctx)
2419 {
2420 int bf, sh, w;
2421 TCGv_i64 t0;
2422 TCGv_i32 t1;
2423
2424 if (unlikely(!ctx->fpu_enabled)) {
2425 gen_exception(ctx, POWERPC_EXCP_FPU);
2426 return;
2427 }
2428 w = FPW(ctx->opcode);
2429 bf = FPBF(ctx->opcode);
2430 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2431 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2432 return;
2433 }
2434 sh = (8 * w) + 7 - bf;
2435 /* NIP cannot be restored if the memory exception comes from an helper */
2436 gen_update_nip(ctx, ctx->nip - 4);
2437 gen_reset_fpstatus();
2438 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2439 t1 = tcg_const_i32(1 << sh);
2440 gen_helper_store_fpscr(cpu_env, t0, t1);
2441 tcg_temp_free_i64(t0);
2442 tcg_temp_free_i32(t1);
2443 if (unlikely(Rc(ctx->opcode) != 0)) {
2444 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2445 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2446 }
2447 /* We can raise a differed exception */
2448 gen_helper_float_check_status(cpu_env);
2449 }
2450
2451 /*** Addressing modes ***/
2452 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2453 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2454 target_long maskl)
2455 {
2456 target_long simm = SIMM(ctx->opcode);
2457
2458 simm &= ~maskl;
2459 if (rA(ctx->opcode) == 0) {
2460 if (NARROW_MODE(ctx)) {
2461 simm = (uint32_t)simm;
2462 }
2463 tcg_gen_movi_tl(EA, simm);
2464 } else if (likely(simm != 0)) {
2465 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2466 if (NARROW_MODE(ctx)) {
2467 tcg_gen_ext32u_tl(EA, EA);
2468 }
2469 } else {
2470 if (NARROW_MODE(ctx)) {
2471 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2472 } else {
2473 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2474 }
2475 }
2476 }
2477
2478 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2479 {
2480 if (rA(ctx->opcode) == 0) {
2481 if (NARROW_MODE(ctx)) {
2482 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2483 } else {
2484 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2485 }
2486 } else {
2487 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2488 if (NARROW_MODE(ctx)) {
2489 tcg_gen_ext32u_tl(EA, EA);
2490 }
2491 }
2492 }
2493
2494 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2495 {
2496 if (rA(ctx->opcode) == 0) {
2497 tcg_gen_movi_tl(EA, 0);
2498 } else if (NARROW_MODE(ctx)) {
2499 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2500 } else {
2501 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2502 }
2503 }
2504
2505 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2506 target_long val)
2507 {
2508 tcg_gen_addi_tl(ret, arg1, val);
2509 if (NARROW_MODE(ctx)) {
2510 tcg_gen_ext32u_tl(ret, ret);
2511 }
2512 }
2513
2514 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2515 {
2516 int l1 = gen_new_label();
2517 TCGv t0 = tcg_temp_new();
2518 TCGv_i32 t1, t2;
2519 /* NIP cannot be restored if the memory exception comes from an helper */
2520 gen_update_nip(ctx, ctx->nip - 4);
2521 tcg_gen_andi_tl(t0, EA, mask);
2522 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2523 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2524 t2 = tcg_const_i32(0);
2525 gen_helper_raise_exception_err(cpu_env, t1, t2);
2526 tcg_temp_free_i32(t1);
2527 tcg_temp_free_i32(t2);
2528 gen_set_label(l1);
2529 tcg_temp_free(t0);
2530 }
2531
2532 /*** Integer load ***/
2533 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2534 {
2535 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2536 }
2537
2538 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2539 {
2540 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2541 }
2542
2543 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2544 {
2545 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2546 if (unlikely(ctx->le_mode)) {
2547 tcg_gen_bswap16_tl(arg1, arg1);
2548 }
2549 }
2550
2551 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552 {
2553 if (unlikely(ctx->le_mode)) {
2554 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2555 tcg_gen_bswap16_tl(arg1, arg1);
2556 tcg_gen_ext16s_tl(arg1, arg1);
2557 } else {
2558 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2559 }
2560 }
2561
2562 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2563 {
2564 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2565 if (unlikely(ctx->le_mode)) {
2566 tcg_gen_bswap32_tl(arg1, arg1);
2567 }
2568 }
2569
2570 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2571 {
2572 TCGv tmp = tcg_temp_new();
2573 gen_qemu_ld32u(ctx, tmp, addr);
2574 tcg_gen_extu_tl_i64(val, tmp);
2575 tcg_temp_free(tmp);
2576 }
2577
2578 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2579 {
2580 if (unlikely(ctx->le_mode)) {
2581 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2582 tcg_gen_bswap32_tl(arg1, arg1);
2583 tcg_gen_ext32s_tl(arg1, arg1);
2584 } else
2585 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2586 }
2587
2588 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2589 {
2590 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2591 if (unlikely(ctx->le_mode)) {
2592 tcg_gen_bswap64_i64(arg1, arg1);
2593 }
2594 }
2595
2596 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2597 {
2598 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2599 }
2600
2601 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2602 {
2603 if (unlikely(ctx->le_mode)) {
2604 TCGv t0 = tcg_temp_new();
2605 tcg_gen_ext16u_tl(t0, arg1);
2606 tcg_gen_bswap16_tl(t0, t0);
2607 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2608 tcg_temp_free(t0);
2609 } else {
2610 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2611 }
2612 }
2613
2614 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2615 {
2616 if (unlikely(ctx->le_mode)) {
2617 TCGv t0 = tcg_temp_new();
2618 tcg_gen_ext32u_tl(t0, arg1);
2619 tcg_gen_bswap32_tl(t0, t0);
2620 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2621 tcg_temp_free(t0);
2622 } else {
2623 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2624 }
2625 }
2626
2627 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2628 {
2629 TCGv tmp = tcg_temp_new();
2630 tcg_gen_trunc_i64_tl(tmp, val);
2631 gen_qemu_st32(ctx, tmp, addr);
2632 tcg_temp_free(tmp);
2633 }
2634
2635 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2636 {
2637 if (unlikely(ctx->le_mode)) {
2638 TCGv_i64 t0 = tcg_temp_new_i64();
2639 tcg_gen_bswap64_i64(t0, arg1);
2640 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2641 tcg_temp_free_i64(t0);
2642 } else
2643 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2644 }
2645
2646 #define GEN_LD(name, ldop, opc, type) \
2647 static void glue(gen_, name)(DisasContext *ctx) \
2648 { \
2649 TCGv EA; \
2650 gen_set_access_type(ctx, ACCESS_INT); \
2651 EA = tcg_temp_new(); \
2652 gen_addr_imm_index(ctx, EA, 0); \
2653 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2654 tcg_temp_free(EA); \
2655 }
2656
2657 #define GEN_LDU(name, ldop, opc, type) \
2658 static void glue(gen_, name##u)(DisasContext *ctx) \
2659 { \
2660 TCGv EA; \
2661 if (unlikely(rA(ctx->opcode) == 0 || \
2662 rA(ctx->opcode) == rD(ctx->opcode))) { \
2663 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2664 return; \
2665 } \
2666 gen_set_access_type(ctx, ACCESS_INT); \
2667 EA = tcg_temp_new(); \
2668 if (type == PPC_64B) \
2669 gen_addr_imm_index(ctx, EA, 0x03); \
2670 else \
2671 gen_addr_imm_index(ctx, EA, 0); \
2672 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2673 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2674 tcg_temp_free(EA); \
2675 }
2676
2677 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2678 static void glue(gen_, name##ux)(DisasContext *ctx) \
2679 { \
2680 TCGv EA; \
2681 if (unlikely(rA(ctx->opcode) == 0 || \
2682 rA(ctx->opcode) == rD(ctx->opcode))) { \
2683 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2684 return; \
2685 } \
2686 gen_set_access_type(ctx, ACCESS_INT); \
2687 EA = tcg_temp_new(); \
2688 gen_addr_reg_index(ctx, EA); \
2689 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2690 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2691 tcg_temp_free(EA); \
2692 }
2693
2694 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2695 static void glue(gen_, name##x)(DisasContext *ctx) \
2696 { \
2697 TCGv EA; \
2698 gen_set_access_type(ctx, ACCESS_INT); \
2699 EA = tcg_temp_new(); \
2700 gen_addr_reg_index(ctx, EA); \
2701 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2702 tcg_temp_free(EA); \
2703 }
2704 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2705 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2706
2707 #define GEN_LDS(name, ldop, op, type) \
2708 GEN_LD(name, ldop, op | 0x20, type); \
2709 GEN_LDU(name, ldop, op | 0x21, type); \
2710 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2711 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2712
2713 /* lbz lbzu lbzux lbzx */
2714 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2715 /* lha lhau lhaux lhax */
2716 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2717 /* lhz lhzu lhzux lhzx */
2718 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2719 /* lwz lwzu lwzux lwzx */
2720 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2721 #if defined(TARGET_PPC64)
2722 /* lwaux */
2723 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2724 /* lwax */
2725 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2726 /* ldux */
2727 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2728 /* ldx */
2729 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2730
2731 static void gen_ld(DisasContext *ctx)
2732 {
2733 TCGv EA;
2734 if (Rc(ctx->opcode)) {
2735 if (unlikely(rA(ctx->opcode) == 0 ||
2736 rA(ctx->opcode) == rD(ctx->opcode))) {
2737 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2738 return;
2739 }
2740 }
2741 gen_set_access_type(ctx, ACCESS_INT);
2742 EA = tcg_temp_new();
2743 gen_addr_imm_index(ctx, EA, 0x03);
2744 if (ctx->opcode & 0x02) {
2745 /* lwa (lwau is undefined) */
2746 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2747 } else {
2748 /* ld - ldu */
2749 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2750 }
2751 if (Rc(ctx->opcode))
2752 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2753 tcg_temp_free(EA);
2754 }
2755
2756 /* lq */
2757 static void gen_lq(DisasContext *ctx)
2758 {
2759 #if defined(CONFIG_USER_ONLY)
2760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2761 #else
2762 int ra, rd;
2763 TCGv EA;
2764
2765 /* Restore CPU state */
2766 if (unlikely(ctx->mem_idx == 0)) {
2767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2768 return;
2769 }
2770 ra = rA(ctx->opcode);
2771 rd = rD(ctx->opcode);
2772 if (unlikely((rd & 1) || rd == ra)) {
2773 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2774 return;
2775 }
2776 if (unlikely(ctx->le_mode)) {
2777 /* Little-endian mode is not handled */
2778 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2779 return;
2780 }
2781 gen_set_access_type(ctx, ACCESS_INT);
2782 EA = tcg_temp_new();
2783 gen_addr_imm_index(ctx, EA, 0x0F);
2784 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2785 gen_addr_add(ctx, EA, EA, 8);
2786 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2787 tcg_temp_free(EA);
2788 #endif
2789 }
2790 #endif
2791
2792 /*** Integer store ***/
2793 #define GEN_ST(name, stop, opc, type) \
2794 static void glue(gen_, name)(DisasContext *ctx) \
2795 { \
2796 TCGv EA; \
2797 gen_set_access_type(ctx, ACCESS_INT); \
2798 EA = tcg_temp_new(); \
2799 gen_addr_imm_index(ctx, EA, 0); \
2800 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2801 tcg_temp_free(EA); \
2802 }
2803
2804 #define GEN_STU(name, stop, opc, type) \
2805 static void glue(gen_, stop##u)(DisasContext *ctx) \
2806 { \
2807 TCGv EA; \
2808 if (unlikely(rA(ctx->opcode) == 0)) { \
2809 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2810 return; \
2811 } \
2812 gen_set_access_type(ctx, ACCESS_INT); \
2813 EA = tcg_temp_new(); \
2814 if (type == PPC_64B) \
2815 gen_addr_imm_index(ctx, EA, 0x03); \
2816 else \
2817 gen_addr_imm_index(ctx, EA, 0); \
2818 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2820 tcg_temp_free(EA); \
2821 }
2822
2823 #define GEN_STUX(name, stop, opc2, opc3, type) \
2824 static void glue(gen_, name##ux)(DisasContext *ctx) \
2825 { \
2826 TCGv EA; \
2827 if (unlikely(rA(ctx->opcode) == 0)) { \
2828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2829 return; \
2830 } \
2831 gen_set_access_type(ctx, ACCESS_INT); \
2832 EA = tcg_temp_new(); \
2833 gen_addr_reg_index(ctx, EA); \
2834 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2835 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2836 tcg_temp_free(EA); \
2837 }
2838
2839 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2840 static void glue(gen_, name##x)(DisasContext *ctx) \
2841 { \
2842 TCGv EA; \
2843 gen_set_access_type(ctx, ACCESS_INT); \
2844 EA = tcg_temp_new(); \
2845 gen_addr_reg_index(ctx, EA); \
2846 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2847 tcg_temp_free(EA); \
2848 }
2849 #define GEN_STX(name, stop, opc2, opc3, type) \
2850 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2851
2852 #define GEN_STS(name, stop, op, type) \
2853 GEN_ST(name, stop, op | 0x20, type); \
2854 GEN_STU(name, stop, op | 0x21, type); \
2855 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2856 GEN_STX(name, stop, 0x17, op | 0x00, type)
2857
2858 /* stb stbu stbux stbx */
2859 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2860 /* sth sthu sthux sthx */
2861 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2862 /* stw stwu stwux stwx */
2863 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2864 #if defined(TARGET_PPC64)
2865 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2866 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2867
2868 static void gen_std(DisasContext *ctx)
2869 {
2870 int rs;
2871 TCGv EA;
2872
2873 rs = rS(ctx->opcode);
2874 if ((ctx->opcode & 0x3) == 0x2) {
2875 #if defined(CONFIG_USER_ONLY)
2876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2877 #else
2878 /* stq */
2879 if (unlikely(ctx->mem_idx == 0)) {
2880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2881 return;
2882 }
2883 if (unlikely(rs & 1)) {
2884 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2885 return;
2886 }
2887 if (unlikely(ctx->le_mode)) {
2888 /* Little-endian mode is not handled */
2889 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2890 return;
2891 }
2892 gen_set_access_type(ctx, ACCESS_INT);
2893 EA = tcg_temp_new();
2894 gen_addr_imm_index(ctx, EA, 0x03);
2895 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2896 gen_addr_add(ctx, EA, EA, 8);
2897 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2898 tcg_temp_free(EA);
2899 #endif
2900 } else {
2901 /* std / stdu */
2902 if (Rc(ctx->opcode)) {
2903 if (unlikely(rA(ctx->opcode) == 0)) {
2904 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2905 return;
2906 }
2907 }
2908 gen_set_access_type(ctx, ACCESS_INT);
2909 EA = tcg_temp_new();
2910 gen_addr_imm_index(ctx, EA, 0x03);
2911 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2912 if (Rc(ctx->opcode))
2913 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2914 tcg_temp_free(EA);
2915 }
2916 }
2917 #endif
2918 /*** Integer load and store with byte reverse ***/
2919 /* lhbrx */
2920 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2921 {
2922 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2923 if (likely(!ctx->le_mode)) {
2924 tcg_gen_bswap16_tl(arg1, arg1);
2925 }
2926 }
2927 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2928
2929 /* lwbrx */
2930 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2931 {
2932 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2933 if (likely(!ctx->le_mode)) {
2934 tcg_gen_bswap32_tl(arg1, arg1);
2935 }
2936 }
2937 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2938
2939 #if defined(TARGET_PPC64)
2940 /* ldbrx */
2941 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2942 {
2943 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2944 if (likely(!ctx->le_mode)) {
2945 tcg_gen_bswap64_tl(arg1, arg1);
2946 }
2947 }
2948 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2949 #endif /* TARGET_PPC64 */
2950
2951 /* sthbrx */
2952 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2953 {
2954 if (likely(!ctx->le_mode)) {
2955 TCGv t0 = tcg_temp_new();
2956 tcg_gen_ext16u_tl(t0, arg1);
2957 tcg_gen_bswap16_tl(t0, t0);
2958 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2959 tcg_temp_free(t0);
2960 } else {
2961 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2962 }
2963 }
2964 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2965
2966 /* stwbrx */
2967 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2968 {
2969 if (likely(!ctx->le_mode)) {
2970 TCGv t0 = tcg_temp_new();
2971 tcg_gen_ext32u_tl(t0, arg1);
2972 tcg_gen_bswap32_tl(t0, t0);
2973 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2974 tcg_temp_free(t0);
2975 } else {
2976 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2977 }
2978 }
2979 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2980
2981 #if defined(TARGET_PPC64)
2982 /* stdbrx */
2983 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2984 {
2985 if (likely(!ctx->le_mode)) {
2986 TCGv t0 = tcg_temp_new();
2987 tcg_gen_bswap64_tl(t0, arg1);
2988 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2989 tcg_temp_free(t0);
2990 } else {
2991 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2992 }
2993 }
2994 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2995 #endif /* TARGET_PPC64 */
2996
2997 /*** Integer load and store multiple ***/
2998
2999 /* lmw */
3000 static void gen_lmw(DisasContext *ctx)
3001 {
3002 TCGv t0;
3003 TCGv_i32 t1;
3004 gen_set_access_type(ctx, ACCESS_INT);
3005 /* NIP cannot be restored if the memory exception comes from an helper */
3006 gen_update_nip(ctx, ctx->nip - 4);
3007 t0 = tcg_temp_new();
3008 t1 = tcg_const_i32(rD(ctx->opcode));
3009 gen_addr_imm_index(ctx, t0, 0);
3010 gen_helper_lmw(cpu_env, t0, t1);
3011 tcg_temp_free(t0);
3012 tcg_temp_free_i32(t1);
3013 }
3014
3015 /* stmw */
3016 static void gen_stmw(DisasContext *ctx)
3017 {
3018 TCGv t0;
3019 TCGv_i32 t1;
3020 gen_set_access_type(ctx, ACCESS_INT);
3021 /* NIP cannot be restored if the memory exception comes from an helper */
3022 gen_update_nip(ctx, ctx->nip - 4);
3023 t0 = tcg_temp_new();
3024 t1 = tcg_const_i32(rS(ctx->opcode));
3025 gen_addr_imm_index(ctx, t0, 0);
3026 gen_helper_stmw(cpu_env, t0, t1);
3027 tcg_temp_free(t0);
3028 tcg_temp_free_i32(t1);
3029 }
3030
3031 /*** Integer load and store strings ***/
3032
3033 /* lswi */
3034 /* PowerPC32 specification says we must generate an exception if
3035 * rA is in the range of registers to be loaded.
3036 * In an other hand, IBM says this is valid, but rA won't be loaded.
3037 * For now, I'll follow the spec...
3038 */
3039 static void gen_lswi(DisasContext *ctx)
3040 {
3041 TCGv t0;
3042 TCGv_i32 t1, t2;
3043 int nb = NB(ctx->opcode);
3044 int start = rD(ctx->opcode);
3045 int ra = rA(ctx->opcode);
3046 int nr;
3047
3048 if (nb == 0)
3049 nb = 32;
3050 nr = nb / 4;
3051 if (unlikely(((start + nr) > 32 &&
3052 start <= ra && (start + nr - 32) > ra) ||
3053 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3055 return;
3056 }
3057 gen_set_access_type(ctx, ACCESS_INT);
3058 /* NIP cannot be restored if the memory exception comes from an helper */
3059 gen_update_nip(ctx, ctx->nip - 4);
3060 t0 = tcg_temp_new();
3061 gen_addr_register(ctx, t0);
3062 t1 = tcg_const_i32(nb);
3063 t2 = tcg_const_i32(start);
3064 gen_helper_lsw(cpu_env, t0, t1, t2);
3065 tcg_temp_free(t0);
3066 tcg_temp_free_i32(t1);
3067 tcg_temp_free_i32(t2);
3068 }
3069
3070 /* lswx */
3071 static void gen_lswx(DisasContext *ctx)
3072 {
3073 TCGv t0;
3074 TCGv_i32 t1, t2, t3;
3075 gen_set_access_type(ctx, ACCESS_INT);
3076 /* NIP cannot be restored if the memory exception comes from an helper */
3077 gen_update_nip(ctx, ctx->nip - 4);
3078 t0 = tcg_temp_new();
3079 gen_addr_reg_index(ctx, t0);
3080 t1 = tcg_const_i32(rD(ctx->opcode));
3081 t2 = tcg_const_i32(rA(ctx->opcode));
3082 t3 = tcg_const_i32(rB(ctx->opcode));
3083 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3084 tcg_temp_free(t0);
3085 tcg_temp_free_i32(t1);
3086 tcg_temp_free_i32(t2);
3087 tcg_temp_free_i32(t3);
3088 }
3089
3090 /* stswi */
3091 static void gen_stswi(DisasContext *ctx)
3092 {
3093 TCGv t0;
3094 TCGv_i32 t1, t2;
3095 int nb = NB(ctx->opcode);
3096 gen_set_access_type(ctx, ACCESS_INT);
3097 /* NIP cannot be restored if the memory exception comes from an helper */
3098 gen_update_nip(ctx, ctx->nip - 4);
3099 t0 = tcg_temp_new();
3100 gen_addr_register(ctx, t0);
3101 if (nb == 0)
3102 nb = 32;
3103 t1 = tcg_const_i32(nb);
3104 t2 = tcg_const_i32(rS(ctx->opcode));
3105 gen_helper_stsw(cpu_env, t0, t1, t2);
3106 tcg_temp_free(t0);
3107 tcg_temp_free_i32(t1);
3108 tcg_temp_free_i32