target-ppc: Fix kvmppc_set_compat to use negotiated cpu-version
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qapi/visitor.h"
32 #include "hw/qdev-properties.h"
33
34 //#define PPC_DUMP_CPU
35 //#define PPC_DEBUG_SPR
36 //#define PPC_DUMP_SPR_ACCESSES
37 /* #define USE_APPLE_GDB */
38
39 /* For user-mode emulation, we don't emulate any IRQ controller */
40 #if defined(CONFIG_USER_ONLY)
41 #define PPC_IRQ_INIT_FN(name) \
42 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43 { \
44 }
45 #else
46 #define PPC_IRQ_INIT_FN(name) \
47 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48 #endif
49
50 PPC_IRQ_INIT_FN(40x);
51 PPC_IRQ_INIT_FN(6xx);
52 PPC_IRQ_INIT_FN(970);
53 PPC_IRQ_INIT_FN(POWER7);
54 PPC_IRQ_INIT_FN(e500);
55
56 /* Generic callbacks:
57 * do nothing but store/retrieve spr value
58 */
59 static void spr_load_dump_spr(int sprn)
60 {
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0 = tcg_const_i32(sprn);
63 gen_helper_load_dump_spr(cpu_env, t0);
64 tcg_temp_free_i32(t0);
65 #endif
66 }
67
68 static void spr_read_generic (void *opaque, int gprn, int sprn)
69 {
70 gen_load_spr(cpu_gpr[gprn], sprn);
71 spr_load_dump_spr(sprn);
72 }
73
74 static void spr_store_dump_spr(int sprn)
75 {
76 #ifdef PPC_DUMP_SPR_ACCESSES
77 TCGv_i32 t0 = tcg_const_i32(sprn);
78 gen_helper_store_dump_spr(cpu_env, t0);
79 tcg_temp_free_i32(t0);
80 #endif
81 }
82
83 static void spr_write_generic (void *opaque, int sprn, int gprn)
84 {
85 gen_store_spr(sprn, cpu_gpr[gprn]);
86 spr_store_dump_spr(sprn);
87 }
88
89 #if !defined(CONFIG_USER_ONLY)
90 static void spr_write_generic32(void *opaque, int sprn, int gprn)
91 {
92 #ifdef TARGET_PPC64
93 TCGv t0 = tcg_temp_new();
94 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
95 gen_store_spr(sprn, t0);
96 tcg_temp_free(t0);
97 spr_store_dump_spr(sprn);
98 #else
99 spr_write_generic(opaque, sprn, gprn);
100 #endif
101 }
102
103 static void spr_write_clear (void *opaque, int sprn, int gprn)
104 {
105 TCGv t0 = tcg_temp_new();
106 TCGv t1 = tcg_temp_new();
107 gen_load_spr(t0, sprn);
108 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
109 tcg_gen_and_tl(t0, t0, t1);
110 gen_store_spr(sprn, t0);
111 tcg_temp_free(t0);
112 tcg_temp_free(t1);
113 }
114
115 static void spr_access_nop(void *opaque, int sprn, int gprn)
116 {
117 }
118
119 #endif
120
121 /* SPR common to all PowerPC */
122 /* XER */
123 static void spr_read_xer (void *opaque, int gprn, int sprn)
124 {
125 gen_read_xer(cpu_gpr[gprn]);
126 }
127
128 static void spr_write_xer (void *opaque, int sprn, int gprn)
129 {
130 gen_write_xer(cpu_gpr[gprn]);
131 }
132
133 /* LR */
134 static void spr_read_lr (void *opaque, int gprn, int sprn)
135 {
136 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
137 }
138
139 static void spr_write_lr (void *opaque, int sprn, int gprn)
140 {
141 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
142 }
143
144 /* CFAR */
145 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
146 static void spr_read_cfar (void *opaque, int gprn, int sprn)
147 {
148 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
149 }
150
151 static void spr_write_cfar (void *opaque, int sprn, int gprn)
152 {
153 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
154 }
155 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
156
157 /* CTR */
158 static void spr_read_ctr (void *opaque, int gprn, int sprn)
159 {
160 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
161 }
162
163 static void spr_write_ctr (void *opaque, int sprn, int gprn)
164 {
165 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
166 }
167
168 /* User read access to SPR */
169 /* USPRx */
170 /* UMMCRx */
171 /* UPMCx */
172 /* USIA */
173 /* UDECR */
174 static void spr_read_ureg (void *opaque, int gprn, int sprn)
175 {
176 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
177 }
178
179 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
180 static void spr_write_ureg(void *opaque, int sprn, int gprn)
181 {
182 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
183 }
184 #endif
185
186 /* SPR common to all non-embedded PowerPC */
187 /* DECR */
188 #if !defined(CONFIG_USER_ONLY)
189 static void spr_read_decr (void *opaque, int gprn, int sprn)
190 {
191 if (use_icount) {
192 gen_io_start();
193 }
194 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
195 if (use_icount) {
196 gen_io_end();
197 gen_stop_exception(opaque);
198 }
199 }
200
201 static void spr_write_decr (void *opaque, int sprn, int gprn)
202 {
203 if (use_icount) {
204 gen_io_start();
205 }
206 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
207 if (use_icount) {
208 gen_io_end();
209 gen_stop_exception(opaque);
210 }
211 }
212 #endif
213
214 /* SPR common to all non-embedded PowerPC, except 601 */
215 /* Time base */
216 static void spr_read_tbl (void *opaque, int gprn, int sprn)
217 {
218 if (use_icount) {
219 gen_io_start();
220 }
221 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
222 if (use_icount) {
223 gen_io_end();
224 gen_stop_exception(opaque);
225 }
226 }
227
228 static void spr_read_tbu (void *opaque, int gprn, int sprn)
229 {
230 if (use_icount) {
231 gen_io_start();
232 }
233 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
234 if (use_icount) {
235 gen_io_end();
236 gen_stop_exception(opaque);
237 }
238 }
239
240 __attribute__ (( unused ))
241 static void spr_read_atbl (void *opaque, int gprn, int sprn)
242 {
243 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
244 }
245
246 __attribute__ (( unused ))
247 static void spr_read_atbu (void *opaque, int gprn, int sprn)
248 {
249 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
250 }
251
252 #if !defined(CONFIG_USER_ONLY)
253 static void spr_write_tbl (void *opaque, int sprn, int gprn)
254 {
255 if (use_icount) {
256 gen_io_start();
257 }
258 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
259 if (use_icount) {
260 gen_io_end();
261 gen_stop_exception(opaque);
262 }
263 }
264
265 static void spr_write_tbu (void *opaque, int sprn, int gprn)
266 {
267 if (use_icount) {
268 gen_io_start();
269 }
270 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
271 if (use_icount) {
272 gen_io_end();
273 gen_stop_exception(opaque);
274 }
275 }
276
277 __attribute__ (( unused ))
278 static void spr_write_atbl (void *opaque, int sprn, int gprn)
279 {
280 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
281 }
282
283 __attribute__ (( unused ))
284 static void spr_write_atbu (void *opaque, int sprn, int gprn)
285 {
286 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
287 }
288
289 #if defined(TARGET_PPC64)
290 __attribute__ (( unused ))
291 static void spr_read_purr (void *opaque, int gprn, int sprn)
292 {
293 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
294 }
295 #endif
296 #endif
297
298 #if !defined(CONFIG_USER_ONLY)
299 /* IBAT0U...IBAT0U */
300 /* IBAT0L...IBAT7L */
301 static void spr_read_ibat (void *opaque, int gprn, int sprn)
302 {
303 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
304 }
305
306 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
307 {
308 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
309 }
310
311 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
312 {
313 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
314 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
315 tcg_temp_free_i32(t0);
316 }
317
318 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
319 {
320 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
321 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
322 tcg_temp_free_i32(t0);
323 }
324
325 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
326 {
327 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
328 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
329 tcg_temp_free_i32(t0);
330 }
331
332 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
333 {
334 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
335 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
336 tcg_temp_free_i32(t0);
337 }
338
339 /* DBAT0U...DBAT7U */
340 /* DBAT0L...DBAT7L */
341 static void spr_read_dbat (void *opaque, int gprn, int sprn)
342 {
343 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
344 }
345
346 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
347 {
348 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
349 }
350
351 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
352 {
353 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
354 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
355 tcg_temp_free_i32(t0);
356 }
357
358 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
359 {
360 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
361 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
362 tcg_temp_free_i32(t0);
363 }
364
365 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
366 {
367 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
368 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
369 tcg_temp_free_i32(t0);
370 }
371
372 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
373 {
374 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
375 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
376 tcg_temp_free_i32(t0);
377 }
378
379 /* SDR1 */
380 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
381 {
382 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
383 }
384
385 /* 64 bits PowerPC specific SPRs */
386 #if defined(TARGET_PPC64)
387 static void spr_read_hior (void *opaque, int gprn, int sprn)
388 {
389 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
390 }
391
392 static void spr_write_hior (void *opaque, int sprn, int gprn)
393 {
394 TCGv t0 = tcg_temp_new();
395 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
396 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
397 tcg_temp_free(t0);
398 }
399 #endif
400 #endif
401
402 /* PowerPC 601 specific registers */
403 /* RTC */
404 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
405 {
406 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
407 }
408
409 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
410 {
411 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
412 }
413
414 #if !defined(CONFIG_USER_ONLY)
415 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
416 {
417 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
418 }
419
420 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
421 {
422 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
423 }
424
425 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
426 {
427 DisasContext *ctx = opaque;
428
429 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
430 /* Must stop the translation as endianness may have changed */
431 gen_stop_exception(ctx);
432 }
433 #endif
434
435 /* Unified bats */
436 #if !defined(CONFIG_USER_ONLY)
437 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
438 {
439 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
440 }
441
442 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
443 {
444 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
445 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
446 tcg_temp_free_i32(t0);
447 }
448
449 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
450 {
451 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
452 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
453 tcg_temp_free_i32(t0);
454 }
455 #endif
456
457 /* PowerPC 40x specific registers */
458 #if !defined(CONFIG_USER_ONLY)
459 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
460 {
461 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
462 }
463
464 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
465 {
466 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
467 }
468
469 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
470 {
471 DisasContext *ctx = opaque;
472
473 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
474 /* We must stop translation as we may have rebooted */
475 gen_stop_exception(ctx);
476 }
477
478 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
479 {
480 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
481 }
482
483 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
484 {
485 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
486 }
487
488 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
489 {
490 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
491 }
492 #endif
493
494 /* PowerPC 403 specific registers */
495 /* PBL1 / PBU1 / PBL2 / PBU2 */
496 #if !defined(CONFIG_USER_ONLY)
497 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
498 {
499 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
500 }
501
502 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
503 {
504 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
505 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
506 tcg_temp_free_i32(t0);
507 }
508
509 static void spr_write_pir (void *opaque, int sprn, int gprn)
510 {
511 TCGv t0 = tcg_temp_new();
512 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
513 gen_store_spr(SPR_PIR, t0);
514 tcg_temp_free(t0);
515 }
516 #endif
517
518 /* SPE specific registers */
519 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
520 {
521 TCGv_i32 t0 = tcg_temp_new_i32();
522 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
523 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
524 tcg_temp_free_i32(t0);
525 }
526
527 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
528 {
529 TCGv_i32 t0 = tcg_temp_new_i32();
530 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
531 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
532 tcg_temp_free_i32(t0);
533 }
534
535 #if !defined(CONFIG_USER_ONLY)
536 /* Callback used to write the exception vector base */
537 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
538 {
539 TCGv t0 = tcg_temp_new();
540 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
541 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
542 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
543 gen_store_spr(sprn, t0);
544 tcg_temp_free(t0);
545 }
546
547 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
548 {
549 DisasContext *ctx = opaque;
550 int sprn_offs;
551
552 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
553 sprn_offs = sprn - SPR_BOOKE_IVOR0;
554 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
555 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
556 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
557 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
558 } else {
559 printf("Trying to write an unknown exception vector %d %03x\n",
560 sprn, sprn);
561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
562 return;
563 }
564
565 TCGv t0 = tcg_temp_new();
566 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
567 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
568 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
569 gen_store_spr(sprn, t0);
570 tcg_temp_free(t0);
571 }
572 #endif
573
574 static inline void vscr_init (CPUPPCState *env, uint32_t val)
575 {
576 env->vscr = val;
577 /* Altivec always uses round-to-nearest */
578 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
579 set_flush_to_zero(vscr_nj, &env->vec_status);
580 }
581
582 #ifdef CONFIG_USER_ONLY
583 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, initial_value)
586 #else
587 #if !defined(CONFIG_KVM)
588 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
589 oea_read, oea_write, one_reg_id, initial_value) \
590 _spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, initial_value)
592 #else
593 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
594 oea_read, oea_write, one_reg_id, initial_value) \
595 _spr_register(env, num, name, uea_read, uea_write, \
596 oea_read, oea_write, one_reg_id, initial_value)
597 #endif
598 #endif
599
600 #define spr_register(env, num, name, uea_read, uea_write, \
601 oea_read, oea_write, initial_value) \
602 spr_register_kvm(env, num, name, uea_read, uea_write, \
603 oea_read, oea_write, 0, initial_value)
604
605 static inline void _spr_register(CPUPPCState *env, int num,
606 const char *name,
607 void (*uea_read)(void *opaque, int gprn, int sprn),
608 void (*uea_write)(void *opaque, int sprn, int gprn),
609 #if !defined(CONFIG_USER_ONLY)
610
611 void (*oea_read)(void *opaque, int gprn, int sprn),
612 void (*oea_write)(void *opaque, int sprn, int gprn),
613 #endif
614 #if defined(CONFIG_KVM)
615 uint64_t one_reg_id,
616 #endif
617 target_ulong initial_value)
618 {
619 ppc_spr_t *spr;
620
621 spr = &env->spr_cb[num];
622 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
623 #if !defined(CONFIG_USER_ONLY)
624 spr->oea_read != NULL || spr->oea_write != NULL ||
625 #endif
626 spr->uea_read != NULL || spr->uea_write != NULL) {
627 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
628 exit(1);
629 }
630 #if defined(PPC_DEBUG_SPR)
631 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
632 name, initial_value);
633 #endif
634 spr->name = name;
635 spr->uea_read = uea_read;
636 spr->uea_write = uea_write;
637 #if !defined(CONFIG_USER_ONLY)
638 spr->oea_read = oea_read;
639 spr->oea_write = oea_write;
640 #endif
641 #if defined(CONFIG_KVM)
642 spr->one_reg_id = one_reg_id,
643 #endif
644 env->spr[num] = spr->default_value = initial_value;
645 }
646
647 /* Generic PowerPC SPRs */
648 static void gen_spr_generic (CPUPPCState *env)
649 {
650 /* Integer processing */
651 spr_register(env, SPR_XER, "XER",
652 &spr_read_xer, &spr_write_xer,
653 &spr_read_xer, &spr_write_xer,
654 0x00000000);
655 /* Branch contol */
656 spr_register(env, SPR_LR, "LR",
657 &spr_read_lr, &spr_write_lr,
658 &spr_read_lr, &spr_write_lr,
659 0x00000000);
660 spr_register(env, SPR_CTR, "CTR",
661 &spr_read_ctr, &spr_write_ctr,
662 &spr_read_ctr, &spr_write_ctr,
663 0x00000000);
664 /* Interrupt processing */
665 spr_register(env, SPR_SRR0, "SRR0",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_generic, &spr_write_generic,
668 0x00000000);
669 spr_register(env, SPR_SRR1, "SRR1",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, &spr_write_generic,
672 0x00000000);
673 /* Processor control */
674 spr_register(env, SPR_SPRG0, "SPRG0",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_generic, &spr_write_generic,
677 0x00000000);
678 spr_register(env, SPR_SPRG1, "SPRG1",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_generic, &spr_write_generic,
681 0x00000000);
682 spr_register(env, SPR_SPRG2, "SPRG2",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_generic, &spr_write_generic,
685 0x00000000);
686 spr_register(env, SPR_SPRG3, "SPRG3",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 0x00000000);
690 }
691
692 /* SPR common to all non-embedded PowerPC, including 601 */
693 static void gen_spr_ne_601 (CPUPPCState *env)
694 {
695 /* Exception processing */
696 spr_register_kvm(env, SPR_DSISR, "DSISR",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_generic, &spr_write_generic,
699 KVM_REG_PPC_DSISR, 0x00000000);
700 spr_register_kvm(env, SPR_DAR, "DAR",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_generic,
703 KVM_REG_PPC_DAR, 0x00000000);
704 /* Timer */
705 spr_register(env, SPR_DECR, "DECR",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_decr, &spr_write_decr,
708 0x00000000);
709 /* Memory management */
710 spr_register(env, SPR_SDR1, "SDR1",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, &spr_write_sdr1,
713 0x00000000);
714 }
715
716 /* BATs 0-3 */
717 static void gen_low_BATs (CPUPPCState *env)
718 {
719 #if !defined(CONFIG_USER_ONLY)
720 spr_register(env, SPR_IBAT0U, "IBAT0U",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat, &spr_write_ibatu,
723 0x00000000);
724 spr_register(env, SPR_IBAT0L, "IBAT0L",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_ibat, &spr_write_ibatl,
727 0x00000000);
728 spr_register(env, SPR_IBAT1U, "IBAT1U",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_ibat, &spr_write_ibatu,
731 0x00000000);
732 spr_register(env, SPR_IBAT1L, "IBAT1L",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_ibat, &spr_write_ibatl,
735 0x00000000);
736 spr_register(env, SPR_IBAT2U, "IBAT2U",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_ibat, &spr_write_ibatu,
739 0x00000000);
740 spr_register(env, SPR_IBAT2L, "IBAT2L",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_ibat, &spr_write_ibatl,
743 0x00000000);
744 spr_register(env, SPR_IBAT3U, "IBAT3U",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_ibat, &spr_write_ibatu,
747 0x00000000);
748 spr_register(env, SPR_IBAT3L, "IBAT3L",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_ibat, &spr_write_ibatl,
751 0x00000000);
752 spr_register(env, SPR_DBAT0U, "DBAT0U",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat, &spr_write_dbatu,
755 0x00000000);
756 spr_register(env, SPR_DBAT0L, "DBAT0L",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_dbat, &spr_write_dbatl,
759 0x00000000);
760 spr_register(env, SPR_DBAT1U, "DBAT1U",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_dbat, &spr_write_dbatu,
763 0x00000000);
764 spr_register(env, SPR_DBAT1L, "DBAT1L",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_dbat, &spr_write_dbatl,
767 0x00000000);
768 spr_register(env, SPR_DBAT2U, "DBAT2U",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_dbat, &spr_write_dbatu,
771 0x00000000);
772 spr_register(env, SPR_DBAT2L, "DBAT2L",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_dbat, &spr_write_dbatl,
775 0x00000000);
776 spr_register(env, SPR_DBAT3U, "DBAT3U",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_dbat, &spr_write_dbatu,
779 0x00000000);
780 spr_register(env, SPR_DBAT3L, "DBAT3L",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_dbat, &spr_write_dbatl,
783 0x00000000);
784 env->nb_BATs += 4;
785 #endif
786 }
787
788 /* BATs 4-7 */
789 static void gen_high_BATs (CPUPPCState *env)
790 {
791 #if !defined(CONFIG_USER_ONLY)
792 spr_register(env, SPR_IBAT4U, "IBAT4U",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat_h, &spr_write_ibatu_h,
795 0x00000000);
796 spr_register(env, SPR_IBAT4L, "IBAT4L",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_ibat_h, &spr_write_ibatl_h,
799 0x00000000);
800 spr_register(env, SPR_IBAT5U, "IBAT5U",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_ibat_h, &spr_write_ibatu_h,
803 0x00000000);
804 spr_register(env, SPR_IBAT5L, "IBAT5L",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_ibat_h, &spr_write_ibatl_h,
807 0x00000000);
808 spr_register(env, SPR_IBAT6U, "IBAT6U",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_ibat_h, &spr_write_ibatu_h,
811 0x00000000);
812 spr_register(env, SPR_IBAT6L, "IBAT6L",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_ibat_h, &spr_write_ibatl_h,
815 0x00000000);
816 spr_register(env, SPR_IBAT7U, "IBAT7U",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_ibat_h, &spr_write_ibatu_h,
819 0x00000000);
820 spr_register(env, SPR_IBAT7L, "IBAT7L",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_ibat_h, &spr_write_ibatl_h,
823 0x00000000);
824 spr_register(env, SPR_DBAT4U, "DBAT4U",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat_h, &spr_write_dbatu_h,
827 0x00000000);
828 spr_register(env, SPR_DBAT4L, "DBAT4L",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_dbat_h, &spr_write_dbatl_h,
831 0x00000000);
832 spr_register(env, SPR_DBAT5U, "DBAT5U",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_dbat_h, &spr_write_dbatu_h,
835 0x00000000);
836 spr_register(env, SPR_DBAT5L, "DBAT5L",
837 SPR_NOACCESS, SPR_NOACCESS,
838 &spr_read_dbat_h, &spr_write_dbatl_h,
839 0x00000000);
840 spr_register(env, SPR_DBAT6U, "DBAT6U",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_dbat_h, &spr_write_dbatu_h,
843 0x00000000);
844 spr_register(env, SPR_DBAT6L, "DBAT6L",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_dbat_h, &spr_write_dbatl_h,
847 0x00000000);
848 spr_register(env, SPR_DBAT7U, "DBAT7U",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_dbat_h, &spr_write_dbatu_h,
851 0x00000000);
852 spr_register(env, SPR_DBAT7L, "DBAT7L",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_dbat_h, &spr_write_dbatl_h,
855 0x00000000);
856 env->nb_BATs += 4;
857 #endif
858 }
859
860 /* Generic PowerPC time base */
861 static void gen_tbl (CPUPPCState *env)
862 {
863 spr_register(env, SPR_VTBL, "TBL",
864 &spr_read_tbl, SPR_NOACCESS,
865 &spr_read_tbl, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_TBL, "TBL",
868 &spr_read_tbl, SPR_NOACCESS,
869 &spr_read_tbl, &spr_write_tbl,
870 0x00000000);
871 spr_register(env, SPR_VTBU, "TBU",
872 &spr_read_tbu, SPR_NOACCESS,
873 &spr_read_tbu, SPR_NOACCESS,
874 0x00000000);
875 spr_register(env, SPR_TBU, "TBU",
876 &spr_read_tbu, SPR_NOACCESS,
877 &spr_read_tbu, &spr_write_tbu,
878 0x00000000);
879 }
880
881 /* Softare table search registers */
882 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
883 {
884 #if !defined(CONFIG_USER_ONLY)
885 env->nb_tlb = nb_tlbs;
886 env->nb_ways = nb_ways;
887 env->id_tlbs = 1;
888 env->tlb_type = TLB_6XX;
889 spr_register(env, SPR_DMISS, "DMISS",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 0x00000000);
893 spr_register(env, SPR_DCMP, "DCMP",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, SPR_NOACCESS,
896 0x00000000);
897 spr_register(env, SPR_HASH1, "HASH1",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, SPR_NOACCESS,
900 0x00000000);
901 spr_register(env, SPR_HASH2, "HASH2",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, SPR_NOACCESS,
904 0x00000000);
905 spr_register(env, SPR_IMISS, "IMISS",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, SPR_NOACCESS,
908 0x00000000);
909 spr_register(env, SPR_ICMP, "ICMP",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, SPR_NOACCESS,
912 0x00000000);
913 spr_register(env, SPR_RPA, "RPA",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 #endif
918 }
919
920 /* SPR common to MPC755 and G2 */
921 static void gen_spr_G2_755 (CPUPPCState *env)
922 {
923 /* SGPRs */
924 spr_register(env, SPR_SPRG4, "SPRG4",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 spr_register(env, SPR_SPRG5, "SPRG5",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 spr_register(env, SPR_SPRG6, "SPRG6",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 spr_register(env, SPR_SPRG7, "SPRG7",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940 }
941
942 /* SPR common to all 7xx PowerPC implementations */
943 static void gen_spr_7xx (CPUPPCState *env)
944 {
945 /* Breakpoints */
946 /* XXX : not implemented */
947 spr_register_kvm(env, SPR_DABR, "DABR",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 KVM_REG_PPC_DABR, 0x00000000);
951 /* XXX : not implemented */
952 spr_register(env, SPR_IABR, "IABR",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
956 /* Cache management */
957 /* XXX : not implemented */
958 spr_register(env, SPR_ICTC, "ICTC",
959 SPR_NOACCESS, SPR_NOACCESS,
960 &spr_read_generic, &spr_write_generic,
961 0x00000000);
962 /* Performance monitors */
963 /* XXX : not implemented */
964 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_7XX_PMC1, "PMC1",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_7XX_PMC2, "PMC2",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_7XX_PMC3, "PMC3",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, &spr_write_generic,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_7XX_PMC4, "PMC4",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_7XX_SIAR, "SIAR",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, SPR_NOACCESS,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1015 &spr_read_ureg, SPR_NOACCESS,
1016 &spr_read_ureg, SPR_NOACCESS,
1017 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1020 &spr_read_ureg, SPR_NOACCESS,
1021 &spr_read_ureg, SPR_NOACCESS,
1022 0x00000000);
1023 /* XXX : not implemented */
1024 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1025 &spr_read_ureg, SPR_NOACCESS,
1026 &spr_read_ureg, SPR_NOACCESS,
1027 0x00000000);
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_7XX_USIAR, "USIAR",
1030 &spr_read_ureg, SPR_NOACCESS,
1031 &spr_read_ureg, SPR_NOACCESS,
1032 0x00000000);
1033 /* External access control */
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_EAR, "EAR",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 }
1040
1041 #ifdef TARGET_PPC64
1042 #ifndef CONFIG_USER_ONLY
1043 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1044 {
1045 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1046 spr_load_dump_spr(SPR_AMR);
1047 }
1048
1049 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1050 {
1051 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1052 spr_store_dump_spr(SPR_AMR);
1053 }
1054
1055 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1056 {
1057 TCGv t0 = tcg_temp_new();
1058
1059 gen_load_spr(t0, SPR_UAMOR);
1060 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1061 gen_store_spr(SPR_AMR, t0);
1062 spr_store_dump_spr(SPR_AMR);
1063 }
1064 #endif /* CONFIG_USER_ONLY */
1065
1066 static void gen_spr_amr (CPUPPCState *env)
1067 {
1068 #ifndef CONFIG_USER_ONLY
1069 /* Virtual Page Class Key protection */
1070 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1071 * userspace accessible, 29 is privileged. So we only need to set
1072 * the kvm ONE_REG id on one of them, we use 29 */
1073 spr_register(env, SPR_UAMR, "UAMR",
1074 &spr_read_uamr, &spr_write_uamr_pr,
1075 &spr_read_uamr, &spr_write_uamr,
1076 0);
1077 spr_register_kvm(env, SPR_AMR, "AMR",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 KVM_REG_PPC_AMR, 0);
1081 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1082 SPR_NOACCESS, SPR_NOACCESS,
1083 &spr_read_generic, &spr_write_generic,
1084 KVM_REG_PPC_UAMOR, 0);
1085 #endif /* !CONFIG_USER_ONLY */
1086 }
1087 #endif /* TARGET_PPC64 */
1088
1089 static void gen_spr_thrm (CPUPPCState *env)
1090 {
1091 /* Thermal management */
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_THRM1, "THRM1",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 /* XXX : not implemented */
1098 spr_register(env, SPR_THRM2, "THRM2",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* XXX : not implemented */
1103 spr_register(env, SPR_THRM3, "THRM3",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_generic,
1106 0x00000000);
1107 }
1108
1109 /* SPR specific to PowerPC 604 implementation */
1110 static void gen_spr_604 (CPUPPCState *env)
1111 {
1112 /* Processor identification */
1113 spr_register(env, SPR_PIR, "PIR",
1114 SPR_NOACCESS, SPR_NOACCESS,
1115 &spr_read_generic, &spr_write_pir,
1116 0x00000000);
1117 /* Breakpoints */
1118 /* XXX : not implemented */
1119 spr_register(env, SPR_IABR, "IABR",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_generic, &spr_write_generic,
1122 0x00000000);
1123 /* XXX : not implemented */
1124 spr_register_kvm(env, SPR_DABR, "DABR",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_generic, &spr_write_generic,
1127 KVM_REG_PPC_DABR, 0x00000000);
1128 /* Performance counters */
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_7XX_PMC1, "PMC1",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_generic,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_7XX_PMC2, "PMC2",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1143 0x00000000);
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_7XX_SIAR, "SIAR",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, SPR_NOACCESS,
1148 0x00000000);
1149 /* XXX : not implemented */
1150 spr_register(env, SPR_SDA, "SDA",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, SPR_NOACCESS,
1153 0x00000000);
1154 /* External access control */
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_EAR, "EAR",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 }
1161
1162 /* SPR specific to PowerPC 603 implementation */
1163 static void gen_spr_603 (CPUPPCState *env)
1164 {
1165 /* External access control */
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_EAR, "EAR",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* Breakpoints */
1172 /* XXX : not implemented */
1173 spr_register(env, SPR_IABR, "IABR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177
1178 }
1179
1180 /* SPR specific to PowerPC G2 implementation */
1181 static void gen_spr_G2 (CPUPPCState *env)
1182 {
1183 /* Memory base address */
1184 /* MBAR */
1185 /* XXX : not implemented */
1186 spr_register(env, SPR_MBAR, "MBAR",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* Exception processing */
1191 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
1199 /* Breakpoints */
1200 /* XXX : not implemented */
1201 spr_register(env, SPR_DABR, "DABR",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_DABR2, "DABR2",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_IABR, "IABR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_IABR2, "IABR2",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_IBCR, "IBCR",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* XXX : not implemented */
1226 spr_register(env, SPR_DBCR, "DBCR",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 0x00000000);
1230 }
1231
1232 /* SPR specific to PowerPC 602 implementation */
1233 static void gen_spr_602 (CPUPPCState *env)
1234 {
1235 /* ESA registers */
1236 /* XXX : not implemented */
1237 spr_register(env, SPR_SER, "SER",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_generic,
1240 0x00000000);
1241 /* XXX : not implemented */
1242 spr_register(env, SPR_SEBR, "SEBR",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 /* XXX : not implemented */
1247 spr_register(env, SPR_ESASRR, "ESASRR",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251 /* Floating point status */
1252 /* XXX : not implemented */
1253 spr_register(env, SPR_SP, "SP",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_generic, &spr_write_generic,
1256 0x00000000);
1257 /* XXX : not implemented */
1258 spr_register(env, SPR_LT, "LT",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
1262 /* Watchdog timer */
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_TCR, "TCR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 /* Interrupt base */
1269 spr_register(env, SPR_IBR, "IBR",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_IABR, "IABR",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 }
1279
1280 /* SPR specific to PowerPC 601 implementation */
1281 static void gen_spr_601 (CPUPPCState *env)
1282 {
1283 /* Multiplication/division register */
1284 /* MQ */
1285 spr_register(env, SPR_MQ, "MQ",
1286 &spr_read_generic, &spr_write_generic,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 /* RTC registers */
1290 spr_register(env, SPR_601_RTCU, "RTCU",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 SPR_NOACCESS, &spr_write_601_rtcu,
1293 0x00000000);
1294 spr_register(env, SPR_601_VRTCU, "RTCU",
1295 &spr_read_601_rtcu, SPR_NOACCESS,
1296 &spr_read_601_rtcu, SPR_NOACCESS,
1297 0x00000000);
1298 spr_register(env, SPR_601_RTCL, "RTCL",
1299 SPR_NOACCESS, SPR_NOACCESS,
1300 SPR_NOACCESS, &spr_write_601_rtcl,
1301 0x00000000);
1302 spr_register(env, SPR_601_VRTCL, "RTCL",
1303 &spr_read_601_rtcl, SPR_NOACCESS,
1304 &spr_read_601_rtcl, SPR_NOACCESS,
1305 0x00000000);
1306 /* Timer */
1307 #if 0 /* ? */
1308 spr_register(env, SPR_601_UDECR, "UDECR",
1309 &spr_read_decr, SPR_NOACCESS,
1310 &spr_read_decr, SPR_NOACCESS,
1311 0x00000000);
1312 #endif
1313 /* External access control */
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_EAR, "EAR",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* Memory management */
1320 #if !defined(CONFIG_USER_ONLY)
1321 spr_register(env, SPR_IBAT0U, "IBAT0U",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_601_ubat, &spr_write_601_ubatu,
1324 0x00000000);
1325 spr_register(env, SPR_IBAT0L, "IBAT0L",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_601_ubat, &spr_write_601_ubatl,
1328 0x00000000);
1329 spr_register(env, SPR_IBAT1U, "IBAT1U",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_601_ubat, &spr_write_601_ubatu,
1332 0x00000000);
1333 spr_register(env, SPR_IBAT1L, "IBAT1L",
1334 SPR_NOACCESS, SPR_NOACCESS,
1335 &spr_read_601_ubat, &spr_write_601_ubatl,
1336 0x00000000);
1337 spr_register(env, SPR_IBAT2U, "IBAT2U",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_601_ubat, &spr_write_601_ubatu,
1340 0x00000000);
1341 spr_register(env, SPR_IBAT2L, "IBAT2L",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_601_ubat, &spr_write_601_ubatl,
1344 0x00000000);
1345 spr_register(env, SPR_IBAT3U, "IBAT3U",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_601_ubat, &spr_write_601_ubatu,
1348 0x00000000);
1349 spr_register(env, SPR_IBAT3L, "IBAT3L",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_601_ubat, &spr_write_601_ubatl,
1352 0x00000000);
1353 env->nb_BATs = 4;
1354 #endif
1355 }
1356
1357 static void gen_spr_74xx (CPUPPCState *env)
1358 {
1359 /* Processor identification */
1360 spr_register(env, SPR_PIR, "PIR",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_pir,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1371 &spr_read_ureg, SPR_NOACCESS,
1372 &spr_read_ureg, SPR_NOACCESS,
1373 0x00000000);
1374 /* XXX: not implemented */
1375 spr_register(env, SPR_BAMR, "BAMR",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* XXX : not implemented */
1380 spr_register(env, SPR_MSSCR0, "MSSCR0",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384 /* Hardware implementation registers */
1385 /* XXX : not implemented */
1386 spr_register(env, SPR_HID0, "HID0",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390 /* XXX : not implemented */
1391 spr_register(env, SPR_HID1, "HID1",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395 /* Altivec */
1396 spr_register(env, SPR_VRSAVE, "VRSAVE",
1397 &spr_read_generic, &spr_write_generic,
1398 &spr_read_generic, &spr_write_generic,
1399 0x00000000);
1400 /* XXX : not implemented */
1401 spr_register(env, SPR_L2CR, "L2CR",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, spr_access_nop,
1404 0x00000000);
1405 /* Not strictly an SPR */
1406 vscr_init(env, 0x00010000);
1407 }
1408
1409 static void gen_l3_ctrl (CPUPPCState *env)
1410 {
1411 /* L3CR */
1412 /* XXX : not implemented */
1413 spr_register(env, SPR_L3CR, "L3CR",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* L3ITCR0 */
1418 /* XXX : not implemented */
1419 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 /* L3PM */
1424 /* XXX : not implemented */
1425 spr_register(env, SPR_L3PM, "L3PM",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_generic,
1428 0x00000000);
1429 }
1430
1431 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1432 {
1433 #if !defined(CONFIG_USER_ONLY)
1434 env->nb_tlb = nb_tlbs;
1435 env->nb_ways = nb_ways;
1436 env->id_tlbs = 1;
1437 env->tlb_type = TLB_6XX;
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_PTEHI, "PTEHI",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 /* XXX : not implemented */
1444 spr_register(env, SPR_PTELO, "PTELO",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448 /* XXX : not implemented */
1449 spr_register(env, SPR_TLBMISS, "TLBMISS",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 #endif
1454 }
1455
1456 #if !defined(CONFIG_USER_ONLY)
1457 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1458 {
1459 TCGv t0 = tcg_temp_new();
1460
1461 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1462 gen_store_spr(sprn, t0);
1463 tcg_temp_free(t0);
1464 }
1465
1466 static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn)
1467 {
1468 TCGv t0 = tcg_temp_new();
1469
1470 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1471 gen_store_spr(sprn, t0);
1472 tcg_temp_free(t0);
1473 }
1474
1475 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1476 {
1477 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1478 }
1479
1480 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1481 {
1482 TCGv_i32 t0 = tcg_const_i32(sprn);
1483 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1484 tcg_temp_free_i32(t0);
1485 }
1486 #endif
1487
1488 static void gen_spr_usprgh (CPUPPCState *env)
1489 {
1490 spr_register(env, SPR_USPRG4, "USPRG4",
1491 &spr_read_ureg, SPR_NOACCESS,
1492 &spr_read_ureg, SPR_NOACCESS,
1493 0x00000000);
1494 spr_register(env, SPR_USPRG5, "USPRG5",
1495 &spr_read_ureg, SPR_NOACCESS,
1496 &spr_read_ureg, SPR_NOACCESS,
1497 0x00000000);
1498 spr_register(env, SPR_USPRG6, "USPRG6",
1499 &spr_read_ureg, SPR_NOACCESS,
1500 &spr_read_ureg, SPR_NOACCESS,
1501 0x00000000);
1502 spr_register(env, SPR_USPRG7, "USPRG7",
1503 &spr_read_ureg, SPR_NOACCESS,
1504 &spr_read_ureg, SPR_NOACCESS,
1505 0x00000000);
1506 }
1507
1508 /* PowerPC BookE SPR */
1509 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1510 {
1511 const char *ivor_names[64] = {
1512 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1513 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1514 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1515 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1516 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1517 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1518 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1519 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1520 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1521 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1522 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1523 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1524 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1525 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1526 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1527 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1528 };
1529 #define SPR_BOOKE_IVORxx (-1)
1530 int ivor_sprn[64] = {
1531 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1532 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1533 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1534 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1535 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1536 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1537 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1538 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1539 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1540 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1541 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1542 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1543 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1544 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1545 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1546 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1547 };
1548 int i;
1549
1550 /* Interrupt processing */
1551 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559 /* Debug */
1560 /* XXX : not implemented */
1561 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 /* XXX : not implemented */
1566 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 /* XXX : not implemented */
1571 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 /* XXX : not implemented */
1576 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580 /* XXX : not implemented */
1581 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_40x_dbcr0,
1584 0x00000000);
1585 /* XXX : not implemented */
1586 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_generic,
1589 0x00000000);
1590 /* XXX : not implemented */
1591 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_clear,
1599 0x00000000);
1600 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604 spr_register(env, SPR_BOOKE_ESR, "ESR",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_excp_prefix,
1611 0x00000000);
1612 /* Exception vectors */
1613 for (i = 0; i < 64; i++) {
1614 if (ivor_mask & (1ULL << i)) {
1615 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1616 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1617 exit(1);
1618 }
1619 spr_register(env, ivor_sprn[i], ivor_names[i],
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_excp_vector,
1622 0x00000000);
1623 }
1624 }
1625 spr_register(env, SPR_BOOKE_PID, "PID",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_booke_pid,
1628 0x00000000);
1629 spr_register(env, SPR_BOOKE_TCR, "TCR",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_booke_tcr,
1632 0x00000000);
1633 spr_register(env, SPR_BOOKE_TSR, "TSR",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_booke_tsr,
1636 0x00000000);
1637 /* Timer */
1638 spr_register(env, SPR_DECR, "DECR",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_decr, &spr_write_decr,
1641 0x00000000);
1642 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 SPR_NOACCESS, &spr_write_generic,
1645 0x00000000);
1646 /* SPRGs */
1647 spr_register(env, SPR_USPRG0, "USPRG0",
1648 &spr_read_generic, &spr_write_generic,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 spr_register(env, SPR_SPRG4, "SPRG4",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_generic,
1654 0x00000000);
1655 spr_register(env, SPR_SPRG5, "SPRG5",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 spr_register(env, SPR_SPRG6, "SPRG6",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 spr_register(env, SPR_SPRG7, "SPRG7",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 }
1668
1669 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1670 uint32_t maxsize, uint32_t flags,
1671 uint32_t nentries)
1672 {
1673 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1674 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1675 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1676 flags | nentries;
1677 }
1678
1679 /* BookE 2.06 storage control registers */
1680 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1681 uint32_t *tlbncfg)
1682 {
1683 #if !defined(CONFIG_USER_ONLY)
1684 const char *mas_names[8] = {
1685 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1686 };
1687 int mas_sprn[8] = {
1688 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1689 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1690 };
1691 int i;
1692
1693 /* TLB assist registers */
1694 /* XXX : not implemented */
1695 for (i = 0; i < 8; i++) {
1696 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1697 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1698 uea_write = &spr_write_generic;
1699 }
1700 if (mas_mask & (1 << i)) {
1701 spr_register(env, mas_sprn[i], mas_names[i],
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, uea_write,
1704 0x00000000);
1705 }
1706 }
1707 if (env->nb_pids > 1) {
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_BOOKE_PID1, "PID1",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_booke_pid,
1712 0x00000000);
1713 }
1714 if (env->nb_pids > 2) {
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_BOOKE_PID2, "PID2",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_booke_pid,
1719 0x00000000);
1720 }
1721 /* XXX : not implemented */
1722 spr_register(env, SPR_MMUCFG, "MMUCFG",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, SPR_NOACCESS,
1725 0x00000000); /* TOFIX */
1726 switch (env->nb_ways) {
1727 case 4:
1728 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, SPR_NOACCESS,
1731 tlbncfg[3]);
1732 /* Fallthru */
1733 case 3:
1734 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, SPR_NOACCESS,
1737 tlbncfg[2]);
1738 /* Fallthru */
1739 case 2:
1740 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, SPR_NOACCESS,
1743 tlbncfg[1]);
1744 /* Fallthru */
1745 case 1:
1746 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1747 SPR_NOACCESS, SPR_NOACCESS,
1748 &spr_read_generic, SPR_NOACCESS,
1749 tlbncfg[0]);
1750 /* Fallthru */
1751 case 0:
1752 default:
1753 break;
1754 }
1755 #endif
1756
1757 gen_spr_usprgh(env);
1758 }
1759
1760 /* SPR specific to PowerPC 440 implementation */
1761 static void gen_spr_440 (CPUPPCState *env)
1762 {
1763 /* Cache control */
1764 /* XXX : not implemented */
1765 spr_register(env, SPR_440_DNV0, "DNV0",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769 /* XXX : not implemented */
1770 spr_register(env, SPR_440_DNV1, "DNV1",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_440_DNV2, "DNV2",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 /* XXX : not implemented */
1780 spr_register(env, SPR_440_DNV3, "DNV3",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784 /* XXX : not implemented */
1785 spr_register(env, SPR_440_DTV0, "DTV0",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789 /* XXX : not implemented */
1790 spr_register(env, SPR_440_DTV1, "DTV1",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_440_DTV2, "DTV2",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_440_DTV3, "DTV3",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* XXX : not implemented */
1805 spr_register(env, SPR_440_DVLIM, "DVLIM",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 /* XXX : not implemented */
1810 spr_register(env, SPR_440_INV0, "INV0",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
1814 /* XXX : not implemented */
1815 spr_register(env, SPR_440_INV1, "INV1",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 /* XXX : not implemented */
1820 spr_register(env, SPR_440_INV2, "INV2",
1821 SPR_NOACCESS, SPR_NOACCESS,
1822 &spr_read_generic, &spr_write_generic,
1823 0x00000000);
1824 /* XXX : not implemented */
1825 spr_register(env, SPR_440_INV3, "INV3",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829 /* XXX : not implemented */
1830 spr_register(env, SPR_440_ITV0, "ITV0",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* XXX : not implemented */
1835 spr_register(env, SPR_440_ITV1, "ITV1",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, &spr_write_generic,
1838 0x00000000);
1839 /* XXX : not implemented */
1840 spr_register(env, SPR_440_ITV2, "ITV2",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_generic,
1843 0x00000000);
1844 /* XXX : not implemented */
1845 spr_register(env, SPR_440_ITV3, "ITV3",
1846 SPR_NOACCESS, SPR_NOACCESS,
1847 &spr_read_generic, &spr_write_generic,
1848 0x00000000);
1849 /* XXX : not implemented */
1850 spr_register(env, SPR_440_IVLIM, "IVLIM",
1851 SPR_NOACCESS, SPR_NOACCESS,
1852 &spr_read_generic, &spr_write_generic,
1853 0x00000000);
1854 /* Cache debug */
1855 /* XXX : not implemented */
1856 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, SPR_NOACCESS,
1859 0x00000000);
1860 /* XXX : not implemented */
1861 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_generic, SPR_NOACCESS,
1864 0x00000000);
1865 /* XXX : not implemented */
1866 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, SPR_NOACCESS,
1869 0x00000000);
1870 /* XXX : not implemented */
1871 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, SPR_NOACCESS,
1874 0x00000000);
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, SPR_NOACCESS,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_440_DBDR, "DBDR",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* Processor control */
1886 spr_register(env, SPR_4xx_CCR0, "CCR0",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1891 SPR_NOACCESS, SPR_NOACCESS,
1892 &spr_read_generic, SPR_NOACCESS,
1893 0x00000000);
1894 /* Storage control */
1895 spr_register(env, SPR_440_MMUCR, "MMUCR",
1896 SPR_NOACCESS, SPR_NOACCESS,
1897 &spr_read_generic, &spr_write_generic,
1898 0x00000000);
1899 }
1900
1901 /* SPR shared between PowerPC 40x implementations */
1902 static void gen_spr_40x (CPUPPCState *env)
1903 {
1904 /* Cache */
1905 /* not emulated, as QEMU do not emulate caches */
1906 spr_register(env, SPR_40x_DCCR, "DCCR",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910 /* not emulated, as QEMU do not emulate caches */
1911 spr_register(env, SPR_40x_ICCR, "ICCR",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915 /* not emulated, as QEMU do not emulate caches */
1916 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1917 SPR_NOACCESS, SPR_NOACCESS,
1918 &spr_read_generic, SPR_NOACCESS,
1919 0x00000000);
1920 /* Exception */
1921 spr_register(env, SPR_40x_DEAR, "DEAR",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 spr_register(env, SPR_40x_ESR, "ESR",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 spr_register(env, SPR_40x_EVPR, "EVPR",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_excp_prefix,
1932 0x00000000);
1933 spr_register(env, SPR_40x_SRR2, "SRR2",
1934 &spr_read_generic, &spr_write_generic,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 spr_register(env, SPR_40x_SRR3, "SRR3",
1938 &spr_read_generic, &spr_write_generic,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 /* Timers */
1942 spr_register(env, SPR_40x_PIT, "PIT",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_40x_pit, &spr_write_40x_pit,
1945 0x00000000);
1946 spr_register(env, SPR_40x_TCR, "TCR",
1947 SPR_NOACCESS, SPR_NOACCESS,
1948 &spr_read_generic, &spr_write_booke_tcr,
1949 0x00000000);
1950 spr_register(env, SPR_40x_TSR, "TSR",
1951 SPR_NOACCESS, SPR_NOACCESS,
1952 &spr_read_generic, &spr_write_booke_tsr,
1953 0x00000000);
1954 }
1955
1956 /* SPR specific to PowerPC 405 implementation */
1957 static void gen_spr_405 (CPUPPCState *env)
1958 {
1959 /* MMU */
1960 spr_register(env, SPR_40x_PID, "PID",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
1964 spr_register(env, SPR_4xx_CCR0, "CCR0",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_generic, &spr_write_generic,
1967 0x00700000);
1968 /* Debug interface */
1969 /* XXX : not implemented */
1970 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_40x_dbcr0,
1973 0x00000000);
1974 /* XXX : not implemented */
1975 spr_register(env, SPR_405_DBCR1, "DBCR1",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 /* XXX : not implemented */
1980 spr_register(env, SPR_40x_DBSR, "DBSR",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, &spr_write_clear,
1983 /* Last reset was system reset */
1984 0x00000300);
1985 /* XXX : not implemented */
1986 spr_register(env, SPR_40x_DAC1, "DAC1",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_generic,
1989 0x00000000);
1990 spr_register(env, SPR_40x_DAC2, "DAC2",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994 /* XXX : not implemented */
1995 spr_register(env, SPR_405_DVC1, "DVC1",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999 /* XXX : not implemented */
2000 spr_register(env, SPR_405_DVC2, "DVC2",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_40x_IAC1, "IAC1",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 spr_register(env, SPR_40x_IAC2, "IAC2",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, &spr_write_generic,
2012 0x00000000);
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_405_IAC3, "IAC3",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_405_IAC4, "IAC4",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, &spr_write_generic,
2022 0x00000000);
2023 /* Storage control */
2024 /* XXX: TODO: not implemented */
2025 spr_register(env, SPR_405_SLER, "SLER",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_40x_sler,
2028 0x00000000);
2029 spr_register(env, SPR_40x_ZPR, "ZPR",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_405_SU0R, "SU0R",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 /* SPRG */
2039 spr_register(env, SPR_USPRG0, "USPRG0",
2040 &spr_read_ureg, SPR_NOACCESS,
2041 &spr_read_ureg, SPR_NOACCESS,
2042 0x00000000);
2043 spr_register(env, SPR_SPRG4, "SPRG4",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 &spr_read_generic, &spr_write_generic,
2046 0x00000000);
2047 spr_register(env, SPR_SPRG5, "SPRG5",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 spr_read_generic, &spr_write_generic,
2050 0x00000000);
2051 spr_register(env, SPR_SPRG6, "SPRG6",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 spr_read_generic, &spr_write_generic,
2054 0x00000000);
2055 spr_register(env, SPR_SPRG7, "SPRG7",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 gen_spr_usprgh(env);
2060 }
2061
2062 /* SPR shared between PowerPC 401 & 403 implementations */
2063 static void gen_spr_401_403 (CPUPPCState *env)
2064 {
2065 /* Time base */
2066 spr_register(env, SPR_403_VTBL, "TBL",
2067 &spr_read_tbl, SPR_NOACCESS,
2068 &spr_read_tbl, SPR_NOACCESS,
2069 0x00000000);
2070 spr_register(env, SPR_403_TBL, "TBL",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 SPR_NOACCESS, &spr_write_tbl,
2073 0x00000000);
2074 spr_register(env, SPR_403_VTBU, "TBU",
2075 &spr_read_tbu, SPR_NOACCESS,
2076 &spr_read_tbu, SPR_NOACCESS,
2077 0x00000000);
2078 spr_register(env, SPR_403_TBU, "TBU",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 SPR_NOACCESS, &spr_write_tbu,
2081 0x00000000);
2082 /* Debug */
2083 /* not emulated, as QEMU do not emulate caches */
2084 spr_register(env, SPR_403_CDBCR, "CDBCR",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2088 }
2089
2090 /* SPR specific to PowerPC 401 implementation */
2091 static void gen_spr_401 (CPUPPCState *env)
2092 {
2093 /* Debug interface */
2094 /* XXX : not implemented */
2095 spr_register(env, SPR_40x_DBCR0, "DBCR",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_40x_dbcr0,
2098 0x00000000);
2099 /* XXX : not implemented */
2100 spr_register(env, SPR_40x_DBSR, "DBSR",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_clear,
2103 /* Last reset was system reset */
2104 0x00000300);
2105 /* XXX : not implemented */
2106 spr_register(env, SPR_40x_DAC1, "DAC",
2107 SPR_NOACCESS, SPR_NOACCESS,
2108 &spr_read_generic, &spr_write_generic,
2109 0x00000000);
2110 /* XXX : not implemented */
2111 spr_register(env, SPR_40x_IAC1, "IAC",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115 /* Storage control */
2116 /* XXX: TODO: not implemented */
2117 spr_register(env, SPR_405_SLER, "SLER",
2118 SPR_NOACCESS, SPR_NOACCESS,
2119 &spr_read_generic, &spr_write_40x_sler,
2120 0x00000000);
2121 /* not emulated, as QEMU never does speculative access */
2122 spr_register(env, SPR_40x_SGR, "SGR",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_generic,
2125 0xFFFFFFFF);
2126 /* not emulated, as QEMU do not emulate caches */
2127 spr_register(env, SPR_40x_DCWR, "DCWR",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 }
2132
2133 static void gen_spr_401x2 (CPUPPCState *env)
2134 {
2135 gen_spr_401(env);
2136 spr_register(env, SPR_40x_PID, "PID",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 spr_register(env, SPR_40x_ZPR, "ZPR",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 }
2145
2146 /* SPR specific to PowerPC 403 implementation */
2147 static void gen_spr_403 (CPUPPCState *env)
2148 {
2149 /* Debug interface */
2150 /* XXX : not implemented */
2151 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_40x_dbcr0,
2154 0x00000000);
2155 /* XXX : not implemented */
2156 spr_register(env, SPR_40x_DBSR, "DBSR",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 &spr_read_generic, &spr_write_clear,
2159 /* Last reset was system reset */
2160 0x00000300);
2161 /* XXX : not implemented */
2162 spr_register(env, SPR_40x_DAC1, "DAC1",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_generic, &spr_write_generic,
2165 0x00000000);
2166 /* XXX : not implemented */
2167 spr_register(env, SPR_40x_DAC2, "DAC2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_40x_IAC1, "IAC1",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, &spr_write_generic,
2175 0x00000000);
2176 /* XXX : not implemented */
2177 spr_register(env, SPR_40x_IAC2, "IAC2",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 }
2182
2183 static void gen_spr_403_real (CPUPPCState *env)
2184 {
2185 spr_register(env, SPR_403_PBL1, "PBL1",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_403_pbr, &spr_write_403_pbr,
2188 0x00000000);
2189 spr_register(env, SPR_403_PBU1, "PBU1",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_403_pbr, &spr_write_403_pbr,
2192 0x00000000);
2193 spr_register(env, SPR_403_PBL2, "PBL2",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_403_pbr, &spr_write_403_pbr,
2196 0x00000000);
2197 spr_register(env, SPR_403_PBU2, "PBU2",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_403_pbr, &spr_write_403_pbr,
2200 0x00000000);
2201 }
2202
2203 static void gen_spr_403_mmu (CPUPPCState *env)
2204 {
2205 /* MMU */
2206 spr_register(env, SPR_40x_PID, "PID",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 spr_register(env, SPR_40x_ZPR, "ZPR",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 }
2215
2216 /* SPR specific to PowerPC compression coprocessor extension */
2217 static void gen_spr_compress (CPUPPCState *env)
2218 {
2219 /* XXX : not implemented */
2220 spr_register(env, SPR_401_SKR, "SKR",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 }
2225
2226 static void gen_spr_5xx_8xx (CPUPPCState *env)
2227 {
2228 /* Exception processing */
2229 spr_register_kvm(env, SPR_DSISR, "DSISR",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 KVM_REG_PPC_DSISR, 0x00000000);
2233 spr_register_kvm(env, SPR_DAR, "DAR",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 KVM_REG_PPC_DAR, 0x00000000);
2237 /* Timer */
2238 spr_register(env, SPR_DECR, "DECR",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_decr, &spr_write_decr,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_MPC_EIE, "EIE",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_MPC_EID, "EID",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_MPC_NRI, "NRI",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_MPC_CMPA, "CMPA",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_MPC_CMPB, "CMPB",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 /* XXX : not implemented */
2268 spr_register(env, SPR_MPC_CMPC, "CMPC",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 /* XXX : not implemented */
2273 spr_register(env, SPR_MPC_CMPD, "CMPD",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_MPC_ECR, "ECR",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_MPC_DER, "DER",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* XXX : not implemented */
2293 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* XXX : not implemented */
2298 spr_register(env, SPR_MPC_CMPE, "CMPE",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_CMPF, "CMPF",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_MPC_CMPG, "CMPG",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_MPC_CMPH, "CMPH",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_BAR, "BAR",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_DPDR, "DPDR",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_IMMR, "IMMR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 }
2343
2344 static void gen_spr_5xx (CPUPPCState *env)
2345 {
2346 /* XXX : not implemented */
2347 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_generic,
2375 0x00000000);
2376 /* XXX : not implemented */
2377 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_generic,
2380 0x00000000);
2381 /* XXX : not implemented */
2382 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 /* XXX : not implemented */
2387 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 /* XXX : not implemented */
2392 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 }
2452
2453 static void gen_spr_8xx (CPUPPCState *env)
2454 {
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 /* XXX : not implemented */
2506 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 /* XXX : not implemented */
2511 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 }
2581
2582 // XXX: TODO
2583 /*
2584 * AMR => SPR 29 (Power 2.04)
2585 * CTRL => SPR 136 (Power 2.04)
2586 * CTRL => SPR 152 (Power 2.04)
2587 * SCOMC => SPR 276 (64 bits ?)
2588 * SCOMD => SPR 277 (64 bits ?)
2589 * TBU40 => SPR 286 (Power 2.04 hypv)
2590 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2591 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2592 * HDSISR => SPR 306 (Power 2.04 hypv)
2593 * HDAR => SPR 307 (Power 2.04 hypv)
2594 * PURR => SPR 309 (Power 2.04 hypv)
2595 * HDEC => SPR 310 (Power 2.04 hypv)
2596 * HIOR => SPR 311 (hypv)
2597 * RMOR => SPR 312 (970)
2598 * HRMOR => SPR 313 (Power 2.04 hypv)
2599 * HSRR0 => SPR 314 (Power 2.04 hypv)
2600 * HSRR1 => SPR 315 (Power 2.04 hypv)
2601 * LPIDR => SPR 317 (970)
2602 * EPR => SPR 702 (Power 2.04 emb)
2603 * perf => 768-783 (Power 2.04)
2604 * perf => 784-799 (Power 2.04)
2605 * PPR => SPR 896 (Power 2.04)
2606 * EPLC => SPR 947 (Power 2.04 emb)
2607 * EPSC => SPR 948 (Power 2.04 emb)
2608 * DABRX => 1015 (Power 2.04 hypv)
2609 * FPECR => SPR 1022 (?)
2610 * ... and more (thermal management, performance counters, ...)
2611 */
2612
2613 /*****************************************************************************/
2614 /* Exception vectors models */
2615 static void init_excp_4xx_real (CPUPPCState *env)
2616 {
2617 #if !defined(CONFIG_USER_ONLY)
2618 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2619 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2620 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2621 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2622 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2623 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2624 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2625 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2626 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2627 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2628 env->ivor_mask = 0x0000FFF0UL;
2629 env->ivpr_mask = 0xFFFF0000UL;
2630 /* Hardware reset vector */
2631 env->hreset_vector = 0xFFFFFFFCUL;
2632 #endif
2633 }
2634
2635 static void init_excp_4xx_softmmu (CPUPPCState *env)
2636 {
2637 #if !defined(CONFIG_USER_ONLY)
2638 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2639 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2640 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2641 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2642 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2643 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2644 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2645 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2646 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2647 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2648 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2649 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2650 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2651 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2652 env->ivor_mask = 0x0000FFF0UL;
2653 env->ivpr_mask = 0xFFFF0000UL;
2654 /* Hardware reset vector */
2655 env->hreset_vector = 0xFFFFFFFCUL;
2656 #endif
2657 }
2658
2659 static void init_excp_MPC5xx (CPUPPCState *env)
2660 {
2661 #if !defined(CONFIG_USER_ONLY)
2662 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2663 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2664 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2665 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2666 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2667 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2668 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2669 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2670 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2671 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2672 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2673 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2674 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2675 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2676 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2677 env->ivor_mask = 0x0000FFF0UL;
2678 env->ivpr_mask = 0xFFFF0000UL;
2679 /* Hardware reset vector */
2680 env->hreset_vector = 0x00000100UL;
2681 #endif
2682 }
2683
2684 static void init_excp_MPC8xx (CPUPPCState *env)
2685 {
2686 #if !defined(CONFIG_USER_ONLY)
2687 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2688 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2689 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2690 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2691 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2692 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2693 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2694 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2695 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2696 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2697 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2698 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2699 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2700 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2701 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2702 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2703 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2704 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2705 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2706 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2707 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2708 env->ivor_mask = 0x0000FFF0UL;
2709 env->ivpr_mask = 0xFFFF0000UL;
2710 /* Hardware reset vector */
2711 env->hreset_vector = 0x00000100UL;
2712 #endif
2713 }
2714
2715 static void init_excp_G2 (CPUPPCState *env)
2716 {
2717 #if !defined(CONFIG_USER_ONLY)
2718 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2719 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2720 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2721 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2722 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2723 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2724 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2725 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2726 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2727 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2728 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2729 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2730 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2731 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2732 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2733 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2734 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2735 /* Hardware reset vector */
2736 env->hreset_vector = 0x00000100UL;
2737 #endif
2738 }
2739
2740 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2741 {
2742 #if !defined(CONFIG_USER_ONLY)
2743 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2744 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2763 env->ivor_mask = 0x0000FFF7UL;
2764 env->ivpr_mask = ivpr_mask;
2765 /* Hardware reset vector */
2766 env->hreset_vector = 0xFFFFFFFCUL;
2767 #endif
2768 }
2769
2770 static void init_excp_BookE (CPUPPCState *env)
2771 {
2772 #if !defined(CONFIG_USER_ONLY)
2773 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2774 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2775 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2776 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2777 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2778 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2779 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2780 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2781 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2782 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2783 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2784 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2785 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2786 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2787 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2788 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2789 env->ivor_mask = 0x0000FFE0UL;
2790 env->ivpr_mask = 0xFFFF0000UL;
2791 /* Hardware reset vector */
2792 env->hreset_vector = 0xFFFFFFFCUL;
2793 #endif
2794 }
2795
2796 static void init_excp_601 (CPUPPCState *env)
2797 {
2798 #if !defined(CONFIG_USER_ONLY)
2799 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2800 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2801 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2802 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2803 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2804 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2805 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2806 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2807 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2808 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2809 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2810 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2811 /* Hardware reset vector */
2812 env->hreset_vector = 0x00000100UL;
2813 #endif
2814 }
2815
2816 static void init_excp_602 (CPUPPCState *env)
2817 {
2818 #if !defined(CONFIG_USER_ONLY)
2819 /* XXX: exception prefix has a special behavior on 602 */
2820 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2821 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2822 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2823 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2824 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2825 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2826 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2827 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2828 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2829 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2830 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2831 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2832 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2833 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2834 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2835 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2836 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2837 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2838 /* Hardware reset vector */
2839 env->hreset_vector = 0x00000100UL;
2840 #endif
2841 }
2842
2843 static void init_excp_603 (CPUPPCState *env)
2844 {
2845 #if !defined(CONFIG_USER_ONLY)
2846 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2847 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2848 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2849 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2850 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2851 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2852 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2853 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2854 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2855 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2856 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2857 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2858 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2859 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2860 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2861 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2862 /* Hardware reset vector */
2863 env->hreset_vector = 0x00000100UL;
2864 #endif
2865 }
2866
2867 static void init_excp_604 (CPUPPCState *env)
2868 {
2869 #if !defined(CONFIG_USER_ONLY)
2870 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2871 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2872 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2873 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2874 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2875 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2876 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2877 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2878 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2879 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2880 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2881 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2882 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2883 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2884 /* Hardware reset vector */
2885 env->hreset_vector = 0x00000100UL;
2886 #endif
2887 }
2888
2889 static void init_excp_7x0 (CPUPPCState *env)
2890 {
2891 #if !defined(CONFIG_USER_ONLY)
2892 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2893 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2894 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2895 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2896 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2897 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2898 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2899 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2900 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2901 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2902 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2903 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2904 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2905 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2906 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2907 /* Hardware reset vector */
2908 env->hreset_vector = 0x00000100UL;
2909 #endif
2910 }
2911
2912 static void init_excp_750cl (CPUPPCState *env)
2913 {
2914 #if !defined(CONFIG_USER_ONLY)
2915 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2916 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2917 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2918 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2919 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2920 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2921 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2922 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2923 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2924 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2925 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2926 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2927 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2928 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2929 /* Hardware reset vector */
2930 env->hreset_vector = 0x00000100UL;
2931 #endif
2932 }
2933
2934 static void init_excp_750cx (CPUPPCState *env)
2935 {
2936 #if !defined(CONFIG_USER_ONLY)
2937 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2938 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2939 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2940 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2941 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2942 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2943 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2944 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2945 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2946 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2947 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2948 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2949 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2950 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2951 /* Hardware reset vector */
2952 env->hreset_vector = 0x00000100UL;
2953 #endif
2954 }
2955
2956 /* XXX: Check if this is correct */
2957 static void init_excp_7x5 (CPUPPCState *env)
2958 {
2959 #if !defined(CONFIG_USER_ONLY)
2960 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2961 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2962 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2963 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2964 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2965 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2966 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2967 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2968 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2969 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2970 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2971 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2972 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2973 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2974 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2975 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2976 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2977 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2978 /* Hardware reset vector */
2979 env->hreset_vector = 0x00000100UL;
2980 #endif
2981 }
2982
2983 static void init_excp_7400 (CPUPPCState *env)
2984 {
2985 #if !defined(CONFIG_USER_ONLY)
2986 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2987 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2988 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2989 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2990 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2991 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2992 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2993 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2994 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2995 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2996 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2997 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2998 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2999 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3000 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3001 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3002 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3003 /* Hardware reset vector */
3004 env->hreset_vector = 0x00000100UL;
3005 #endif
3006 }
3007
3008 static void init_excp_7450 (CPUPPCState *env)
3009 {
3010 #if !defined(CONFIG_USER_ONLY)
3011 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3012 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3013 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3014 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3015 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3016 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3017 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3018 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3019 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3020 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3021 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3022 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3023 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3024 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3025 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3026 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3027 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3028 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3029 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3030 /* Hardware reset vector */
3031 env->hreset_vector = 0x00000100UL;
3032 #endif
3033 }
3034
3035 #if defined (TARGET_PPC64)
3036 static void init_excp_970 (CPUPPCState *env)
3037 {
3038 #if !defined(CONFIG_USER_ONLY)
3039 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3040 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3041 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3042 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3043 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3044 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3045 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3046 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3047 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3048 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3049 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3050 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3051 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3052 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3053 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3054 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3055 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3056 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3057 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3058 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3059 /* Hardware reset vector */
3060 env->hreset_vector = 0x0000000000000100ULL;
3061 #endif
3062 }
3063
3064 static void init_excp_POWER7 (CPUPPCState *env)
3065 {
3066 #if !defined(CONFIG_USER_ONLY)
3067 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3068 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3069 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3070 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3071 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3072 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3073 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3074 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3075 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3076 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3077 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3078 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3079 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3080 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3081 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3082 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3083 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3084 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3085 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3086 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3087 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3088 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3089 /* Hardware reset vector */
3090 env->hreset_vector = 0x0000000000000100ULL;
3091 #endif
3092 }
3093 #endif
3094
3095 /*****************************************************************************/
3096 /* Power management enable checks */
3097 static int check_pow_none (CPUPPCState *env)
3098 {
3099 return 0;
3100 }
3101
3102 static int check_pow_nocheck (CPUPPCState *env)
3103 {
3104 return 1;
3105 }
3106
3107 static int check_pow_hid0 (CPUPPCState *env)
3108 {
3109 if (env->spr[SPR_HID0] & 0x00E00000)
3110 return 1;