qom: add the base Object class (v2)
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "gdbstub.h"
28 #include <kvm.h>
29 #include "kvm_ppc.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34 #if defined(CONFIG_USER_ONLY)
35 #define TODO_USER_ONLY 1
36 #endif
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_read_generic (void *opaque, int gprn, int sprn)
59 {
60 gen_load_spr(cpu_gpr[gprn], sprn);
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 {
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 }
67 #endif
68 }
69
70 static void spr_write_generic (void *opaque, int sprn, int gprn)
71 {
72 gen_store_spr(sprn, cpu_gpr[gprn]);
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv_i32 t0 = tcg_const_i32(sprn);
76 gen_helper_store_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79 #endif
80 }
81
82 #if !defined(CONFIG_USER_ONLY)
83 static void spr_write_clear (void *opaque, int sprn, int gprn)
84 {
85 TCGv t0 = tcg_temp_new();
86 TCGv t1 = tcg_temp_new();
87 gen_load_spr(t0, sprn);
88 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
89 tcg_gen_and_tl(t0, t0, t1);
90 gen_store_spr(sprn, t0);
91 tcg_temp_free(t0);
92 tcg_temp_free(t1);
93 }
94 #endif
95
96 /* SPR common to all PowerPC */
97 /* XER */
98 static void spr_read_xer (void *opaque, int gprn, int sprn)
99 {
100 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
101 }
102
103 static void spr_write_xer (void *opaque, int sprn, int gprn)
104 {
105 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
106 }
107
108 /* LR */
109 static void spr_read_lr (void *opaque, int gprn, int sprn)
110 {
111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
112 }
113
114 static void spr_write_lr (void *opaque, int sprn, int gprn)
115 {
116 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
117 }
118
119 /* CFAR */
120 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
121 static void spr_read_cfar (void *opaque, int gprn, int sprn)
122 {
123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
124 }
125
126 static void spr_write_cfar (void *opaque, int sprn, int gprn)
127 {
128 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
129 }
130 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 if (use_icount) {
160 gen_io_start();
161 }
162 gen_helper_load_decr(cpu_gpr[gprn]);
163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
167 }
168
169 static void spr_write_decr (void *opaque, int sprn, int gprn)
170 {
171 if (use_icount) {
172 gen_io_start();
173 }
174 gen_helper_store_decr(cpu_gpr[gprn]);
175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC, except 601 */
183 /* Time base */
184 static void spr_read_tbl (void *opaque, int gprn, int sprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_load_tbl(cpu_gpr[gprn]);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195
196 static void spr_read_tbu (void *opaque, int gprn, int sprn)
197 {
198 if (use_icount) {
199 gen_io_start();
200 }
201 gen_helper_load_tbu(cpu_gpr[gprn]);
202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
206 }
207
208 __attribute__ (( unused ))
209 static void spr_read_atbl (void *opaque, int gprn, int sprn)
210 {
211 gen_helper_load_atbl(cpu_gpr[gprn]);
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbu (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbu(cpu_gpr[gprn]);
218 }
219
220 #if !defined(CONFIG_USER_ONLY)
221 static void spr_write_tbl (void *opaque, int sprn, int gprn)
222 {
223 if (use_icount) {
224 gen_io_start();
225 }
226 gen_helper_store_tbl(cpu_gpr[gprn]);
227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
231 }
232
233 static void spr_write_tbu (void *opaque, int sprn, int gprn)
234 {
235 if (use_icount) {
236 gen_io_start();
237 }
238 gen_helper_store_tbu(cpu_gpr[gprn]);
239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
243 }
244
245 __attribute__ (( unused ))
246 static void spr_write_atbl (void *opaque, int sprn, int gprn)
247 {
248 gen_helper_store_atbl(cpu_gpr[gprn]);
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbu (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbu(cpu_gpr[gprn]);
255 }
256
257 #if defined(TARGET_PPC64)
258 __attribute__ (( unused ))
259 static void spr_read_purr (void *opaque, int gprn, int sprn)
260 {
261 gen_helper_load_purr(cpu_gpr[gprn]);
262 }
263 #endif
264 #endif
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* IBAT0U...IBAT0U */
268 /* IBAT0L...IBAT7L */
269 static void spr_read_ibat (void *opaque, int gprn, int sprn)
270 {
271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
272 }
273
274 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
275 {
276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
277 }
278
279 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
280 {
281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
284 }
285
286 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
287 {
288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
291 }
292
293 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 /* DBAT0U...DBAT7U */
308 /* DBAT0L...DBAT7L */
309 static void spr_read_dbat (void *opaque, int gprn, int sprn)
310 {
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
312 }
313
314 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
315 {
316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
317 }
318
319 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 /* SDR1 */
348 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
349 {
350 gen_helper_store_sdr1(cpu_gpr[gprn]);
351 }
352
353 /* 64 bits PowerPC specific SPRs */
354 /* ASR */
355 #if defined(TARGET_PPC64)
356 static void spr_read_hior (void *opaque, int gprn, int sprn)
357 {
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
359 }
360
361 static void spr_write_hior (void *opaque, int sprn, int gprn)
362 {
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
366 tcg_temp_free(t0);
367 }
368
369 static void spr_read_asr (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
372 }
373
374 static void spr_write_asr (void *opaque, int sprn, int gprn)
375 {
376 gen_helper_store_asr(cpu_gpr[gprn]);
377 }
378 #endif
379 #endif
380
381 /* PowerPC 601 specific registers */
382 /* RTC */
383 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
384 {
385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
386 }
387
388 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
391 }
392
393 #if !defined(CONFIG_USER_ONLY)
394 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
397 }
398
399 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
402 }
403
404 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
405 {
406 DisasContext *ctx = opaque;
407
408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
409 /* Must stop the translation as endianness may have changed */
410 gen_stop_exception(ctx);
411 }
412 #endif
413
414 /* Unified bats */
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
417 {
418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
419 }
420
421 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
422 {
423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
426 }
427
428 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
429 {
430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
433 }
434 #endif
435
436 /* PowerPC 40x specific registers */
437 #if !defined(CONFIG_USER_ONLY)
438 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
439 {
440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
441 }
442
443 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
444 {
445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
446 }
447
448 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
449 {
450 DisasContext *ctx = opaque;
451
452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
453 /* We must stop translation as we may have rebooted */
454 gen_stop_exception(ctx);
455 }
456
457 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
460 }
461
462 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
470 }
471 #endif
472
473 /* PowerPC 403 specific registers */
474 /* PBL1 / PBU1 / PBL2 / PBU2 */
475 #if !defined(CONFIG_USER_ONLY)
476 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
477 {
478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
479 }
480
481 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
482 {
483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
486 }
487
488 static void spr_write_pir (void *opaque, int sprn, int gprn)
489 {
490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
494 }
495 #endif
496
497 /* SPE specific registers */
498 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499 {
500 TCGv_i32 t0 = tcg_temp_new_i32();
501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507 {
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
511 tcg_temp_free_i32(t0);
512 }
513
514 #if !defined(CONFIG_USER_ONLY)
515 /* Callback used to write the exception vector base */
516 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
522 gen_store_spr(sprn, t0);
523 tcg_temp_free(t0);
524 }
525
526 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
527 {
528 DisasContext *ctx = opaque;
529
530 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
544 } else {
545 printf("Trying to write an unknown exception vector %d %03x\n",
546 sprn, sprn);
547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
548 }
549 }
550 #endif
551
552 static inline void vscr_init (CPUPPCState *env, uint32_t val)
553 {
554 env->vscr = val;
555 /* Altivec always uses round-to-nearest */
556 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
557 set_flush_to_zero(vscr_nj, &env->vec_status);
558 }
559
560 #if defined(CONFIG_USER_ONLY)
561 #define spr_register(env, num, name, uea_read, uea_write, \
562 oea_read, oea_write, initial_value) \
563 do { \
564 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
565 } while (0)
566 static inline void _spr_register (CPUPPCState *env, int num,
567 const char *name,
568 void (*uea_read)(void *opaque, int gprn, int sprn),
569 void (*uea_write)(void *opaque, int sprn, int gprn),
570 target_ulong initial_value)
571 #else
572 static inline void spr_register (CPUPPCState *env, int num,
573 const char *name,
574 void (*uea_read)(void *opaque, int gprn, int sprn),
575 void (*uea_write)(void *opaque, int sprn, int gprn),
576 void (*oea_read)(void *opaque, int gprn, int sprn),
577 void (*oea_write)(void *opaque, int sprn, int gprn),
578 target_ulong initial_value)
579 #endif
580 {
581 ppc_spr_t *spr;
582
583 spr = &env->spr_cb[num];
584 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
585 #if !defined(CONFIG_USER_ONLY)
586 spr->oea_read != NULL || spr->oea_write != NULL ||
587 #endif
588 spr->uea_read != NULL || spr->uea_write != NULL) {
589 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
590 exit(1);
591 }
592 #if defined(PPC_DEBUG_SPR)
593 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
594 name, initial_value);
595 #endif
596 spr->name = name;
597 spr->uea_read = uea_read;
598 spr->uea_write = uea_write;
599 #if !defined(CONFIG_USER_ONLY)
600 spr->oea_read = oea_read;
601 spr->oea_write = oea_write;
602 #endif
603 env->spr[num] = initial_value;
604 }
605
606 /* Generic PowerPC SPRs */
607 static void gen_spr_generic (CPUPPCState *env)
608 {
609 /* Integer processing */
610 spr_register(env, SPR_XER, "XER",
611 &spr_read_xer, &spr_write_xer,
612 &spr_read_xer, &spr_write_xer,
613 0x00000000);
614 /* Branch contol */
615 spr_register(env, SPR_LR, "LR",
616 &spr_read_lr, &spr_write_lr,
617 &spr_read_lr, &spr_write_lr,
618 0x00000000);
619 spr_register(env, SPR_CTR, "CTR",
620 &spr_read_ctr, &spr_write_ctr,
621 &spr_read_ctr, &spr_write_ctr,
622 0x00000000);
623 /* Interrupt processing */
624 spr_register(env, SPR_SRR0, "SRR0",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628 spr_register(env, SPR_SRR1, "SRR1",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632 /* Processor control */
633 spr_register(env, SPR_SPRG0, "SPRG0",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_generic,
636 0x00000000);
637 spr_register(env, SPR_SPRG1, "SPRG1",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SPRG2, "SPRG2",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 spr_register(env, SPR_SPRG3, "SPRG3",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 }
650
651 /* SPR common to all non-embedded PowerPC, including 601 */
652 static void gen_spr_ne_601 (CPUPPCState *env)
653 {
654 /* Exception processing */
655 spr_register(env, SPR_DSISR, "DSISR",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_DAR, "DAR",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Timer */
664 spr_register(env, SPR_DECR, "DECR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_decr, &spr_write_decr,
667 0x00000000);
668 /* Memory management */
669 spr_register(env, SPR_SDR1, "SDR1",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, &spr_write_sdr1,
672 0x00000000);
673 }
674
675 /* BATs 0-3 */
676 static void gen_low_BATs (CPUPPCState *env)
677 {
678 #if !defined(CONFIG_USER_ONLY)
679 spr_register(env, SPR_IBAT0U, "IBAT0U",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat, &spr_write_ibatu,
682 0x00000000);
683 spr_register(env, SPR_IBAT0L, "IBAT0L",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat, &spr_write_ibatl,
686 0x00000000);
687 spr_register(env, SPR_IBAT1U, "IBAT1U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat, &spr_write_ibatu,
690 0x00000000);
691 spr_register(env, SPR_IBAT1L, "IBAT1L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat, &spr_write_ibatl,
694 0x00000000);
695 spr_register(env, SPR_IBAT2U, "IBAT2U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat, &spr_write_ibatu,
698 0x00000000);
699 spr_register(env, SPR_IBAT2L, "IBAT2L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatl,
702 0x00000000);
703 spr_register(env, SPR_IBAT3U, "IBAT3U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatu,
706 0x00000000);
707 spr_register(env, SPR_IBAT3L, "IBAT3L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatl,
710 0x00000000);
711 spr_register(env, SPR_DBAT0U, "DBAT0U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat, &spr_write_dbatu,
714 0x00000000);
715 spr_register(env, SPR_DBAT0L, "DBAT0L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat, &spr_write_dbatl,
718 0x00000000);
719 spr_register(env, SPR_DBAT1U, "DBAT1U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat, &spr_write_dbatu,
722 0x00000000);
723 spr_register(env, SPR_DBAT1L, "DBAT1L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat, &spr_write_dbatl,
726 0x00000000);
727 spr_register(env, SPR_DBAT2U, "DBAT2U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat, &spr_write_dbatu,
730 0x00000000);
731 spr_register(env, SPR_DBAT2L, "DBAT2L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatl,
734 0x00000000);
735 spr_register(env, SPR_DBAT3U, "DBAT3U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatu,
738 0x00000000);
739 spr_register(env, SPR_DBAT3L, "DBAT3L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatl,
742 0x00000000);
743 env->nb_BATs += 4;
744 #endif
745 }
746
747 /* BATs 4-7 */
748 static void gen_high_BATs (CPUPPCState *env)
749 {
750 #if !defined(CONFIG_USER_ONLY)
751 spr_register(env, SPR_IBAT4U, "IBAT4U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat_h, &spr_write_ibatu_h,
754 0x00000000);
755 spr_register(env, SPR_IBAT4L, "IBAT4L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat_h, &spr_write_ibatl_h,
758 0x00000000);
759 spr_register(env, SPR_IBAT5U, "IBAT5U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat_h, &spr_write_ibatu_h,
762 0x00000000);
763 spr_register(env, SPR_IBAT5L, "IBAT5L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat_h, &spr_write_ibatl_h,
766 0x00000000);
767 spr_register(env, SPR_IBAT6U, "IBAT6U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat_h, &spr_write_ibatu_h,
770 0x00000000);
771 spr_register(env, SPR_IBAT6L, "IBAT6L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatl_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT7U, "IBAT7U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatu_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT7L, "IBAT7L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatl_h,
782 0x00000000);
783 spr_register(env, SPR_DBAT4U, "DBAT4U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat_h, &spr_write_dbatu_h,
786 0x00000000);
787 spr_register(env, SPR_DBAT4L, "DBAT4L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat_h, &spr_write_dbatl_h,
790 0x00000000);
791 spr_register(env, SPR_DBAT5U, "DBAT5U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat_h, &spr_write_dbatu_h,
794 0x00000000);
795 spr_register(env, SPR_DBAT5L, "DBAT5L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat_h, &spr_write_dbatl_h,
798 0x00000000);
799 spr_register(env, SPR_DBAT6U, "DBAT6U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat_h, &spr_write_dbatu_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT6L, "DBAT6L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatl_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT7U, "DBAT7U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatu_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT7L, "DBAT7L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatl_h,
814 0x00000000);
815 env->nb_BATs += 4;
816 #endif
817 }
818
819 /* Generic PowerPC time base */
820 static void gen_tbl (CPUPPCState *env)
821 {
822 spr_register(env, SPR_VTBL, "TBL",
823 &spr_read_tbl, SPR_NOACCESS,
824 &spr_read_tbl, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_TBL, "TBL",
827 &spr_read_tbl, SPR_NOACCESS,
828 &spr_read_tbl, &spr_write_tbl,
829 0x00000000);
830 spr_register(env, SPR_VTBU, "TBU",
831 &spr_read_tbu, SPR_NOACCESS,
832 &spr_read_tbu, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_TBU, "TBU",
835 &spr_read_tbu, SPR_NOACCESS,
836 &spr_read_tbu, &spr_write_tbu,
837 0x00000000);
838 }
839
840 /* Softare table search registers */
841 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
842 {
843 #if !defined(CONFIG_USER_ONLY)
844 env->nb_tlb = nb_tlbs;
845 env->nb_ways = nb_ways;
846 env->id_tlbs = 1;
847 env->tlb_type = TLB_6XX;
848 spr_register(env, SPR_DMISS, "DMISS",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_generic, SPR_NOACCESS,
851 0x00000000);
852 spr_register(env, SPR_DCMP, "DCMP",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_HASH1, "HASH1",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_generic, SPR_NOACCESS,
859 0x00000000);
860 spr_register(env, SPR_HASH2, "HASH2",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, SPR_NOACCESS,
863 0x00000000);
864 spr_register(env, SPR_IMISS, "IMISS",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_generic, SPR_NOACCESS,
867 0x00000000);
868 spr_register(env, SPR_ICMP, "ICMP",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, SPR_NOACCESS,
871 0x00000000);
872 spr_register(env, SPR_RPA, "RPA",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 #endif
877 }
878
879 /* SPR common to MPC755 and G2 */
880 static void gen_spr_G2_755 (CPUPPCState *env)
881 {
882 /* SGPRs */
883 spr_register(env, SPR_SPRG4, "SPRG4",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887 spr_register(env, SPR_SPRG5, "SPRG5",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 spr_register(env, SPR_SPRG6, "SPRG6",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
894 0x00000000);
895 spr_register(env, SPR_SPRG7, "SPRG7",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
899 }
900
901 /* SPR common to all 7xx PowerPC implementations */
902 static void gen_spr_7xx (CPUPPCState *env)
903 {
904 /* Breakpoints */
905 /* XXX : not implemented */
906 spr_register(env, SPR_DABR, "DABR",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 /* XXX : not implemented */
911 spr_register(env, SPR_IABR, "IABR",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 /* Cache management */
916 /* XXX : not implemented */
917 spr_register(env, SPR_ICTC, "ICTC",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 /* Performance monitors */
922 /* XXX : not implemented */
923 spr_register(env, SPR_MMCR0, "MMCR0",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 /* XXX : not implemented */
928 spr_register(env, SPR_MMCR1, "MMCR1",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_PMC1, "PMC1",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* XXX : not implemented */
938 spr_register(env, SPR_PMC2, "PMC2",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* XXX : not implemented */
943 spr_register(env, SPR_PMC3, "PMC3",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_PMC4, "PMC4",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* XXX : not implemented */
953 spr_register(env, SPR_SIAR, "SIAR",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, SPR_NOACCESS,
956 0x00000000);
957 /* XXX : not implemented */
958 spr_register(env, SPR_UMMCR0, "UMMCR0",
959 &spr_read_ureg, SPR_NOACCESS,
960 &spr_read_ureg, SPR_NOACCESS,
961 0x00000000);
962 /* XXX : not implemented */
963 spr_register(env, SPR_UMMCR1, "UMMCR1",
964 &spr_read_ureg, SPR_NOACCESS,
965 &spr_read_ureg, SPR_NOACCESS,
966 0x00000000);
967 /* XXX : not implemented */
968 spr_register(env, SPR_UPMC1, "UPMC1",
969 &spr_read_ureg, SPR_NOACCESS,
970 &spr_read_ureg, SPR_NOACCESS,
971 0x00000000);
972 /* XXX : not implemented */
973 spr_register(env, SPR_UPMC2, "UPMC2",
974 &spr_read_ureg, SPR_NOACCESS,
975 &spr_read_ureg, SPR_NOACCESS,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_UPMC3, "UPMC3",
979 &spr_read_ureg, SPR_NOACCESS,
980 &spr_read_ureg, SPR_NOACCESS,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_UPMC4, "UPMC4",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_USIAR, "USIAR",
989 &spr_read_ureg, SPR_NOACCESS,
990 &spr_read_ureg, SPR_NOACCESS,
991 0x00000000);
992 /* External access control */
993 /* XXX : not implemented */
994 spr_register(env, SPR_EAR, "EAR",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 }
999
1000 static void gen_spr_thrm (CPUPPCState *env)
1001 {
1002 /* Thermal management */
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_THRM1, "THRM1",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_THRM2, "THRM2",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_THRM3, "THRM3",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 }
1019
1020 /* SPR specific to PowerPC 604 implementation */
1021 static void gen_spr_604 (CPUPPCState *env)
1022 {
1023 /* Processor identification */
1024 spr_register(env, SPR_PIR, "PIR",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_pir,
1027 0x00000000);
1028 /* Breakpoints */
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_IABR, "IABR",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_DABR, "DABR",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* Performance counters */
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_MMCR0, "MMCR0",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_PMC1, "PMC1",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_PMC2, "PMC2",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_SIAR, "SIAR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, SPR_NOACCESS,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_SDA, "SDA",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, SPR_NOACCESS,
1064 0x00000000);
1065 /* External access control */
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_EAR, "EAR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 }
1072
1073 /* SPR specific to PowerPC 603 implementation */
1074 static void gen_spr_603 (CPUPPCState *env)
1075 {
1076 /* External access control */
1077 /* XXX : not implemented */
1078 spr_register(env, SPR_EAR, "EAR",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, &spr_write_generic,
1081 0x00000000);
1082 }
1083
1084 /* SPR specific to PowerPC G2 implementation */
1085 static void gen_spr_G2 (CPUPPCState *env)
1086 {
1087 /* Memory base address */
1088 /* MBAR */
1089 /* XXX : not implemented */
1090 spr_register(env, SPR_MBAR, "MBAR",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
1094 /* Exception processing */
1095 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
1099 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_generic, &spr_write_generic,
1102 0x00000000);
1103 /* Breakpoints */
1104 /* XXX : not implemented */
1105 spr_register(env, SPR_DABR, "DABR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 /* XXX : not implemented */
1110 spr_register(env, SPR_DABR2, "DABR2",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 /* XXX : not implemented */
1115 spr_register(env, SPR_IABR, "IABR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_IABR2, "IABR2",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_IBCR, "IBCR",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_DBCR, "DBCR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 }
1135
1136 /* SPR specific to PowerPC 602 implementation */
1137 static void gen_spr_602 (CPUPPCState *env)
1138 {
1139 /* ESA registers */
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_SER, "SER",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_SEBR, "SEBR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_ESASRR, "ESASRR",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* Floating point status */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_SP, "SP",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* XXX : not implemented */
1162 spr_register(env, SPR_LT, "LT",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_generic,
1165 0x00000000);
1166 /* Watchdog timer */
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_TCR, "TCR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* Interrupt base */
1173 spr_register(env, SPR_IBR, "IBR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_IABR, "IABR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 }
1183
1184 /* SPR specific to PowerPC 601 implementation */
1185 static void gen_spr_601 (CPUPPCState *env)
1186 {
1187 /* Multiplication/division register */
1188 /* MQ */
1189 spr_register(env, SPR_MQ, "MQ",
1190 &spr_read_generic, &spr_write_generic,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193 /* RTC registers */
1194 spr_register(env, SPR_601_RTCU, "RTCU",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 SPR_NOACCESS, &spr_write_601_rtcu,
1197 0x00000000);
1198 spr_register(env, SPR_601_VRTCU, "RTCU",
1199 &spr_read_601_rtcu, SPR_NOACCESS,
1200 &spr_read_601_rtcu, SPR_NOACCESS,
1201 0x00000000);
1202 spr_register(env, SPR_601_RTCL, "RTCL",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 SPR_NOACCESS, &spr_write_601_rtcl,
1205 0x00000000);
1206 spr_register(env, SPR_601_VRTCL, "RTCL",
1207 &spr_read_601_rtcl, SPR_NOACCESS,
1208 &spr_read_601_rtcl, SPR_NOACCESS,
1209 0x00000000);
1210 /* Timer */
1211 #if 0 /* ? */
1212 spr_register(env, SPR_601_UDECR, "UDECR",
1213 &spr_read_decr, SPR_NOACCESS,
1214 &spr_read_decr, SPR_NOACCESS,
1215 0x00000000);
1216 #endif
1217 /* External access control */
1218 /* XXX : not implemented */
1219 spr_register(env, SPR_EAR, "EAR",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* Memory management */
1224 #if !defined(CONFIG_USER_ONLY)
1225 spr_register(env, SPR_IBAT0U, "IBAT0U",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_601_ubat, &spr_write_601_ubatu,
1228 0x00000000);
1229 spr_register(env, SPR_IBAT0L, "IBAT0L",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_601_ubat, &spr_write_601_ubatl,
1232 0x00000000);
1233 spr_register(env, SPR_IBAT1U, "IBAT1U",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_601_ubat, &spr_write_601_ubatu,
1236 0x00000000);
1237 spr_register(env, SPR_IBAT1L, "IBAT1L",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_601_ubat, &spr_write_601_ubatl,
1240 0x00000000);
1241 spr_register(env, SPR_IBAT2U, "IBAT2U",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_601_ubat, &spr_write_601_ubatu,
1244 0x00000000);
1245 spr_register(env, SPR_IBAT2L, "IBAT2L",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_601_ubat, &spr_write_601_ubatl,
1248 0x00000000);
1249 spr_register(env, SPR_IBAT3U, "IBAT3U",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_601_ubat, &spr_write_601_ubatu,
1252 0x00000000);
1253 spr_register(env, SPR_IBAT3L, "IBAT3L",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_601_ubat, &spr_write_601_ubatl,
1256 0x00000000);
1257 env->nb_BATs = 4;
1258 #endif
1259 }
1260
1261 static void gen_spr_74xx (CPUPPCState *env)
1262 {
1263 /* Processor identification */
1264 spr_register(env, SPR_PIR, "PIR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_pir,
1267 0x00000000);
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_MMCR2, "MMCR2",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_UMMCR2, "UMMCR2",
1275 &spr_read_ureg, SPR_NOACCESS,
1276 &spr_read_ureg, SPR_NOACCESS,
1277 0x00000000);
1278 /* XXX: not implemented */
1279 spr_register(env, SPR_BAMR, "BAMR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_MSSCR0, "MSSCR0",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* Hardware implementation registers */
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_HID0, "HID0",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_HID1, "HID1",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* Altivec */
1300 spr_register(env, SPR_VRSAVE, "VRSAVE",
1301 &spr_read_generic, &spr_write_generic,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_L2CR, "L2CR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Not strictly an SPR */
1310 vscr_init(env, 0x00010000);
1311 }
1312
1313 static void gen_l3_ctrl (CPUPPCState *env)
1314 {
1315 /* L3CR */
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_L3CR, "L3CR",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 /* L3ITCR0 */
1322 /* XXX : not implemented */
1323 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
1327 /* L3PM */
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_L3PM, "L3PM",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 }
1334
1335 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1336 {
1337 #if !defined(CONFIG_USER_ONLY)
1338 env->nb_tlb = nb_tlbs;
1339 env->nb_ways = nb_ways;
1340 env->id_tlbs = 1;
1341 env->tlb_type = TLB_6XX;
1342 /* XXX : not implemented */
1343 spr_register(env, SPR_PTEHI, "PTEHI",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347 /* XXX : not implemented */
1348 spr_register(env, SPR_PTELO, "PTELO",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 /* XXX : not implemented */
1353 spr_register(env, SPR_TLBMISS, "TLBMISS",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
1357 #endif
1358 }
1359
1360 #if !defined(CONFIG_USER_ONLY)
1361 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1362 {
1363 TCGv t0 = tcg_temp_new();
1364
1365 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1366 gen_store_spr(sprn, t0);
1367 tcg_temp_free(t0);
1368 }
1369
1370 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1371 {
1372 TCGv_i32 t0 = tcg_const_i32(sprn);
1373 gen_helper_booke206_tlbflush(t0);
1374 tcg_temp_free_i32(t0);
1375 }
1376
1377 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1378 {
1379 TCGv_i32 t0 = tcg_const_i32(sprn);
1380 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1381 tcg_temp_free_i32(t0);
1382 }
1383 #endif
1384
1385 static void gen_spr_usprgh (CPUPPCState *env)
1386 {
1387 spr_register(env, SPR_USPRG4, "USPRG4",
1388 &spr_read_ureg, SPR_NOACCESS,
1389 &spr_read_ureg, SPR_NOACCESS,
1390 0x00000000);
1391 spr_register(env, SPR_USPRG5, "USPRG5",
1392 &spr_read_ureg, SPR_NOACCESS,
1393 &spr_read_ureg, SPR_NOACCESS,
1394 0x00000000);
1395 spr_register(env, SPR_USPRG6, "USPRG6",
1396 &spr_read_ureg, SPR_NOACCESS,
1397 &spr_read_ureg, SPR_NOACCESS,
1398 0x00000000);
1399 spr_register(env, SPR_USPRG7, "USPRG7",
1400 &spr_read_ureg, SPR_NOACCESS,
1401 &spr_read_ureg, SPR_NOACCESS,
1402 0x00000000);
1403 }
1404
1405 /* PowerPC BookE SPR */
1406 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1407 {
1408 const char *ivor_names[64] = {
1409 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1410 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1411 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1412 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1413 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1414 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1415 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1416 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1417 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1418 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1419 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1420 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1421 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1422 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1423 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1424 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1425 };
1426 #define SPR_BOOKE_IVORxx (-1)
1427 int ivor_sprn[64] = {
1428 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1429 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1430 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1431 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1432 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1435 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1437 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1438 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1439 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1444 };
1445 int i;
1446
1447 /* Interrupt processing */
1448 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
1452 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456 /* Debug */
1457 /* XXX : not implemented */
1458 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 /* XXX : not implemented */
1463 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 /* XXX : not implemented */
1468 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* XXX : not implemented */
1478 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 /* XXX : not implemented */
1483 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 /* XXX : not implemented */
1488 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_clear,
1496 0x00000000);
1497 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_BOOKE_ESR, "ESR",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_excp_prefix,
1508 0x00000000);
1509 /* Exception vectors */
1510 for (i = 0; i < 64; i++) {
1511 if (ivor_mask & (1ULL << i)) {
1512 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1513 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1514 exit(1);
1515 }
1516 spr_register(env, ivor_sprn[i], ivor_names[i],
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_excp_vector,
1519 0x00000000);
1520 }
1521 }
1522 spr_register(env, SPR_BOOKE_PID, "PID",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_booke_pid,
1525 0x00000000);
1526 spr_register(env, SPR_BOOKE_TCR, "TCR",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_booke_tcr,
1529 0x00000000);
1530 spr_register(env, SPR_BOOKE_TSR, "TSR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_booke_tsr,
1533 0x00000000);
1534 /* Timer */
1535 spr_register(env, SPR_DECR, "DECR",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_decr, &spr_write_decr,
1538 0x00000000);
1539 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 SPR_NOACCESS, &spr_write_generic,
1542 0x00000000);
1543 /* SPRGs */
1544 spr_register(env, SPR_USPRG0, "USPRG0",
1545 &spr_read_generic, &spr_write_generic,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 spr_register(env, SPR_SPRG4, "SPRG4",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 spr_register(env, SPR_SPRG5, "SPRG5",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
1556 spr_register(env, SPR_SPRG6, "SPRG6",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 spr_register(env, SPR_SPRG7, "SPRG7",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 }
1565
1566 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1567 uint32_t maxsize, uint32_t flags,
1568 uint32_t nentries)
1569 {
1570 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1571 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1572 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1573 flags | nentries;
1574 }
1575
1576 /* BookE 2.06 storage control registers */
1577 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1578 uint32_t *tlbncfg)
1579 {
1580 #if !defined(CONFIG_USER_ONLY)
1581 const char *mas_names[8] = {
1582 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1583 };
1584 int mas_sprn[8] = {
1585 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1586 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1587 };
1588 int i;
1589
1590 /* TLB assist registers */
1591 /* XXX : not implemented */
1592 for (i = 0; i < 8; i++) {
1593 if (mas_mask & (1 << i)) {
1594 spr_register(env, mas_sprn[i], mas_names[i],
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 }
1599 }
1600 if (env->nb_pids > 1) {
1601 /* XXX : not implemented */
1602 spr_register(env, SPR_BOOKE_PID1, "PID1",
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_booke_pid,
1605 0x00000000);
1606 }
1607 if (env->nb_pids > 2) {
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_BOOKE_PID2, "PID2",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_booke_pid,
1612 0x00000000);
1613 }
1614 /* XXX : not implemented */
1615 spr_register(env, SPR_MMUCFG, "MMUCFG",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, SPR_NOACCESS,
1618 0x00000000); /* TOFIX */
1619 switch (env->nb_ways) {
1620 case 4:
1621 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, SPR_NOACCESS,
1624 tlbncfg[3]);
1625 /* Fallthru */
1626 case 3:
1627 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, SPR_NOACCESS,
1630 tlbncfg[2]);
1631 /* Fallthru */
1632 case 2:
1633 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, SPR_NOACCESS,
1636 tlbncfg[1]);
1637 /* Fallthru */
1638 case 1:
1639 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, SPR_NOACCESS,
1642 tlbncfg[0]);
1643 /* Fallthru */
1644 case 0:
1645 default:
1646 break;
1647 }
1648 #endif
1649
1650 gen_spr_usprgh(env);
1651 }
1652
1653 /* SPR specific to PowerPC 440 implementation */
1654 static void gen_spr_440 (CPUPPCState *env)
1655 {
1656 /* Cache control */
1657 /* XXX : not implemented */
1658 spr_register(env, SPR_440_DNV0, "DNV0",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_440_DNV1, "DNV1",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_440_DNV2, "DNV2",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_440_DNV3, "DNV3",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_440_DTV0, "DTV0",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_DTV1, "DTV1",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_DTV2, "DTV2",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DTV3, "DTV3",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DVLIM, "DVLIM",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_INV0, "INV0",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_INV1, "INV1",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_INV2, "INV2",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_440_INV3, "INV3",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_440_ITV0, "ITV0",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_440_ITV1, "ITV1",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_ITV2, "ITV2",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_ITV3, "ITV3",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_IVLIM, "IVLIM",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Cache debug */
1748 /* XXX : not implemented */
1749 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, SPR_NOACCESS,
1752 0x00000000);
1753 /* XXX : not implemented */
1754 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, SPR_NOACCESS,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, SPR_NOACCESS,
1762 0x00000000);
1763 /* XXX : not implemented */
1764 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, SPR_NOACCESS,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, SPR_NOACCESS,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_440_DBDR, "DBDR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* Processor control */
1779 spr_register(env, SPR_4xx_CCR0, "CCR0",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, SPR_NOACCESS,
1786 0x00000000);
1787 /* Storage control */
1788 spr_register(env, SPR_440_MMUCR, "MMUCR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 }
1793
1794 /* SPR shared between PowerPC 40x implementations */
1795 static void gen_spr_40x (CPUPPCState *env)
1796 {
1797 /* Cache */
1798 /* not emulated, as Qemu do not emulate caches */
1799 spr_register(env, SPR_40x_DCCR, "DCCR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* not emulated, as Qemu do not emulate caches */
1804 spr_register(env, SPR_40x_ICCR, "ICCR",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 /* not emulated, as Qemu do not emulate caches */
1809 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, SPR_NOACCESS,
1812 0x00000000);
1813 /* Exception */
1814 spr_register(env, SPR_40x_DEAR, "DEAR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_40x_ESR, "ESR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 spr_register(env, SPR_40x_EVPR, "EVPR",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_excp_prefix,
1825 0x00000000);
1826 spr_register(env, SPR_40x_SRR2, "SRR2",
1827 &spr_read_generic, &spr_write_generic,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 spr_register(env, SPR_40x_SRR3, "SRR3",
1831 &spr_read_generic, &spr_write_generic,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* Timers */
1835 spr_register(env, SPR_40x_PIT, "PIT",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_40x_pit, &spr_write_40x_pit,
1838 0x00000000);
1839 spr_register(env, SPR_40x_TCR, "TCR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_booke_tcr,
1842 0x00000000);
1843 spr_register(env, SPR_40x_TSR, "TSR",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_booke_tsr,
1846 0x00000000);
1847 }
1848
1849 /* SPR specific to PowerPC 405 implementation */
1850 static void gen_spr_405 (CPUPPCState *env)
1851 {
1852 /* MMU */
1853 spr_register(env, SPR_40x_PID, "PID",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857 spr_register(env, SPR_4xx_CCR0, "CCR0",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00700000);
1861 /* Debug interface */
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_40x_dbcr0,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_405_DBCR1, "DBCR1",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_40x_DBSR, "DBSR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_clear,
1876 /* Last reset was system reset */
1877 0x00000300);
1878 /* XXX : not implemented */
1879 spr_register(env, SPR_40x_DAC1, "DAC1",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
1883 spr_register(env, SPR_40x_DAC2, "DAC2",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_405_DVC1, "DVC1",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_405_DVC2, "DVC2",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_40x_IAC1, "IAC1",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 spr_register(env, SPR_40x_IAC2, "IAC2",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_405_IAC3, "IAC3",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 /* XXX : not implemented */
1912 spr_register(env, SPR_405_IAC4, "IAC4",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_generic,
1915 0x00000000);
1916 /* Storage control */
1917 /* XXX: TODO: not implemented */
1918 spr_register(env, SPR_405_SLER, "SLER",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_40x_sler,
1921 0x00000000);
1922 spr_register(env, SPR_40x_ZPR, "ZPR",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926 /* XXX : not implemented */
1927 spr_register(env, SPR_405_SU0R, "SU0R",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* SPRG */
1932 spr_register(env, SPR_USPRG0, "USPRG0",
1933 &spr_read_ureg, SPR_NOACCESS,
1934 &spr_read_ureg, SPR_NOACCESS,
1935 0x00000000);
1936 spr_register(env, SPR_SPRG4, "SPRG4",
1937 SPR_NOACCESS, SPR_NOACCESS,
1938 &spr_read_generic, &spr_write_generic,
1939 0x00000000);
1940 spr_register(env, SPR_SPRG5, "SPRG5",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 spr_register(env, SPR_SPRG6, "SPRG6",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 spr_read_generic, &spr_write_generic,
1947 0x00000000);
1948 spr_register(env, SPR_SPRG7, "SPRG7",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 gen_spr_usprgh(env);
1953 }
1954
1955 /* SPR shared between PowerPC 401 & 403 implementations */
1956 static void gen_spr_401_403 (CPUPPCState *env)
1957 {
1958 /* Time base */
1959 spr_register(env, SPR_403_VTBL, "TBL",
1960 &spr_read_tbl, SPR_NOACCESS,
1961 &spr_read_tbl, SPR_NOACCESS,
1962 0x00000000);
1963 spr_register(env, SPR_403_TBL, "TBL",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 SPR_NOACCESS, &spr_write_tbl,
1966 0x00000000);
1967 spr_register(env, SPR_403_VTBU, "TBU",
1968 &spr_read_tbu, SPR_NOACCESS,
1969 &spr_read_tbu, SPR_NOACCESS,
1970 0x00000000);
1971 spr_register(env, SPR_403_TBU, "TBU",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 SPR_NOACCESS, &spr_write_tbu,
1974 0x00000000);
1975 /* Debug */
1976 /* not emulated, as Qemu do not emulate caches */
1977 spr_register(env, SPR_403_CDBCR, "CDBCR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
1981 }
1982
1983 /* SPR specific to PowerPC 401 implementation */
1984 static void gen_spr_401 (CPUPPCState *env)
1985 {
1986 /* Debug interface */
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_DBCR0, "DBCR",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_40x_dbcr0,
1991 0x00000000);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_40x_DBSR, "DBSR",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_clear,
1996 /* Last reset was system reset */
1997 0x00000300);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_40x_DAC1, "DAC",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_40x_IAC1, "IAC",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* Storage control */
2009 /* XXX: TODO: not implemented */
2010 spr_register(env, SPR_405_SLER, "SLER",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_40x_sler,
2013 0x00000000);
2014 /* not emulated, as Qemu never does speculative access */
2015 spr_register(env, SPR_40x_SGR, "SGR",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0xFFFFFFFF);
2019 /* not emulated, as Qemu do not emulate caches */
2020 spr_register(env, SPR_40x_DCWR, "DCWR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024 }
2025
2026 static void gen_spr_401x2 (CPUPPCState *env)
2027 {
2028 gen_spr_401(env);
2029 spr_register(env, SPR_40x_PID, "PID",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 spr_register(env, SPR_40x_ZPR, "ZPR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037 }
2038
2039 /* SPR specific to PowerPC 403 implementation */
2040 static void gen_spr_403 (CPUPPCState *env)
2041 {
2042 /* Debug interface */
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_40x_dbcr0,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_DBSR, "DBSR",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_clear,
2052 /* Last reset was system reset */
2053 0x00000300);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_40x_DAC1, "DAC1",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 /* XXX : not implemented */
2060 spr_register(env, SPR_40x_DAC2, "DAC2",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 /* XXX : not implemented */
2065 spr_register(env, SPR_40x_IAC1, "IAC1",
2066 SPR_NOACCESS, SPR_NOACCESS,
2067 &spr_read_generic, &spr_write_generic,
2068 0x00000000);
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_40x_IAC2, "IAC2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
2074 }
2075
2076 static void gen_spr_403_real (CPUPPCState *env)
2077 {
2078 spr_register(env, SPR_403_PBL1, "PBL1",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_403_pbr, &spr_write_403_pbr,
2081 0x00000000);
2082 spr_register(env, SPR_403_PBU1, "PBU1",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_403_pbr, &spr_write_403_pbr,
2085 0x00000000);
2086 spr_register(env, SPR_403_PBL2, "PBL2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_403_pbr, &spr_write_403_pbr,
2089 0x00000000);
2090 spr_register(env, SPR_403_PBU2, "PBU2",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_403_pbr, &spr_write_403_pbr,
2093 0x00000000);
2094 }
2095
2096 static void gen_spr_403_mmu (CPUPPCState *env)
2097 {
2098 /* MMU */
2099 spr_register(env, SPR_40x_PID, "PID",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2103 spr_register(env, SPR_40x_ZPR, "ZPR",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 }
2108
2109 /* SPR specific to PowerPC compression coprocessor extension */
2110 static void gen_spr_compress (CPUPPCState *env)
2111 {
2112 /* XXX : not implemented */
2113 spr_register(env, SPR_401_SKR, "SKR",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
2117 }
2118
2119 #if defined (TARGET_PPC64)
2120 /* SPR specific to PowerPC 620 */
2121 static void gen_spr_620 (CPUPPCState *env)
2122 {
2123 /* Processor identification */
2124 spr_register(env, SPR_PIR, "PIR",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_pir,
2127 0x00000000);
2128 spr_register(env, SPR_ASR, "ASR",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_asr, &spr_write_asr,
2131 0x00000000);
2132 /* Breakpoints */
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_IABR, "IABR",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_DABR, "DABR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_SIAR, "SIAR",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, SPR_NOACCESS,
2147 0x00000000);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_SDA, "SDA",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, SPR_NOACCESS,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_620_PMC1R, "PMC1",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, SPR_NOACCESS,
2157 0x00000000);
2158 spr_register(env, SPR_620_PMC1W, "PMC1",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 SPR_NOACCESS, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_620_PMC2R, "PMC2",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, SPR_NOACCESS,
2166 0x00000000);
2167 spr_register(env, SPR_620_PMC2W, "PMC2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 SPR_NOACCESS, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, SPR_NOACCESS,
2175 0x00000000);
2176 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 SPR_NOACCESS, &spr_write_generic,
2179 0x00000000);
2180 /* External access control */
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_EAR, "EAR",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186 #if 0 // XXX: check this
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_PMR0, "PMR0",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_620_PMR1, "PMR1",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_PMR2, "PMR2",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_620_PMR3, "PMR3",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_620_PMR4, "PMR4",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_620_PMR5, "PMR5",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_620_PMR6, "PMR6",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_620_PMR7, "PMR7",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_620_PMR8, "PMR8",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_620_PMR9, "PMR9",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_620_PMRA, "PMR10",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_620_PMRB, "PMR11",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_620_PMRC, "PMR12",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_620_PMRD, "PMR13",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_620_PMRE, "PMR14",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_620_PMRF, "PMR15",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 #endif
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_620_L2CR, "L2CR",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_620_L2SR, "L2SR",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 }
2284 #endif /* defined (TARGET_PPC64) */
2285
2286 static void gen_spr_5xx_8xx (CPUPPCState *env)
2287 {
2288 /* Exception processing */
2289 spr_register(env, SPR_DSISR, "DSISR",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 spr_register(env, SPR_DAR, "DAR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* Timer */
2298 spr_register(env, SPR_DECR, "DECR",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_decr, &spr_write_decr,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_EIE, "EIE",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_MPC_EID, "EID",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_MPC_NRI, "NRI",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_MPC_CMPA, "CMPA",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_MPC_CMPB, "CMPB",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_CMPC, "CMPC",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_CMPD, "CMPD",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_ECR, "ECR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_DER, "DER",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPE, "CMPE",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_CMPF, "CMPF",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_CMPG, "CMPG",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_CMPH, "CMPH",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_BAR, "BAR",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_DPDR, "DPDR",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_IMMR, "IMMR",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 }
2403
2404 static void gen_spr_5xx (CPUPPCState *env)
2405 {
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 }
2512
2513 static void gen_spr_8xx (CPUPPCState *env)
2514 {
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 }
2641
2642 // XXX: TODO
2643 /*
2644 * AMR => SPR 29 (Power 2.04)
2645 * CTRL => SPR 136 (Power 2.04)
2646 * CTRL => SPR 152 (Power 2.04)
2647 * SCOMC => SPR 276 (64 bits ?)
2648 * SCOMD => SPR 277 (64 bits ?)
2649 * TBU40 => SPR 286 (Power 2.04 hypv)
2650 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2651 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2652 * HDSISR => SPR 306 (Power 2.04 hypv)
2653 * HDAR => SPR 307 (Power 2.04 hypv)
2654 * PURR => SPR 309 (Power 2.04 hypv)
2655 * HDEC => SPR 310 (Power 2.04 hypv)
2656 * HIOR => SPR 311 (hypv)
2657 * RMOR => SPR 312 (970)
2658 * HRMOR => SPR 313 (Power 2.04 hypv)
2659 * HSRR0 => SPR 314 (Power 2.04 hypv)
2660 * HSRR1 => SPR 315 (Power 2.04 hypv)
2661 * LPCR => SPR 316 (970)
2662 * LPIDR => SPR 317 (970)
2663 * EPR => SPR 702 (Power 2.04 emb)
2664 * perf => 768-783 (Power 2.04)
2665 * perf => 784-799 (Power 2.04)
2666 * PPR => SPR 896 (Power 2.04)
2667 * EPLC => SPR 947 (Power 2.04 emb)
2668 * EPSC => SPR 948 (Power 2.04 emb)
2669 * DABRX => 1015 (Power 2.04 hypv)
2670 * FPECR => SPR 1022 (?)
2671 * ... and more (thermal management, performance counters, ...)
2672 */
2673
2674 /*****************************************************************************/
2675 /* Exception vectors models */
2676 static void init_excp_4xx_real (CPUPPCState *env)
2677 {
2678 #if !defined(CONFIG_USER_ONLY)
2679 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2680 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2681 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2682 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2683 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2684 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2685 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2686 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2687 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2688 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2689 env->hreset_excp_prefix = 0x00000000UL;
2690 env->ivor_mask = 0x0000FFF0UL;
2691 env->ivpr_mask = 0xFFFF0000UL;
2692 /* Hardware reset vector */
2693 env->hreset_vector = 0xFFFFFFFCUL;
2694 #endif
2695 }
2696
2697 static void init_excp_4xx_softmmu (CPUPPCState *env)
2698 {
2699 #if !defined(CONFIG_USER_ONLY)
2700 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2701 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2702 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2703 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2704 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2705 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2706 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2707 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2708 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2709 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2710 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2711 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2712 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2713 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2714 env->hreset_excp_prefix = 0x00000000UL;
2715 env->ivor_mask = 0x0000FFF0UL;
2716 env->ivpr_mask = 0xFFFF0000UL;
2717 /* Hardware reset vector */
2718 env->hreset_vector = 0xFFFFFFFCUL;
2719 #endif
2720 }
2721
2722 static void init_excp_MPC5xx (CPUPPCState *env)
2723 {
2724 #if !defined(CONFIG_USER_ONLY)
2725 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2726 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2731 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2733 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2734 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2735 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2736 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2737 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2739 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2740 env->hreset_excp_prefix = 0x00000000UL;
2741 env->ivor_mask = 0x0000FFF0UL;
2742 env->ivpr_mask = 0xFFFF0000UL;
2743 /* Hardware reset vector */
2744 env->hreset_vector = 0xFFFFFFFCUL;
2745 #endif
2746 }
2747
2748 static void init_excp_MPC8xx (CPUPPCState *env)
2749 {
2750 #if !defined(CONFIG_USER_ONLY)
2751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2752 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2753 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2754 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2755 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2756 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2757 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2758 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2759 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2760 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2761 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2762 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2763 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2764 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2765 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2766 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2767 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2768 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2769 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2770 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2771 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2772 env->hreset_excp_prefix = 0x00000000UL;
2773 env->ivor_mask = 0x0000FFF0UL;
2774 env->ivpr_mask = 0xFFFF0000UL;
2775 /* Hardware reset vector */
2776 env->hreset_vector = 0xFFFFFFFCUL;
2777 #endif
2778 }
2779
2780 static void init_excp_G2 (CPUPPCState *env)
2781 {
2782 #if !defined(CONFIG_USER_ONLY)
2783 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2784 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2785 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2786 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2787 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2788 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2789 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2790 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2791 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2792 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2793 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2794 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2795 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2796 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2797 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2798 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2799 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2800 env->hreset_excp_prefix = 0x00000000UL;
2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
2803 #endif
2804 }
2805
2806 static void init_excp_e200 (CPUPPCState *env)
2807 {
2808 #if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2810 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2811 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2829 env->hreset_excp_prefix = 0x00000000UL;
2830 env->ivor_mask = 0x0000FFF7UL;
2831 env->ivpr_mask = 0xFFFF0000UL;
2832 /* Hardware reset vector */
2833 env->hreset_vector = 0xFFFFFFFCUL;
2834 #endif
2835 }
2836
2837 static void init_excp_BookE (CPUPPCState *env)
2838 {
2839 #if !defined(CONFIG_USER_ONLY)
2840 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2856 env->hreset_excp_prefix = 0x00000000UL;
2857 env->ivor_mask = 0x0000FFE0UL;
2858 env->ivpr_mask = 0xFFFF0000UL;
2859 /* Hardware reset vector */
2860 env->hreset_vector = 0xFFFFFFFCUL;
2861 #endif
2862 }
2863
2864 static void init_excp_601 (CPUPPCState *env)
2865 {
2866 #if !defined(CONFIG_USER_ONLY)
2867 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2868 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2869 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2870 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2871 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2872 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2873 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2874 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2875 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2876 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2877 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2878 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2879 env->hreset_excp_prefix = 0xFFF00000UL;
2880 /* Hardware reset vector */
2881 env->hreset_vector = 0x00000100UL;
2882 #endif
2883 }
2884
2885 static void init_excp_602 (CPUPPCState *env)
2886 {
2887 #if !defined(CONFIG_USER_ONLY)
2888 /* XXX: exception prefix has a special behavior on 602 */
2889 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2890 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2891 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2892 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2893 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2894 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2895 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2896 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2897 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2898 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2899 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2900 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2901 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2902 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2903 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2904 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2905 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2906 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2907 env->hreset_excp_prefix = 0xFFF00000UL;
2908 /* Hardware reset vector */
2909 env->hreset_vector = 0xFFFFFFFCUL;
2910 #endif
2911 }
2912
2913 static void init_excp_603 (CPUPPCState *env)
2914 {
2915 #if !defined(CONFIG_USER_ONLY)
2916 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2917 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2918 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2919 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2920 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2921 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2922 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2923 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2924 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2925 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2926 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2927 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2928 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2929 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2930 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2931 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2932 env->hreset_excp_prefix = 0x00000000UL;
2933 /* Hardware reset vector */
2934 env->hreset_vector = 0xFFFFFFFCUL;
2935 #endif
2936 }
2937
2938 static void init_excp_604 (CPUPPCState *env)
2939 {
2940 #if !defined(CONFIG_USER_ONLY)
2941 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2942 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2943 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2946 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2947 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2948 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2949 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2950 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2951 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2952 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2953 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2954 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2955 env->hreset_excp_prefix = 0xFFF00000UL;
2956 /* Hardware reset vector */
2957 env->hreset_vector = 0x00000100UL;
2958 #endif
2959 }
2960
2961 #if defined(TARGET_PPC64)
2962 static void init_excp_620 (CPUPPCState *env)
2963 {
2964 #if !defined(CONFIG_USER_ONLY)
2965 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2966 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2967 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2968 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2969 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2970 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2971 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2972 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2973 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2974 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2975 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2976 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2977 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2978 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2979 env->hreset_excp_prefix = 0xFFF00000UL;
2980 /* Hardware reset vector */
2981 env->hreset_vector = 0x0000000000000100ULL;
2982 #endif
2983 }
2984 #endif /* defined(TARGET_PPC64) */
2985
2986 static void init_excp_7x0 (CPUPPCState *env)
2987 {
2988 #if !defined(CONFIG_USER_ONLY)
2989 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2990 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2991 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2992 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2993 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2994 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2995 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2996 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2997 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2998 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2999 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3000 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3001 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3002 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3003 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3004 env->hreset_excp_prefix = 0x00000000UL;
3005 /* Hardware reset vector */
3006 env->hreset_vector = 0xFFFFFFFCUL;
3007 #endif
3008 }
3009
3010 static void init_excp_750cl (CPUPPCState *env)
3011 {
3012 #if !defined(CONFIG_USER_ONLY)
3013 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3014 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3015 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3016 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3017 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3018 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3019 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3020 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3021 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3022 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3023 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3024 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3025 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3026 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3027 env->hreset_excp_prefix = 0x00000000UL;
3028 /* Hardware reset vector */
3029 env->hreset_vector = 0xFFFFFFFCUL;
3030 #endif
3031 }
3032
3033 static void init_excp_750cx (CPUPPCState *env)
3034 {
3035 #if !defined(CONFIG_USER_ONLY)
3036 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3037 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3038 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3040 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3041 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3042 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3043 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3044 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3047 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3048 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3049 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3050 env->hreset_excp_prefix = 0x00000000UL;
3051 /* Hardware reset vector */
3052 env->hreset_vector = 0xFFFFFFFCUL;
3053 #endif
3054 }
3055
3056 /* XXX: Check if this is correct */
3057 static void init_excp_7x5 (CPUPPCState *env)
3058 {
3059 #if !defined(CONFIG_USER_ONLY)
3060 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3061 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3062 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3063 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3064 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3065 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3066 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3067 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3068 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3069 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3070 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3071 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3072 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3073 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3074 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3075 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3076 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3077 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3078 env->hreset_excp_prefix = 0x00000000UL;
3079 /* Hardware reset vector */
3080 env->hreset_vector = 0xFFFFFFFCUL;
3081 #endif
3082 }
3083
3084 static void init_excp_7400 (CPUPPCState *env)
3085 {
3086 #if !defined(CONFIG_USER_ONLY)
3087 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3088 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3089 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3090 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3091 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3092 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3093 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3094 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3095 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3096 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3097 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3098 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3099 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3102 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3103 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3104 env->hreset_excp_prefix = 0x00000000UL;
3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
3107 #endif
3108 }
3109
3110 static void init_excp_7450 (CPUPPCState *env)
3111 {
3112 #if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000