vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include <sysemu/kvm.h>
25 #include "kvm_ppc.h"
26 #include "sysemu/arch_init.h"
27 #include "sysemu/cpus.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ppc/ppc.h"
35
36 //#define PPC_DUMP_CPU
37 //#define PPC_DEBUG_SPR
38 //#define PPC_DUMP_SPR_ACCESSES
39 /* #define USE_APPLE_GDB */
40
41 /* Generic callbacks:
42 * do nothing but store/retrieve spr value
43 */
44 static void spr_load_dump_spr(int sprn)
45 {
46 #ifdef PPC_DUMP_SPR_ACCESSES
47 TCGv_i32 t0 = tcg_const_i32(sprn);
48 gen_helper_load_dump_spr(cpu_env, t0);
49 tcg_temp_free_i32(t0);
50 #endif
51 }
52
53 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
54 {
55 gen_load_spr(cpu_gpr[gprn], sprn);
56 spr_load_dump_spr(sprn);
57 }
58
59 static void spr_store_dump_spr(int sprn)
60 {
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0 = tcg_const_i32(sprn);
63 gen_helper_store_dump_spr(cpu_env, t0);
64 tcg_temp_free_i32(t0);
65 #endif
66 }
67
68 static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
69 {
70 gen_store_spr(sprn, cpu_gpr[gprn]);
71 spr_store_dump_spr(sprn);
72 }
73
74 #if !defined(CONFIG_USER_ONLY)
75 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
76 {
77 #ifdef TARGET_PPC64
78 TCGv t0 = tcg_temp_new();
79 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
80 gen_store_spr(sprn, t0);
81 tcg_temp_free(t0);
82 spr_store_dump_spr(sprn);
83 #else
84 spr_write_generic(ctx, sprn, gprn);
85 #endif
86 }
87
88 static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
89 {
90 TCGv t0 = tcg_temp_new();
91 TCGv t1 = tcg_temp_new();
92 gen_load_spr(t0, sprn);
93 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
94 tcg_gen_and_tl(t0, t0, t1);
95 gen_store_spr(sprn, t0);
96 tcg_temp_free(t0);
97 tcg_temp_free(t1);
98 }
99
100 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
101 {
102 }
103
104 #endif
105
106 /* SPR common to all PowerPC */
107 /* XER */
108 static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
109 {
110 gen_read_xer(cpu_gpr[gprn]);
111 }
112
113 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
114 {
115 gen_write_xer(cpu_gpr[gprn]);
116 }
117
118 /* LR */
119 static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
120 {
121 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
122 }
123
124 static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
125 {
126 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
127 }
128
129 /* CFAR */
130 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
131 static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
134 }
135
136 static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
139 }
140 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
141
142 /* CTR */
143 static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
146 }
147
148 static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
151 }
152
153 /* User read access to SPR */
154 /* USPRx */
155 /* UMMCRx */
156 /* UPMCx */
157 /* USIA */
158 /* UDECR */
159 static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
160 {
161 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
162 }
163
164 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
165 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
166 {
167 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
168 }
169 #endif
170
171 /* SPR common to all non-embedded PowerPC */
172 /* DECR */
173 #if !defined(CONFIG_USER_ONLY)
174 static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
175 {
176 if (ctx->tb->cflags & CF_USE_ICOUNT) {
177 gen_io_start();
178 }
179 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
180 if (ctx->tb->cflags & CF_USE_ICOUNT) {
181 gen_io_end();
182 gen_stop_exception(ctx);
183 }
184 }
185
186 static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
187 {
188 if (ctx->tb->cflags & CF_USE_ICOUNT) {
189 gen_io_start();
190 }
191 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
192 if (ctx->tb->cflags & CF_USE_ICOUNT) {
193 gen_io_end();
194 gen_stop_exception(ctx);
195 }
196 }
197 #endif
198
199 /* SPR common to all non-embedded PowerPC, except 601 */
200 /* Time base */
201 static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
202 {
203 if (ctx->tb->cflags & CF_USE_ICOUNT) {
204 gen_io_start();
205 }
206 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
207 if (ctx->tb->cflags & CF_USE_ICOUNT) {
208 gen_io_end();
209 gen_stop_exception(ctx);
210 }
211 }
212
213 static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
214 {
215 if (ctx->tb->cflags & CF_USE_ICOUNT) {
216 gen_io_start();
217 }
218 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
219 if (ctx->tb->cflags & CF_USE_ICOUNT) {
220 gen_io_end();
221 gen_stop_exception(ctx);
222 }
223 }
224
225 __attribute__ (( unused ))
226 static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
227 {
228 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
229 }
230
231 __attribute__ (( unused ))
232 static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
233 {
234 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
235 }
236
237 #if !defined(CONFIG_USER_ONLY)
238 static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
239 {
240 if (ctx->tb->cflags & CF_USE_ICOUNT) {
241 gen_io_start();
242 }
243 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
244 if (ctx->tb->cflags & CF_USE_ICOUNT) {
245 gen_io_end();
246 gen_stop_exception(ctx);
247 }
248 }
249
250 static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
251 {
252 if (ctx->tb->cflags & CF_USE_ICOUNT) {
253 gen_io_start();
254 }
255 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
256 if (ctx->tb->cflags & CF_USE_ICOUNT) {
257 gen_io_end();
258 gen_stop_exception(ctx);
259 }
260 }
261
262 __attribute__ (( unused ))
263 static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
264 {
265 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
266 }
267
268 __attribute__ (( unused ))
269 static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
270 {
271 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
272 }
273
274 #if defined(TARGET_PPC64)
275 __attribute__ (( unused ))
276 static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
277 {
278 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
279 }
280 #endif
281 #endif
282
283 #if !defined(CONFIG_USER_ONLY)
284 /* IBAT0U...IBAT0U */
285 /* IBAT0L...IBAT7L */
286 static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
287 {
288 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
289 }
290
291 static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
292 {
293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
294 }
295
296 static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
297 {
298 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
299 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
300 tcg_temp_free_i32(t0);
301 }
302
303 static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
304 {
305 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
306 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
307 tcg_temp_free_i32(t0);
308 }
309
310 static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
311 {
312 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
313 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
314 tcg_temp_free_i32(t0);
315 }
316
317 static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
318 {
319 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
320 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
321 tcg_temp_free_i32(t0);
322 }
323
324 /* DBAT0U...DBAT7U */
325 /* DBAT0L...DBAT7L */
326 static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
327 {
328 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
329 }
330
331 static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
332 {
333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
334 }
335
336 static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
337 {
338 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
339 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
340 tcg_temp_free_i32(t0);
341 }
342
343 static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
344 {
345 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
346 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
347 tcg_temp_free_i32(t0);
348 }
349
350 static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
351 {
352 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
353 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
354 tcg_temp_free_i32(t0);
355 }
356
357 static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
358 {
359 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
360 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
361 tcg_temp_free_i32(t0);
362 }
363
364 /* SDR1 */
365 static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
366 {
367 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
368 }
369
370 /* 64 bits PowerPC specific SPRs */
371 #if defined(TARGET_PPC64)
372 static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
373 {
374 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
375 }
376
377 static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
378 {
379 TCGv t0 = tcg_temp_new();
380 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
381 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
382 tcg_temp_free(t0);
383 }
384 #endif
385 #endif
386
387 /* PowerPC 601 specific registers */
388 /* RTC */
389 static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
390 {
391 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
392 }
393
394 static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
397 }
398
399 #if !defined(CONFIG_USER_ONLY)
400 static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
401 {
402 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
403 }
404
405 static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
411 {
412 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
413 /* Must stop the translation as endianness may have changed */
414 gen_stop_exception(ctx);
415 }
416 #endif
417
418 /* Unified bats */
419 #if !defined(CONFIG_USER_ONLY)
420 static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
421 {
422 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
423 }
424
425 static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
426 {
427 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
428 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
429 tcg_temp_free_i32(t0);
430 }
431
432 static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
433 {
434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
435 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
436 tcg_temp_free_i32(t0);
437 }
438 #endif
439
440 /* PowerPC 40x specific registers */
441 #if !defined(CONFIG_USER_ONLY)
442 static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
443 {
444 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
445 }
446
447 static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
448 {
449 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
450 }
451
452 static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
453 {
454 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
455 /* We must stop translation as we may have rebooted */
456 gen_stop_exception(ctx);
457 }
458
459 static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
460 {
461 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
462 }
463
464 static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
465 {
466 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
467 }
468
469 static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
470 {
471 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
472 }
473 #endif
474
475 /* PowerPC 403 specific registers */
476 /* PBL1 / PBU1 / PBL2 / PBU2 */
477 #if !defined(CONFIG_USER_ONLY)
478 static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
479 {
480 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
481 }
482
483 static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
484 {
485 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
486 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
487 tcg_temp_free_i32(t0);
488 }
489
490 static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
491 {
492 TCGv t0 = tcg_temp_new();
493 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
494 gen_store_spr(SPR_PIR, t0);
495 tcg_temp_free(t0);
496 }
497 #endif
498
499 /* SPE specific registers */
500 static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
501 {
502 TCGv_i32 t0 = tcg_temp_new_i32();
503 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
504 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
505 tcg_temp_free_i32(t0);
506 }
507
508 static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
509 {
510 TCGv_i32 t0 = tcg_temp_new_i32();
511 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
512 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
513 tcg_temp_free_i32(t0);
514 }
515
516 #if !defined(CONFIG_USER_ONLY)
517 /* Callback used to write the exception vector base */
518 static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
519 {
520 TCGv t0 = tcg_temp_new();
521 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
522 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
523 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
524 gen_store_spr(sprn, t0);
525 tcg_temp_free(t0);
526 }
527
528 static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
529 {
530 int sprn_offs;
531
532 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
533 sprn_offs = sprn - SPR_BOOKE_IVOR0;
534 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
535 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
536 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
537 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
538 } else {
539 printf("Trying to write an unknown exception vector %d %03x\n",
540 sprn, sprn);
541 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
542 return;
543 }
544
545 TCGv t0 = tcg_temp_new();
546 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
547 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
548 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
549 gen_store_spr(sprn, t0);
550 tcg_temp_free(t0);
551 }
552 #endif
553
554 static inline void vscr_init (CPUPPCState *env, uint32_t val)
555 {
556 env->vscr = val;
557 /* Altivec always uses round-to-nearest */
558 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
559 set_flush_to_zero(vscr_nj, &env->vec_status);
560 }
561
562 #ifdef CONFIG_USER_ONLY
563 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
564 oea_read, oea_write, one_reg_id, initial_value) \
565 _spr_register(env, num, name, uea_read, uea_write, initial_value)
566 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
567 oea_read, oea_write, hea_read, hea_write, \
568 one_reg_id, initial_value) \
569 _spr_register(env, num, name, uea_read, uea_write, initial_value)
570 #else
571 #if !defined(CONFIG_KVM)
572 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
573 oea_read, oea_write, one_reg_id, initial_value) \
574 _spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, oea_read, oea_write, initial_value)
576 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, hea_read, hea_write, \
578 one_reg_id, initial_value) \
579 _spr_register(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, hea_read, hea_write, initial_value)
581 #else
582 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, one_reg_id, initial_value) \
584 _spr_register(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, oea_read, oea_write, \
586 one_reg_id, initial_value)
587 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
588 oea_read, oea_write, hea_read, hea_write, \
589 one_reg_id, initial_value) \
590 _spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, hea_read, hea_write, \
592 one_reg_id, initial_value)
593 #endif
594 #endif
595
596 #define spr_register(env, num, name, uea_read, uea_write, \
597 oea_read, oea_write, initial_value) \
598 spr_register_kvm(env, num, name, uea_read, uea_write, \
599 oea_read, oea_write, 0, initial_value)
600
601 #define spr_register_hv(env, num, name, uea_read, uea_write, \
602 oea_read, oea_write, hea_read, hea_write, \
603 initial_value) \
604 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
605 oea_read, oea_write, hea_read, hea_write, \
606 0, initial_value)
607
608 static inline void _spr_register(CPUPPCState *env, int num,
609 const char *name,
610 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
611 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
612 #if !defined(CONFIG_USER_ONLY)
613
614 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
615 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
616 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
617 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
618 #endif
619 #if defined(CONFIG_KVM)
620 uint64_t one_reg_id,
621 #endif
622 target_ulong initial_value)
623 {
624 ppc_spr_t *spr;
625
626 spr = &env->spr_cb[num];
627 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
628 #if !defined(CONFIG_USER_ONLY)
629 spr->oea_read != NULL || spr->oea_write != NULL ||
630 #endif
631 spr->uea_read != NULL || spr->uea_write != NULL) {
632 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
633 exit(1);
634 }
635 #if defined(PPC_DEBUG_SPR)
636 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
637 name, initial_value);
638 #endif
639 spr->name = name;
640 spr->uea_read = uea_read;
641 spr->uea_write = uea_write;
642 #if !defined(CONFIG_USER_ONLY)
643 spr->oea_read = oea_read;
644 spr->oea_write = oea_write;
645 spr->hea_read = hea_read;
646 spr->hea_write = hea_write;
647 #endif
648 #if defined(CONFIG_KVM)
649 spr->one_reg_id = one_reg_id,
650 #endif
651 env->spr[num] = spr->default_value = initial_value;
652 }
653
654 /* Generic PowerPC SPRs */
655 static void gen_spr_generic (CPUPPCState *env)
656 {
657 /* Integer processing */
658 spr_register(env, SPR_XER, "XER",
659 &spr_read_xer, &spr_write_xer,
660 &spr_read_xer, &spr_write_xer,
661 0x00000000);
662 /* Branch contol */
663 spr_register(env, SPR_LR, "LR",
664 &spr_read_lr, &spr_write_lr,
665 &spr_read_lr, &spr_write_lr,
666 0x00000000);
667 spr_register(env, SPR_CTR, "CTR",
668 &spr_read_ctr, &spr_write_ctr,
669 &spr_read_ctr, &spr_write_ctr,
670 0x00000000);
671 /* Interrupt processing */
672 spr_register(env, SPR_SRR0, "SRR0",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SRR1, "SRR1",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 /* Processor control */
681 spr_register(env, SPR_SPRG0, "SPRG0",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 spr_register(env, SPR_SPRG1, "SPRG1",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, &spr_write_generic,
688 0x00000000);
689 spr_register(env, SPR_SPRG2, "SPRG2",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, &spr_write_generic,
692 0x00000000);
693 spr_register(env, SPR_SPRG3, "SPRG3",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, &spr_write_generic,
696 0x00000000);
697 }
698
699 /* SPR common to all non-embedded PowerPC, including 601 */
700 static void gen_spr_ne_601 (CPUPPCState *env)
701 {
702 /* Exception processing */
703 spr_register_kvm(env, SPR_DSISR, "DSISR",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_generic, &spr_write_generic,
706 KVM_REG_PPC_DSISR, 0x00000000);
707 spr_register_kvm(env, SPR_DAR, "DAR",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, &spr_write_generic,
710 KVM_REG_PPC_DAR, 0x00000000);
711 /* Timer */
712 spr_register(env, SPR_DECR, "DECR",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_decr, &spr_write_decr,
715 0x00000000);
716 /* Memory management */
717 spr_register(env, SPR_SDR1, "SDR1",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, &spr_write_sdr1,
720 0x00000000);
721 }
722
723 /* BATs 0-3 */
724 static void gen_low_BATs (CPUPPCState *env)
725 {
726 #if !defined(CONFIG_USER_ONLY)
727 spr_register(env, SPR_IBAT0U, "IBAT0U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_ibat, &spr_write_ibatu,
730 0x00000000);
731 spr_register(env, SPR_IBAT0L, "IBAT0L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_ibat, &spr_write_ibatl,
734 0x00000000);
735 spr_register(env, SPR_IBAT1U, "IBAT1U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_ibat, &spr_write_ibatu,
738 0x00000000);
739 spr_register(env, SPR_IBAT1L, "IBAT1L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_ibat, &spr_write_ibatl,
742 0x00000000);
743 spr_register(env, SPR_IBAT2U, "IBAT2U",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_ibat, &spr_write_ibatu,
746 0x00000000);
747 spr_register(env, SPR_IBAT2L, "IBAT2L",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_ibat, &spr_write_ibatl,
750 0x00000000);
751 spr_register(env, SPR_IBAT3U, "IBAT3U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat, &spr_write_ibatu,
754 0x00000000);
755 spr_register(env, SPR_IBAT3L, "IBAT3L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat, &spr_write_ibatl,
758 0x00000000);
759 spr_register(env, SPR_DBAT0U, "DBAT0U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_dbat, &spr_write_dbatu,
762 0x00000000);
763 spr_register(env, SPR_DBAT0L, "DBAT0L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_dbat, &spr_write_dbatl,
766 0x00000000);
767 spr_register(env, SPR_DBAT1U, "DBAT1U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_dbat, &spr_write_dbatu,
770 0x00000000);
771 spr_register(env, SPR_DBAT1L, "DBAT1L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_dbat, &spr_write_dbatl,
774 0x00000000);
775 spr_register(env, SPR_DBAT2U, "DBAT2U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_dbat, &spr_write_dbatu,
778 0x00000000);
779 spr_register(env, SPR_DBAT2L, "DBAT2L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_dbat, &spr_write_dbatl,
782 0x00000000);
783 spr_register(env, SPR_DBAT3U, "DBAT3U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat, &spr_write_dbatu,
786 0x00000000);
787 spr_register(env, SPR_DBAT3L, "DBAT3L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat, &spr_write_dbatl,
790 0x00000000);
791 env->nb_BATs += 4;
792 #endif
793 }
794
795 /* BATs 4-7 */
796 static void gen_high_BATs (CPUPPCState *env)
797 {
798 #if !defined(CONFIG_USER_ONLY)
799 spr_register(env, SPR_IBAT4U, "IBAT4U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat_h, &spr_write_ibatu_h,
802 0x00000000);
803 spr_register(env, SPR_IBAT4L, "IBAT4L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_ibat_h, &spr_write_ibatl_h,
806 0x00000000);
807 spr_register(env, SPR_IBAT5U, "IBAT5U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_ibat_h, &spr_write_ibatu_h,
810 0x00000000);
811 spr_register(env, SPR_IBAT5L, "IBAT5L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_ibat_h, &spr_write_ibatl_h,
814 0x00000000);
815 spr_register(env, SPR_IBAT6U, "IBAT6U",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_ibat_h, &spr_write_ibatu_h,
818 0x00000000);
819 spr_register(env, SPR_IBAT6L, "IBAT6L",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_ibat_h, &spr_write_ibatl_h,
822 0x00000000);
823 spr_register(env, SPR_IBAT7U, "IBAT7U",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_ibat_h, &spr_write_ibatu_h,
826 0x00000000);
827 spr_register(env, SPR_IBAT7L, "IBAT7L",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_ibat_h, &spr_write_ibatl_h,
830 0x00000000);
831 spr_register(env, SPR_DBAT4U, "DBAT4U",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat_h, &spr_write_dbatu_h,
834 0x00000000);
835 spr_register(env, SPR_DBAT4L, "DBAT4L",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_dbat_h, &spr_write_dbatl_h,
838 0x00000000);
839 spr_register(env, SPR_DBAT5U, "DBAT5U",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_dbat_h, &spr_write_dbatu_h,
842 0x00000000);
843 spr_register(env, SPR_DBAT5L, "DBAT5L",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_dbat_h, &spr_write_dbatl_h,
846 0x00000000);
847 spr_register(env, SPR_DBAT6U, "DBAT6U",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_dbat_h, &spr_write_dbatu_h,
850 0x00000000);
851 spr_register(env, SPR_DBAT6L, "DBAT6L",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_dbat_h, &spr_write_dbatl_h,
854 0x00000000);
855 spr_register(env, SPR_DBAT7U, "DBAT7U",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_dbat_h, &spr_write_dbatu_h,
858 0x00000000);
859 spr_register(env, SPR_DBAT7L, "DBAT7L",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_dbat_h, &spr_write_dbatl_h,
862 0x00000000);
863 env->nb_BATs += 4;
864 #endif
865 }
866
867 /* Generic PowerPC time base */
868 static void gen_tbl (CPUPPCState *env)
869 {
870 spr_register(env, SPR_VTBL, "TBL",
871 &spr_read_tbl, SPR_NOACCESS,
872 &spr_read_tbl, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_TBL, "TBL",
875 &spr_read_tbl, SPR_NOACCESS,
876 &spr_read_tbl, &spr_write_tbl,
877 0x00000000);
878 spr_register(env, SPR_VTBU, "TBU",
879 &spr_read_tbu, SPR_NOACCESS,
880 &spr_read_tbu, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_TBU, "TBU",
883 &spr_read_tbu, SPR_NOACCESS,
884 &spr_read_tbu, &spr_write_tbu,
885 0x00000000);
886 }
887
888 /* Softare table search registers */
889 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
890 {
891 #if !defined(CONFIG_USER_ONLY)
892 env->nb_tlb = nb_tlbs;
893 env->nb_ways = nb_ways;
894 env->id_tlbs = 1;
895 env->tlb_type = TLB_6XX;
896 spr_register(env, SPR_DMISS, "DMISS",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, SPR_NOACCESS,
899 0x00000000);
900 spr_register(env, SPR_DCMP, "DCMP",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, SPR_NOACCESS,
903 0x00000000);
904 spr_register(env, SPR_HASH1, "HASH1",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, SPR_NOACCESS,
907 0x00000000);
908 spr_register(env, SPR_HASH2, "HASH2",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, SPR_NOACCESS,
911 0x00000000);
912 spr_register(env, SPR_IMISS, "IMISS",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, SPR_NOACCESS,
915 0x00000000);
916 spr_register(env, SPR_ICMP, "ICMP",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, SPR_NOACCESS,
919 0x00000000);
920 spr_register(env, SPR_RPA, "RPA",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 #endif
925 }
926
927 /* SPR common to MPC755 and G2 */
928 static void gen_spr_G2_755 (CPUPPCState *env)
929 {
930 /* SGPRs */
931 spr_register(env, SPR_SPRG4, "SPRG4",
932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
935 spr_register(env, SPR_SPRG5, "SPRG5",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 spr_register(env, SPR_SPRG6, "SPRG6",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 spr_register(env, SPR_SPRG7, "SPRG7",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 }
948
949 /* SPR common to all 7xx PowerPC implementations */
950 static void gen_spr_7xx (CPUPPCState *env)
951 {
952 /* Breakpoints */
953 /* XXX : not implemented */
954 spr_register_kvm(env, SPR_DABR, "DABR",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 KVM_REG_PPC_DABR, 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_IABR, "IABR",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* Cache management */
964 /* XXX : not implemented */
965 spr_register(env, SPR_ICTC, "ICTC",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* Performance monitors */
970 /* XXX : not implemented */
971 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_7XX_PMC1, "PMC1",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_7XX_PMC2, "PMC2",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_7XX_PMC3, "PMC3",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_7XX_PMC4, "PMC4",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_7XX_SIAR, "SIAR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, SPR_NOACCESS,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1007 &spr_read_ureg, SPR_NOACCESS,
1008 &spr_read_ureg, SPR_NOACCESS,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1012 &spr_read_ureg, SPR_NOACCESS,
1013 &spr_read_ureg, SPR_NOACCESS,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1017 &spr_read_ureg, SPR_NOACCESS,
1018 &spr_read_ureg, SPR_NOACCESS,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1022 &spr_read_ureg, SPR_NOACCESS,
1023 &spr_read_ureg, SPR_NOACCESS,
1024 0x00000000);
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1027 &spr_read_ureg, SPR_NOACCESS,
1028 &spr_read_ureg, SPR_NOACCESS,
1029 0x00000000);
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1032 &spr_read_ureg, SPR_NOACCESS,
1033 &spr_read_ureg, SPR_NOACCESS,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_7XX_USIAR, "USIAR",
1037 &spr_read_ureg, SPR_NOACCESS,
1038 &spr_read_ureg, SPR_NOACCESS,
1039 0x00000000);
1040 /* External access control */
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_EAR, "EAR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 }
1047
1048 #ifdef TARGET_PPC64
1049 #ifndef CONFIG_USER_ONLY
1050 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1051 {
1052 TCGv t0 = tcg_temp_new();
1053 TCGv t1 = tcg_temp_new();
1054 TCGv t2 = tcg_temp_new();
1055
1056 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1057 * spr_write_generic for HV mode in the SPR table
1058 */
1059
1060 /* Build insertion mask into t1 based on context */
1061 if (ctx->pr) {
1062 gen_load_spr(t1, SPR_UAMOR);
1063 } else {
1064 gen_load_spr(t1, SPR_AMOR);
1065 }
1066
1067 /* Mask new bits into t2 */
1068 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1069
1070 /* Load AMR and clear new bits in t0 */
1071 gen_load_spr(t0, SPR_AMR);
1072 tcg_gen_andc_tl(t0, t0, t1);
1073
1074 /* Or'in new bits and write it out */
1075 tcg_gen_or_tl(t0, t0, t2);
1076 gen_store_spr(SPR_AMR, t0);
1077 spr_store_dump_spr(SPR_AMR);
1078
1079 tcg_temp_free(t0);
1080 tcg_temp_free(t1);
1081 tcg_temp_free(t2);
1082 }
1083
1084 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1085 {
1086 TCGv t0 = tcg_temp_new();
1087 TCGv t1 = tcg_temp_new();
1088 TCGv t2 = tcg_temp_new();
1089
1090 /* Note, the HV=1 case is handled earlier by simply using
1091 * spr_write_generic for HV mode in the SPR table
1092 */
1093
1094 /* Build insertion mask into t1 based on context */
1095 gen_load_spr(t1, SPR_AMOR);
1096
1097 /* Mask new bits into t2 */
1098 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1099
1100 /* Load AMR and clear new bits in t0 */
1101 gen_load_spr(t0, SPR_UAMOR);
1102 tcg_gen_andc_tl(t0, t0, t1);
1103
1104 /* Or'in new bits and write it out */
1105 tcg_gen_or_tl(t0, t0, t2);
1106 gen_store_spr(SPR_UAMOR, t0);
1107 spr_store_dump_spr(SPR_UAMOR);
1108
1109 tcg_temp_free(t0);
1110 tcg_temp_free(t1);
1111 tcg_temp_free(t2);
1112 }
1113
1114 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1115 {
1116 TCGv t0 = tcg_temp_new();
1117 TCGv t1 = tcg_temp_new();
1118 TCGv t2 = tcg_temp_new();
1119
1120 /* Note, the HV=1 case is handled earlier by simply using
1121 * spr_write_generic for HV mode in the SPR table
1122 */
1123
1124 /* Build insertion mask into t1 based on context */
1125 gen_load_spr(t1, SPR_AMOR);
1126
1127 /* Mask new bits into t2 */
1128 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1129
1130 /* Load AMR and clear new bits in t0 */
1131 gen_load_spr(t0, SPR_IAMR);
1132 tcg_gen_andc_tl(t0, t0, t1);
1133
1134 /* Or'in new bits and write it out */
1135 tcg_gen_or_tl(t0, t0, t2);
1136 gen_store_spr(SPR_IAMR, t0);
1137 spr_store_dump_spr(SPR_IAMR);
1138
1139 tcg_temp_free(t0);
1140 tcg_temp_free(t1);
1141 tcg_temp_free(t2);
1142 }
1143 #endif /* CONFIG_USER_ONLY */
1144
1145 static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
1146 {
1147 #ifndef CONFIG_USER_ONLY
1148 /* Virtual Page Class Key protection */
1149 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1150 * userspace accessible, 29 is privileged. So we only need to set
1151 * the kvm ONE_REG id on one of them, we use 29 */
1152 spr_register(env, SPR_UAMR, "UAMR",
1153 &spr_read_generic, &spr_write_amr,
1154 &spr_read_generic, &spr_write_amr,
1155 0);
1156 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_amr,
1159 &spr_read_generic, &spr_write_generic,
1160 KVM_REG_PPC_AMR, 0);
1161 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_uamor,
1164 &spr_read_generic, &spr_write_generic,
1165 KVM_REG_PPC_UAMOR, 0);
1166 spr_register_hv(env, SPR_AMOR, "AMOR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0);
1171 if (has_iamr) {
1172 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_iamr,
1175 &spr_read_generic, &spr_write_generic,
1176 KVM_REG_PPC_IAMR, 0);
1177 }
1178 #endif /* !CONFIG_USER_ONLY */
1179 }
1180 #endif /* TARGET_PPC64 */
1181
1182 static void gen_spr_thrm (CPUPPCState *env)
1183 {
1184 /* Thermal management */
1185 /* XXX : not implemented */
1186 spr_register(env, SPR_THRM1, "THRM1",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_THRM2, "THRM2",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_THRM3, "THRM3",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 }
1201
1202 /* SPR specific to PowerPC 604 implementation */
1203 static void gen_spr_604 (CPUPPCState *env)
1204 {
1205 /* Processor identification */
1206 spr_register(env, SPR_PIR, "PIR",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_pir,
1209 0x00000000);
1210 /* Breakpoints */
1211 /* XXX : not implemented */
1212 spr_register(env, SPR_IABR, "IABR",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* XXX : not implemented */
1217 spr_register_kvm(env, SPR_DABR, "DABR",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 KVM_REG_PPC_DABR, 0x00000000);
1221 /* Performance counters */
1222 /* XXX : not implemented */
1223 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 /* XXX : not implemented */
1228 spr_register(env, SPR_7XX_PMC1, "PMC1",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 /* XXX : not implemented */
1233 spr_register(env, SPR_7XX_PMC2, "PMC2",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_generic, &spr_write_generic,
1236 0x00000000);
1237 /* XXX : not implemented */
1238 spr_register(env, SPR_7XX_SIAR, "SIAR",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_generic, SPR_NOACCESS,
1241 0x00000000);
1242 /* XXX : not implemented */
1243 spr_register(env, SPR_SDA, "SDA",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, SPR_NOACCESS,
1246 0x00000000);
1247 /* External access control */
1248 /* XXX : not implemented */
1249 spr_register(env, SPR_EAR, "EAR",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_generic, &spr_write_generic,
1252 0x00000000);
1253 }
1254
1255 /* SPR specific to PowerPC 603 implementation */
1256 static void gen_spr_603 (CPUPPCState *env)
1257 {
1258 /* External access control */
1259 /* XXX : not implemented */
1260 spr_register(env, SPR_EAR, "EAR",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0x00000000);
1264 /* Breakpoints */
1265 /* XXX : not implemented */
1266 spr_register(env, SPR_IABR, "IABR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270
1271 }
1272
1273 /* SPR specific to PowerPC G2 implementation */
1274 static void gen_spr_G2 (CPUPPCState *env)
1275 {
1276 /* Memory base address */
1277 /* MBAR */
1278 /* XXX : not implemented */
1279 spr_register(env, SPR_MBAR, "MBAR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 /* Exception processing */
1284 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292 /* Breakpoints */
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_DABR, "DABR",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_DABR2, "DABR2",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_IABR, "IABR",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* XXX : not implemented */
1309 spr_register(env, SPR_IABR2, "IABR2",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_IBCR, "IBCR",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_DBCR, "DBCR",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 }
1324
1325 /* SPR specific to PowerPC 602 implementation */
1326 static void gen_spr_602 (CPUPPCState *env)
1327 {
1328 /* ESA registers */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_SER, "SER",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_SEBR, "SEBR",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 /* XXX : not implemented */
1340 spr_register(env, SPR_ESASRR, "ESASRR",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, &spr_write_generic,
1343 0x00000000);
1344 /* Floating point status */
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_SP, "SP",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_LT, "LT",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 /* Watchdog timer */
1356 /* XXX : not implemented */
1357 spr_register(env, SPR_TCR, "TCR",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 0x00000000);
1361 /* Interrupt base */
1362 spr_register(env, SPR_IBR, "IBR",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1365 0x00000000);
1366 /* XXX : not implemented */
1367 spr_register(env, SPR_IABR, "IABR",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 }
1372
1373 /* SPR specific to PowerPC 601 implementation */
1374 static void gen_spr_601 (CPUPPCState *env)
1375 {
1376 /* Multiplication/division register */
1377 /* MQ */
1378 spr_register(env, SPR_MQ, "MQ",
1379 &spr_read_generic, &spr_write_generic,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 /* RTC registers */
1383 spr_register(env, SPR_601_RTCU, "RTCU",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 SPR_NOACCESS, &spr_write_601_rtcu,
1386 0x00000000);
1387 spr_register(env, SPR_601_VRTCU, "RTCU",
1388 &spr_read_601_rtcu, SPR_NOACCESS,
1389 &spr_read_601_rtcu, SPR_NOACCESS,
1390 0x00000000);
1391 spr_register(env, SPR_601_RTCL, "RTCL",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 SPR_NOACCESS, &spr_write_601_rtcl,
1394 0x00000000);
1395 spr_register(env, SPR_601_VRTCL, "RTCL",
1396 &spr_read_601_rtcl, SPR_NOACCESS,
1397 &spr_read_601_rtcl, SPR_NOACCESS,
1398 0x00000000);
1399 /* Timer */
1400 #if 0 /* ? */
1401 spr_register(env, SPR_601_UDECR, "UDECR",
1402 &spr_read_decr, SPR_NOACCESS,
1403 &spr_read_decr, SPR_NOACCESS,
1404 0x00000000);
1405 #endif
1406 /* External access control */
1407 /* XXX : not implemented */
1408 spr_register(env, SPR_EAR, "EAR",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412 /* Memory management */
1413 #if !defined(CONFIG_USER_ONLY)
1414 spr_register(env, SPR_IBAT0U, "IBAT0U",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_601_ubat, &spr_write_601_ubatu,
1417 0x00000000);
1418 spr_register(env, SPR_IBAT0L, "IBAT0L",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 &spr_read_601_ubat, &spr_write_601_ubatl,
1421 0x00000000);
1422 spr_register(env, SPR_IBAT1U, "IBAT1U",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_601_ubat, &spr_write_601_ubatu,
1425 0x00000000);
1426 spr_register(env, SPR_IBAT1L, "IBAT1L",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_601_ubat, &spr_write_601_ubatl,
1429 0x00000000);
1430 spr_register(env, SPR_IBAT2U, "IBAT2U",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_601_ubat, &spr_write_601_ubatu,
1433 0x00000000);
1434 spr_register(env, SPR_IBAT2L, "IBAT2L",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_601_ubat, &spr_write_601_ubatl,
1437 0x00000000);
1438 spr_register(env, SPR_IBAT3U, "IBAT3U",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_601_ubat, &spr_write_601_ubatu,
1441 0x00000000);
1442 spr_register(env, SPR_IBAT3L, "IBAT3L",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_601_ubat, &spr_write_601_ubatl,
1445 0x00000000);
1446 env->nb_BATs = 4;
1447 #endif
1448 }
1449
1450 static void gen_spr_74xx (CPUPPCState *env)
1451 {
1452 /* Processor identification */
1453 spr_register(env, SPR_PIR, "PIR",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_pir,
1456 0x00000000);
1457 /* XXX : not implemented */
1458 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 /* XXX : not implemented */
1463 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1464 &spr_read_ureg, SPR_NOACCESS,
1465 &spr_read_ureg, SPR_NOACCESS,
1466 0x00000000);
1467 /* XXX: not implemented */
1468 spr_register(env, SPR_BAMR, "BAMR",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_MSSCR0, "MSSCR0",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* Hardware implementation registers */
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_HID0, "HID0",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_HID1, "HID1",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* Altivec */
1489 spr_register(env, SPR_VRSAVE, "VRSAVE",
1490 &spr_read_generic, &spr_write_generic,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_L2CR, "L2CR",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, spr_access_nop,
1497 0x00000000);
1498 /* Not strictly an SPR */
1499 vscr_init(env, 0x00010000);
1500 }
1501
1502 static void gen_l3_ctrl (CPUPPCState *env)
1503 {
1504 /* L3CR */
1505 /* XXX : not implemented */
1506 spr_register(env, SPR_L3CR, "L3CR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510 /* L3ITCR0 */
1511 /* XXX : not implemented */
1512 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 &spr_read_generic, &spr_write_generic,
1515 0x00000000);
1516 /* L3PM */
1517 /* XXX : not implemented */
1518 spr_register(env, SPR_L3PM, "L3PM",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 }
1523
1524 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1525 {
1526 #if !defined(CONFIG_USER_ONLY)
1527 env->nb_tlb = nb_tlbs;
1528 env->nb_ways = nb_ways;
1529 env->id_tlbs = 1;
1530 env->tlb_type = TLB_6XX;
1531 /* XXX : not implemented */
1532 spr_register(env, SPR_PTEHI, "PTEHI",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
1536 /* XXX : not implemented */
1537 spr_register(env, SPR_PTELO, "PTELO",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541 /* XXX : not implemented */
1542 spr_register(env, SPR_TLBMISS, "TLBMISS",
1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
1546 #endif
1547 }
1548
1549 #if !defined(CONFIG_USER_ONLY)
1550 static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1551 {
1552 TCGv t0 = tcg_temp_new();
1553
1554 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1555 gen_store_spr(sprn, t0);
1556 tcg_temp_free(t0);
1557 }
1558
1559 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1560 {
1561 TCGv t0 = tcg_temp_new();
1562
1563 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1564 gen_store_spr(sprn, t0);
1565 tcg_temp_free(t0);
1566 }
1567
1568 static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1569 {
1570 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1571 }
1572
1573 static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1574 {
1575 TCGv_i32 t0 = tcg_const_i32(sprn);
1576 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1577 tcg_temp_free_i32(t0);
1578 }
1579 #endif
1580
1581 static void gen_spr_usprgh (CPUPPCState *env)
1582 {
1583 spr_register(env, SPR_USPRG4, "USPRG4",
1584 &spr_read_ureg, SPR_NOACCESS,
1585 &spr_read_ureg, SPR_NOACCESS,
1586 0x00000000);
1587 spr_register(env, SPR_USPRG5, "USPRG5",
1588 &spr_read_ureg, SPR_NOACCESS,
1589 &spr_read_ureg, SPR_NOACCESS,
1590 0x00000000);
1591 spr_register(env, SPR_USPRG6, "USPRG6",
1592 &spr_read_ureg, SPR_NOACCESS,
1593 &spr_read_ureg, SPR_NOACCESS,
1594 0x00000000);
1595 spr_register(env, SPR_USPRG7, "USPRG7",
1596 &spr_read_ureg, SPR_NOACCESS,
1597 &spr_read_ureg, SPR_NOACCESS,
1598 0x00000000);
1599 }
1600
1601 /* PowerPC BookE SPR */
1602 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1603 {
1604 const char *ivor_names[64] = {
1605 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1606 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1607 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1608 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1609 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1610 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1611 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1612 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1613 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1614 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1615 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1616 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1617 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1618 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1619 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1620 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1621 };
1622 #define SPR_BOOKE_IVORxx (-1)
1623 int ivor_sprn[64] = {
1624 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1625 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1626 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1627 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1628 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1629 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1630 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1631 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1632 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1633 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1634 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1635 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1636 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1637 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1638 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1639 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1640 };
1641 int i;
1642
1643 /* Interrupt processing */
1644 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652 /* Debug */
1653 /* XXX : not implemented */
1654 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_40x_dbcr0,
1677 0x00000000);
1678 /* XXX : not implemented */
1679 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 /* XXX : not implemented */
1684 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_clear,
1692 0x00000000);
1693 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 spr_register(env, SPR_BOOKE_ESR, "ESR",
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_excp_prefix,
1704 0x00000000);
1705 /* Exception vectors */
1706 for (i = 0; i < 64; i++) {
1707 if (ivor_mask & (1ULL << i)) {
1708 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1709 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1710 exit(1);
1711 }
1712 spr_register(env, ivor_sprn[i], ivor_names[i],
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_excp_vector,
1715 0x00000000);
1716 }
1717 }
1718 spr_register(env, SPR_BOOKE_PID, "PID",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_booke_pid,
1721 0x00000000);
1722 spr_register(env, SPR_BOOKE_TCR, "TCR",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, &spr_write_booke_tcr,
1725 0x00000000);
1726 spr_register(env, SPR_BOOKE_TSR, "TSR",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_booke_tsr,
1729 0x00000000);
1730 /* Timer */
1731 spr_register(env, SPR_DECR, "DECR",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_decr, &spr_write_decr,
1734 0x00000000);
1735 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 SPR_NOACCESS, &spr_write_generic,
1738 0x00000000);
1739 /* SPRGs */
1740 spr_register(env, SPR_USPRG0, "USPRG0",
1741 &spr_read_generic, &spr_write_generic,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744 spr_register(env, SPR_SPRG4, "SPRG4",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 spr_register(env, SPR_SPRG5, "SPRG5",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 spr_register(env, SPR_SPRG6, "SPRG6",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, &spr_write_generic,
1755 0x00000000);
1756 spr_register(env, SPR_SPRG7, "SPRG7",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 }
1761
1762 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1763 uint32_t maxsize, uint32_t flags,
1764 uint32_t nentries)
1765 {
1766 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1767 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1768 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1769 flags | nentries;
1770 }
1771
1772 /* BookE 2.06 storage control registers */
1773 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1774 uint32_t *tlbncfg)
1775 {
1776 #if !defined(CONFIG_USER_ONLY)
1777 const char *mas_names[8] = {
1778 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1779 };
1780 int mas_sprn[8] = {
1781 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1782 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1783 };
1784 int i;
1785
1786 /* TLB assist registers */
1787 /* XXX : not implemented */
1788 for (i = 0; i < 8; i++) {
1789 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1790 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1791 uea_write = &spr_write_generic;
1792 }
1793 if (mas_mask & (1 << i)) {
1794 spr_register(env, mas_sprn[i], mas_names[i],
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, uea_write,
1797 0x00000000);
1798 }
1799 }
1800 if (env->nb_pids > 1) {
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_BOOKE_PID1, "PID1",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_booke_pid,
1805 0x00000000);
1806 }
1807 if (env->nb_pids > 2) {
1808 /* XXX : not implemented */
1809 spr_register(env, SPR_BOOKE_PID2, "PID2",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, &spr_write_booke_pid,
1812 0x00000000);
1813 }
1814 /* XXX : not implemented */
1815 spr_register(env, SPR_MMUCFG, "MMUCFG",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, SPR_NOACCESS,
1818 0x00000000); /* TOFIX */
1819 switch (env->nb_ways) {
1820 case 4:
1821 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, SPR_NOACCESS,
1824 tlbncfg[3]);
1825 /* Fallthru */
1826 case 3:
1827 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, SPR_NOACCESS,
1830 tlbncfg[2]);
1831 /* Fallthru */
1832 case 2:
1833 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, SPR_NOACCESS,
1836 tlbncfg[1]);
1837 /* Fallthru */
1838 case 1:
1839 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, SPR_NOACCESS,
1842 tlbncfg[0]);
1843 /* Fallthru */
1844 case 0:
1845 default:
1846 break;
1847 }
1848 #endif
1849
1850 gen_spr_usprgh(env);
1851 }
1852
1853 /* SPR specific to PowerPC 440 implementation */
1854 static void gen_spr_440 (CPUPPCState *env)
1855 {
1856 /* Cache control */
1857 /* XXX : not implemented */
1858 spr_register(env, SPR_440_DNV0, "DNV0",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_440_DNV1, "DNV1",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_generic,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_440_DNV2, "DNV2",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_440_DNV3, "DNV3",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877 /* XXX : not implemented */
1878 spr_register(env, SPR_440_DTV0, "DTV0",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 /* XXX : not implemented */
1883 spr_register(env, SPR_440_DTV1, "DTV1",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887 /* XXX : not implemented */
1888 spr_register(env, SPR_440_DTV2, "DTV2",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_440_DTV3, "DTV3",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_440_DVLIM, "DVLIM",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 /* XXX : not implemented */
1903 spr_register(env, SPR_440_INV0, "INV0",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_440_INV1, "INV1",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_440_INV2, "INV2",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* XXX : not implemented */
1918 spr_register(env, SPR_440_INV3, "INV3",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
1922 /* XXX : not implemented */
1923 spr_register(env, SPR_440_ITV0, "ITV0",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_440_ITV1, "ITV1",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_440_ITV2, "ITV2",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_440_ITV3, "ITV3",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* XXX : not implemented */
1943 spr_register(env, SPR_440_IVLIM, "IVLIM",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 /* Cache debug */
1948 /* XXX : not implemented */
1949 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, SPR_NOACCESS,
1952 0x00000000);
1953 /* XXX : not implemented */
1954 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1955 SPR_NOACCESS, SPR_NOACCESS,
1956 &spr_read_generic, SPR_NOACCESS,
1957 0x00000000);
1958 /* XXX : not implemented */
1959 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 &spr_read_generic, SPR_NOACCESS,
1962 0x00000000);
1963 /* XXX : not implemented */
1964 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_generic, SPR_NOACCESS,
1967 0x00000000);
1968 /* XXX : not implemented */
1969 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, SPR_NOACCESS,
1972 0x00000000);
1973 /* XXX : not implemented */
1974 spr_register(env, SPR_440_DBDR, "DBDR",
1975 SPR_NOACCESS, SPR_NOACCESS,
1976 &spr_read_generic, &spr_write_generic,
1977 0x00000000);
1978 /* Processor control */
1979 spr_register(env, SPR_4xx_CCR0, "CCR0",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_generic, &spr_write_generic,
1982 0x00000000);
1983 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, SPR_NOACCESS,
1986 0x00000000);
1987 /* Storage control */
1988 spr_register(env, SPR_440_MMUCR, "MMUCR",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 }
1993
1994 /* SPR shared between PowerPC 40x implementations */
1995 static void gen_spr_40x (CPUPPCState *env)
1996 {
1997 /* Cache */
1998 /* not emulated, as QEMU do not emulate caches */
1999 spr_register(env, SPR_40x_DCCR, "DCCR",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* not emulated, as QEMU do not emulate caches */
2004 spr_register(env, SPR_40x_ICCR, "ICCR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* not emulated, as QEMU do not emulate caches */
2009 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, SPR_NOACCESS,
2012 0x00000000);
2013 /* Exception */
2014 spr_register(env, SPR_40x_DEAR, "DEAR",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 spr_register(env, SPR_40x_ESR, "ESR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 spr_register(env, SPR_40x_EVPR, "EVPR",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_excp_prefix,
2025 0x00000000);
2026 spr_register(env, SPR_40x_SRR2, "SRR2",
2027 &spr_read_generic, &spr_write_generic,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 spr_register(env, SPR_40x_SRR3, "SRR3",
2031 &spr_read_generic, &spr_write_generic,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 /* Timers */
2035 spr_register(env, SPR_40x_PIT, "PIT",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_40x_pit, &spr_write_40x_pit,
2038 0x00000000);
2039 spr_register(env, SPR_40x_TCR, "TCR",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_booke_tcr,
2042 0x00000000);
2043 spr_register(env, SPR_40x_TSR, "TSR",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 &spr_read_generic, &spr_write_booke_tsr,
2046 0x00000000);
2047 }
2048
2049 /* SPR specific to PowerPC 405 implementation */
2050 static void gen_spr_405 (CPUPPCState *env)
2051 {
2052 /* MMU */
2053 spr_register(env, SPR_40x_PID, "PID",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057 spr_register(env, SPR_4xx_CCR0, "CCR0",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_generic,
2060 0x00700000);
2061 /* Debug interface */
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_40x_dbcr0,
2066 0x00000000);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_405_DBCR1, "DBCR1",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 /* XXX : not implemented */
2073 spr_register(env, SPR_40x_DBSR, "DBSR",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_clear,
2076 /* Last reset was system reset */
2077 0x00000300);
2078 /* XXX : not implemented */
2079 spr_register(env, SPR_40x_DAC1, "DAC1",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, &spr_write_generic,
2082 0x00000000);
2083 spr_register(env, SPR_40x_DAC2, "DAC2",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 /* XXX : not implemented */
2088 spr_register(env, SPR_405_DVC1, "DVC1",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 /* XXX : not implemented */
2093 spr_register(env, SPR_405_DVC2, "DVC2",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, &spr_write_generic,
2096 0x00000000);
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_40x_IAC1, "IAC1",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 spr_register(env, SPR_40x_IAC2, "IAC2",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, &spr_write_generic,
2105 0x00000000);
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_405_IAC3, "IAC3",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 /* XXX : not implemented */
2112 spr_register(env, SPR_405_IAC4, "IAC4",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_generic, &spr_write_generic,
2115 0x00000000);
2116 /* Storage control */
2117 /* XXX: TODO: not implemented */
2118 spr_register(env, SPR_405_SLER, "SLER",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_40x_sler,
2121 0x00000000);
2122 spr_register(env, SPR_40x_ZPR, "ZPR",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_generic,
2125 0x00000000);
2126 /* XXX : not implemented */
2127 spr_register(env, SPR_405_SU0R, "SU0R",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 /* SPRG */
2132 spr_register(env, SPR_USPRG0, "USPRG0",
2133 &spr_read_ureg, SPR_NOACCESS,
2134 &spr_read_ureg, SPR_NOACCESS,
2135 0x00000000);
2136 spr_register(env, SPR_SPRG4, "SPRG4",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 spr_register(env, SPR_SPRG5, "SPRG5",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 spr_register(env, SPR_SPRG6, "SPRG6",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 spr_read_generic, &spr_write_generic,
2147 0x00000000);
2148 spr_register(env, SPR_SPRG7, "SPRG7",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 spr_read_generic, &spr_write_generic,
2151 0x00000000);
2152 gen_spr_usprgh(env);
2153 }
2154
2155 /* SPR shared between PowerPC 401 & 403 implementations */
2156 static void gen_spr_401_403 (CPUPPCState *env)
2157 {
2158 /* Time base */
2159 spr_register(env, SPR_403_VTBL, "TBL",
2160 &spr_read_tbl, SPR_NOACCESS,
2161 &spr_read_tbl, SPR_NOACCESS,
2162 0x00000000);
2163 spr_register(env, SPR_403_TBL, "TBL",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 SPR_NOACCESS, &spr_write_tbl,
2166 0x00000000);
2167 spr_register(env, SPR_403_VTBU, "TBU",
2168 &spr_read_tbu, SPR_NOACCESS,
2169 &spr_read_tbu, SPR_NOACCESS,
2170 0x00000000);
2171 spr_register(env, SPR_403_TBU, "TBU",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 SPR_NOACCESS, &spr_write_tbu,
2174 0x00000000);
2175 /* Debug */
2176 /* not emulated, as QEMU do not emulate caches */
2177 spr_register(env, SPR_403_CDBCR, "CDBCR",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 }
2182
2183 /* SPR specific to PowerPC 401 implementation */
2184 static void gen_spr_401 (CPUPPCState *env)
2185 {
2186 /* Debug interface */
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_40x_DBCR0, "DBCR",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_40x_dbcr0,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_40x_DBSR, "DBSR",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_clear,
2196 /* Last reset was system reset */
2197 0x00000300);
2198 /* XXX : not implemented */
2199 spr_register(env, SPR_40x_DAC1, "DAC",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 /* XXX : not implemented */
2204 spr_register(env, SPR_40x_IAC1, "IAC",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_generic,
2207 0x00000000);
2208 /* Storage control */
2209 /* XXX: TODO: not implemented */
2210 spr_register(env, SPR_405_SLER, "SLER",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 &spr_read_generic, &spr_write_40x_sler,
2213 0x00000000);
2214 /* not emulated, as QEMU never does speculative access */
2215 spr_register(env, SPR_40x_SGR, "SGR",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0xFFFFFFFF);
2219 /* not emulated, as QEMU do not emulate caches */
2220 spr_register(env, SPR_40x_DCWR, "DCWR",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 }
2225
2226 static void gen_spr_401x2 (CPUPPCState *env)
2227 {
2228 gen_spr_401(env);
2229 spr_register(env, SPR_40x_PID, "PID",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 spr_register(env, SPR_40x_ZPR, "ZPR",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 }
2238
2239 /* SPR specific to PowerPC 403 implementation */
2240 static void gen_spr_403 (CPUPPCState *env)
2241 {
2242 /* Debug interface */
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_40x_dbcr0,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_40x_DBSR, "DBSR",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_clear,
2252 /* Last reset was system reset */
2253 0x00000300);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_40x_DAC1, "DAC1",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_40x_DAC2, "DAC2",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_40x_IAC1, "IAC1",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_40x_IAC2, "IAC2",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 }
2275
2276 static void gen_spr_403_real (CPUPPCState *env)
2277 {
2278 spr_register(env, SPR_403_PBL1, "PBL1",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_403_pbr, &spr_write_403_pbr,
2281 0x00000000);
2282 spr_register(env, SPR_403_PBU1, "PBU1",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_403_pbr, &spr_write_403_pbr,
2285 0x00000000);
2286 spr_register(env, SPR_403_PBL2, "PBL2",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_403_pbr, &spr_write_403_pbr,
2289 0x00000000);
2290 spr_register(env, SPR_403_PBU2, "PBU2",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_403_pbr, &spr_write_403_pbr,
2293 0x00000000);
2294 }
2295
2296 static void gen_spr_403_mmu (CPUPPCState *env)
2297 {
2298 /* MMU */
2299 spr_register(env, SPR_40x_PID, "PID",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 spr_register(env, SPR_40x_ZPR, "ZPR",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 }
2308
2309 /* SPR specific to PowerPC compression coprocessor extension */
2310 static void gen_spr_compress (CPUPPCState *env)
2311 {
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_401_SKR, "SKR",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 }
2318
2319 static void gen_spr_5xx_8xx (CPUPPCState *env)
2320 {
2321 /* Exception processing */
2322 spr_register_kvm(env, SPR_DSISR, "DSISR",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 KVM_REG_PPC_DSISR, 0x00000000);
2326 spr_register_kvm(env, SPR_DAR, "DAR",
2327 SPR_NOACCESS, SPR_NOACCESS,
2328 &spr_read_generic, &spr_write_generic,
2329 KVM_REG_PPC_DAR, 0x00000000);
2330 /* Timer */
2331 spr_register(env, SPR_DECR, "DECR",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_decr, &spr_write_decr,
2334 0x00000000);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_MPC_EIE, "EIE",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_MPC_EID, "EID",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_MPC_NRI, "NRI",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_MPC_CMPA, "CMPA",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_MPC_CMPB, "CMPB",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_MPC_CMPC, "CMPC",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_MPC_CMPD, "CMPD",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_MPC_ECR, "ECR",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_MPC_DER, "DER",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_CMPE, "CMPE",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_CMPF, "CMPF",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_MPC_CMPG, "CMPG",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_MPC_CMPH, "CMPH",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_MPC_BAR, "BAR",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_MPC_DPDR, "DPDR",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_MPC_IMMR, "IMMR",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 }
2436
2437 static void gen_spr_5xx (CPUPPCState *env)
2438 {
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 }
2545
2546 static void gen_spr_8xx (CPUPPCState *env)
2547 {
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 /* XXX : not implemented */
2639 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2640 SPR_NOACCESS, SPR_NOACCESS,
2641 &spr_read_generic, &spr_write_generic,
2642 0x00000000);
2643 /* XXX : not implemented */
2644 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2645 SPR_NOACCESS, SPR_NOACCESS,
2646 &spr_read_generic, &spr_write_generic,
2647 0x00000000);
2648 /* XXX : not implemented */
2649 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2650 SPR_NOACCESS, SPR_NOACCESS,
2651 &spr_read_generic, &spr_write_generic,
2652 0x00000000);
2653 /* XXX : not implemented */
2654 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2655 SPR_NOACCESS, SPR_NOACCESS,
2656 &spr_read_generic, &spr_write_generic,
2657 0x00000000);
2658 /* XXX : not implemented */
2659 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2660 SPR_NOACCESS, SPR_NOACCESS,
2661 &spr_read_generic, &spr_write_generic,
2662 0x00000000);
2663 /* XXX : not implemented */
2664 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2665 SPR_NOACCESS, SPR_NOACCESS,
2666 &spr_read_generic, &spr_write_generic,
2667 0x00000000);
2668 /* XXX : not implemented */
2669 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 }
2674
2675 // XXX: TODO
2676 /*
2677 * AMR => SPR 29 (Power 2.04)
2678 * CTRL => SPR 136 (Power 2.04)
2679 * CTRL => SPR 152 (Power 2.04)
2680 * SCOMC => SPR 276 (64 bits ?)
2681 * SCOMD => SPR 277 (64 bits ?)
2682 * TBU40 => SPR 286 (Power 2.04 hypv)
2683 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2684 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2685 * HDSISR => SPR 306 (Power 2.04 hypv)
2686 * HDAR => SPR 307 (Power 2.04 hypv)
2687 * PURR => SPR 309 (Power 2.04 hypv)
2688 * HDEC => SPR 310 (Power 2.04 hypv)
2689 * HIOR => SPR 311 (hypv)
2690 * RMOR => SPR 312 (970)
2691 * HRMOR => SPR 313 (Power 2.04 hypv)
2692 * HSRR0 => SPR 314 (Power 2.04 hypv)
2693 * HSRR1 => SPR 315 (Power 2.04 hypv)
2694 * LPIDR => SPR 317 (970)
2695 * EPR => SPR 702 (Power 2.04 emb)
2696 * perf => 768-783 (Power 2.04)
2697 * perf => 784-799 (Power 2.04)
2698 * PPR => SPR 896 (Power 2.04)
2699 * EPLC => SPR 947 (Power 2.04 emb)
2700 * EPSC => SPR 948 (Power 2.04 emb)
2701 * DABRX => 1015 (Power 2.04 hypv)
2702 * FPECR => SPR 1022 (?)
2703 * ... and more (thermal management, performance counters, ...)
2704 */
2705
2706 /*****************************************************************************/
2707 /* Exception vectors models */
2708 static void init_excp_4xx_real (CPUPPCState *env)
2709 {
2710 #if !defined(CONFIG_USER_ONLY)
2711 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2712 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2713 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2714 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2715 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2716 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2717 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2718 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2719 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2720 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2721 env->ivor_mask = 0x0000FFF0UL;
2722 env->ivpr_mask = 0xFFFF0000UL;
2723 /* Hardware reset vector */
2724 env->hreset_vector = 0xFFFFFFFCUL;
2725 #endif
2726 }
2727
2728 static void init_excp_4xx_softmmu (CPUPPCState *env)
2729 {
2730 #if !defined(CONFIG_USER_ONLY)
2731 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2732 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2733 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2734 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2735 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2736 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2737 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2738 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2739 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2740 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2741 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2742 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2743 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2744 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2745 env->ivor_mask = 0x0000FFF0UL;
2746 env->ivpr_mask = 0xFFFF0000UL;
2747 /* Hardware reset vector */
2748 env->hreset_vector = 0xFFFFFFFCUL;
2749 #endif
2750 }
2751
2752 static void init_excp_MPC5xx (CPUPPCState *env)
2753 {
2754 #if !defined(CONFIG_USER_ONLY)
2755 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2756 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2757 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2758 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2759 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2760 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2761 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2762 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2763 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2764 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2765 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2766 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2767 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2768 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2769 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2770 env->ivor_mask = 0x0000FFF0UL;
2771 env->ivpr_mask = 0xFFFF0000UL;
2772 /* Hardware reset vector */
2773 env->hreset_vector = 0x00000100UL;
2774 #endif
2775 }
2776
2777 static void init_excp_MPC8xx (CPUPPCState *env)
2778 {
2779 #if !defined(CONFIG_USER_ONLY)
2780 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2781 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2782 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2783 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2784 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2785 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2786 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2787 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2788 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2789 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2790 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2791 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2792 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2793 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2794 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2795 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2796 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2797 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2798 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2799 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2800 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2801 env->ivor_mask = 0x0000FFF0UL;
2802 env->ivpr_mask = 0xFFFF0000UL;
2803 /* Hardware reset vector */
2804 env->hreset_vector = 0x00000100UL;
2805 #endif
2806 }
2807
2808 static void init_excp_G2 (CPUPPCState *env)
2809 {
2810 #if !defined(CONFIG_USER_ONLY)
2811 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2819 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2820 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2821 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2822 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2823 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2824 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2825 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2826 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2827 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2828 /* Hardware reset vector */
2829 env->hreset_vector = 0x00000100UL;
2830 #endif
2831 }
2832
2833 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2834 {
2835 #if !defined(CONFIG_USER_ONLY)
2836 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2837 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2856 env->ivor_mask = 0x0000FFF7UL;
2857 env->ivpr_mask = ivpr_mask;
2858 /* Hardware reset vector */
2859 env->hreset_vector = 0xFFFFFFFCUL;
2860 #endif
2861 }
2862
2863 static void init_excp_BookE (CPUPPCState *env)
2864 {
2865 #if !defined(CONFIG_USER_ONLY)
2866 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2882 env->ivor_mask = 0x0000FFF0UL;
2883 env->ivpr_mask = 0xFFFF0000UL;
2884 /* Hardware reset vector */
2885 env->hreset_vector = 0xFFFFFFFCUL;
2886 #endif
2887 }
2888
2889 static void init_excp_601 (CPUPPCState *env)
2890 {
2891 #if !defined(CONFIG_USER_ONLY)
2892 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2893 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2894 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2895 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2896 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2897 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2898 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2899 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2900 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2901 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2902 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2903 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2904 /* Hardware reset vector */
2905 env->hreset_vector = 0x00000100UL;
2906 #endif
2907 }
2908
2909 static void init_excp_602 (CPUPPCState *env)
2910 {
2911 #if !defined(CONFIG_USER_ONLY)
2912 /* XXX: exception prefix has a special behavior on 602 */
2913 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2914 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2915 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2916 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2917 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2918 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2919 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2920 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2921 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2922 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2923 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2924 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2925 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2926 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2927 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2928 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2929 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2930 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2931 /* Hardware reset vector */
2932 env->hreset_vector = 0x00000100UL;
2933 #endif
2934 }
2935
2936 static void init_excp_603 (CPUPPCState *env)
2937 {
2938 #if !defined(CONFIG_USER_ONLY)
2939 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2940 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2941 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2942 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2943 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2944 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2945 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2946 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2947 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2948 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2949 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2950 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2951 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2952 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2953 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2954 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2955 /* Hardware reset vector */
2956 env->hreset_vector = 0x00000100UL;
2957 #endif
2958 }
2959
2960 static void init_excp_604 (CPUPPCState *env)
2961 {
2962 #if !defined(CONFIG_USER_ONLY)
2963 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2964 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2965 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2966 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2967 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2968 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2969 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2970 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2971 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2972 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2973 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2974 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2975 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2976 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2977 /* Hardware reset vector */
2978 env->hreset_vector = 0x00000100UL;
2979 #endif
2980 }
2981
2982 static void init_excp_7x0 (CPUPPCState *env)
2983 {
2984 #if !defined(CONFIG_USER_ONLY)
2985 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2986 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2987 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2988 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2989 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2990 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2991 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2992 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2993 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2994 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2995 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2996 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2997 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2998 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2999 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3000 /* Hardware reset vector */
3001 env->hreset_vector = 0x00000100UL;
3002 #endif
3003 }
3004
3005 static void init_excp_750cl (CPUPPCState *env)
3006 {
3007 #if !defined(CONFIG_USER_ONLY)
3008 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3009 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3010 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3012 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3013 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3014 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3015 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3016 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3019 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3020 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3021 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3022 /* Hardware reset vector */
3023 env->hreset_vector = 0x00000100UL;
3024 #endif
3025 }
3026
3027 static void init_excp_750cx (CPUPPCState *env)
3028 {
3029 #if !defined(CONFIG_USER_ONLY)
3030 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3031 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3032 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3033 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3034 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3035 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3036 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3037 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3038 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3039 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3040 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3041 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3042 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3043 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3044 /* Hardware reset vector */
3045 env->hreset_vector = 0x00000100UL;
3046 #endif
3047 }
3048
3049 /* XXX: Check if this is correct */
3050 static void init_excp_7x5 (CPUPPCState *env)
3051 {
3052 #if !defined(CONFIG_USER_ONLY)
3053 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3054 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3055 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3056 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3057 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3058 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3059 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3060 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3061 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3062 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3063 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3064 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3065 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3066 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3067 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3068 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3069 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3070 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3071 /* Hardware reset vector */
3072 env->hreset_vector = 0x00000100UL;
3073 #endif
3074 }
3075
3076 static void init_excp_7400 (CPUPPCState *env)
3077 {
3078 #if !defined(CONFIG_USER_ONLY)
3079 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3080 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3081 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3082 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3083 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3084 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3085 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3086 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3087 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3088 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3089 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3090 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3091 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3092 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3093 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3094 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3095 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3096 /* Hardware reset vector */
3097 env->hreset_vector = 0x00000100UL;
3098 #endif
3099 }
3100
3101 static void init_excp_7450 (CPUPPCState *env)
3102 {
3103 #if !defined(CONFIG_USER_ONLY)
3104 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3105 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3106 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3107 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3108 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3109 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3110 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3111 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3112 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3113 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3114 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3115 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3116 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3117 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3118 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3119 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3120 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3121 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;