PPC: Add another 64 bits to instruction feature mask
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
25 #include "dis-asm.h"
26 #include "gdbstub.h"
27
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DUMP_SPR_ACCESSES
31 #if defined(CONFIG_USER_ONLY)
32 #define TODO_USER_ONLY 1
33 #endif
34
35 struct ppc_def_t {
36 const char *name;
37 uint32_t pvr;
38 uint32_t svr;
39 uint64_t insns_flags;
40 uint64_t insns_flags2;
41 uint64_t msr_mask;
42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
45 uint32_t flags;
46 int bfd_mach;
47 void (*init_proc)(CPUPPCState *env);
48 int (*check_pow)(CPUPPCState *env);
49 };
50
51 /* For user-mode emulation, we don't emulate any IRQ controller */
52 #if defined(CONFIG_USER_ONLY)
53 #define PPC_IRQ_INIT_FN(name) \
54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55 { \
56 }
57 #else
58 #define PPC_IRQ_INIT_FN(name) \
59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60 #endif
61
62 PPC_IRQ_INIT_FN(40x);
63 PPC_IRQ_INIT_FN(6xx);
64 PPC_IRQ_INIT_FN(970);
65 PPC_IRQ_INIT_FN(POWER7);
66 PPC_IRQ_INIT_FN(e500);
67
68 /* Generic callbacks:
69 * do nothing but store/retrieve spr value
70 */
71 static void spr_read_generic (void *opaque, int gprn, int sprn)
72 {
73 gen_load_spr(cpu_gpr[gprn], sprn);
74 #ifdef PPC_DUMP_SPR_ACCESSES
75 {
76 TCGv t0 = tcg_const_i32(sprn);
77 gen_helper_load_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 }
80 #endif
81 }
82
83 static void spr_write_generic (void *opaque, int sprn, int gprn)
84 {
85 gen_store_spr(sprn, cpu_gpr[gprn]);
86 #ifdef PPC_DUMP_SPR_ACCESSES
87 {
88 TCGv t0 = tcg_const_i32(sprn);
89 gen_helper_store_dump_spr(t0);
90 tcg_temp_free_i32(t0);
91 }
92 #endif
93 }
94
95 #if !defined(CONFIG_USER_ONLY)
96 static void spr_write_clear (void *opaque, int sprn, int gprn)
97 {
98 TCGv t0 = tcg_temp_new();
99 TCGv t1 = tcg_temp_new();
100 gen_load_spr(t0, sprn);
101 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
102 tcg_gen_and_tl(t0, t0, t1);
103 gen_store_spr(sprn, t0);
104 tcg_temp_free(t0);
105 tcg_temp_free(t1);
106 }
107 #endif
108
109 /* SPR common to all PowerPC */
110 /* XER */
111 static void spr_read_xer (void *opaque, int gprn, int sprn)
112 {
113 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
114 }
115
116 static void spr_write_xer (void *opaque, int sprn, int gprn)
117 {
118 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
119 }
120
121 /* LR */
122 static void spr_read_lr (void *opaque, int gprn, int sprn)
123 {
124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
125 }
126
127 static void spr_write_lr (void *opaque, int sprn, int gprn)
128 {
129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
130 }
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 if (use_icount) {
160 gen_io_start();
161 }
162 gen_helper_load_decr(cpu_gpr[gprn]);
163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
167 }
168
169 static void spr_write_decr (void *opaque, int sprn, int gprn)
170 {
171 if (use_icount) {
172 gen_io_start();
173 }
174 gen_helper_store_decr(cpu_gpr[gprn]);
175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC, except 601 */
183 /* Time base */
184 static void spr_read_tbl (void *opaque, int gprn, int sprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_load_tbl(cpu_gpr[gprn]);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195
196 static void spr_read_tbu (void *opaque, int gprn, int sprn)
197 {
198 if (use_icount) {
199 gen_io_start();
200 }
201 gen_helper_load_tbu(cpu_gpr[gprn]);
202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
206 }
207
208 __attribute__ (( unused ))
209 static void spr_read_atbl (void *opaque, int gprn, int sprn)
210 {
211 gen_helper_load_atbl(cpu_gpr[gprn]);
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbu (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbu(cpu_gpr[gprn]);
218 }
219
220 #if !defined(CONFIG_USER_ONLY)
221 static void spr_write_tbl (void *opaque, int sprn, int gprn)
222 {
223 if (use_icount) {
224 gen_io_start();
225 }
226 gen_helper_store_tbl(cpu_gpr[gprn]);
227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
231 }
232
233 static void spr_write_tbu (void *opaque, int sprn, int gprn)
234 {
235 if (use_icount) {
236 gen_io_start();
237 }
238 gen_helper_store_tbu(cpu_gpr[gprn]);
239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
243 }
244
245 __attribute__ (( unused ))
246 static void spr_write_atbl (void *opaque, int sprn, int gprn)
247 {
248 gen_helper_store_atbl(cpu_gpr[gprn]);
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbu (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbu(cpu_gpr[gprn]);
255 }
256
257 #if defined(TARGET_PPC64)
258 __attribute__ (( unused ))
259 static void spr_read_purr (void *opaque, int gprn, int sprn)
260 {
261 gen_helper_load_purr(cpu_gpr[gprn]);
262 }
263 #endif
264 #endif
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* IBAT0U...IBAT0U */
268 /* IBAT0L...IBAT7L */
269 static void spr_read_ibat (void *opaque, int gprn, int sprn)
270 {
271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
272 }
273
274 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
275 {
276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
277 }
278
279 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
280 {
281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
284 }
285
286 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
287 {
288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
291 }
292
293 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 /* DBAT0U...DBAT7U */
308 /* DBAT0L...DBAT7L */
309 static void spr_read_dbat (void *opaque, int gprn, int sprn)
310 {
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
312 }
313
314 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
315 {
316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
317 }
318
319 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 /* SDR1 */
348 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
349 {
350 gen_helper_store_sdr1(cpu_gpr[gprn]);
351 }
352
353 /* 64 bits PowerPC specific SPRs */
354 /* ASR */
355 #if defined(TARGET_PPC64)
356 static void spr_read_hior (void *opaque, int gprn, int sprn)
357 {
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
359 }
360
361 static void spr_write_hior (void *opaque, int sprn, int gprn)
362 {
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
366 tcg_temp_free(t0);
367 }
368
369 static void spr_read_asr (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
372 }
373
374 static void spr_write_asr (void *opaque, int sprn, int gprn)
375 {
376 gen_helper_store_asr(cpu_gpr[gprn]);
377 }
378 #endif
379 #endif
380
381 /* PowerPC 601 specific registers */
382 /* RTC */
383 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
384 {
385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
386 }
387
388 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
391 }
392
393 #if !defined(CONFIG_USER_ONLY)
394 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
397 }
398
399 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
402 }
403
404 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
405 {
406 DisasContext *ctx = opaque;
407
408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
409 /* Must stop the translation as endianness may have changed */
410 gen_stop_exception(ctx);
411 }
412 #endif
413
414 /* Unified bats */
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
417 {
418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
419 }
420
421 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
422 {
423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
426 }
427
428 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
429 {
430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
433 }
434 #endif
435
436 /* PowerPC 40x specific registers */
437 #if !defined(CONFIG_USER_ONLY)
438 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
439 {
440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
441 }
442
443 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
444 {
445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
446 }
447
448 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
449 {
450 DisasContext *ctx = opaque;
451
452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
453 /* We must stop translation as we may have rebooted */
454 gen_stop_exception(ctx);
455 }
456
457 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
460 }
461
462 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
470 }
471 #endif
472
473 /* PowerPC 403 specific registers */
474 /* PBL1 / PBU1 / PBL2 / PBU2 */
475 #if !defined(CONFIG_USER_ONLY)
476 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
477 {
478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
479 }
480
481 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
482 {
483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
486 }
487
488 static void spr_write_pir (void *opaque, int sprn, int gprn)
489 {
490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
494 }
495 #endif
496
497 /* SPE specific registers */
498 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499 {
500 TCGv_i32 t0 = tcg_temp_new_i32();
501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507 {
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
511 tcg_temp_free_i32(t0);
512 }
513
514 #if !defined(CONFIG_USER_ONLY)
515 /* Callback used to write the exception vector base */
516 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
522 gen_store_spr(sprn, t0);
523 tcg_temp_free(t0);
524 }
525
526 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
527 {
528 DisasContext *ctx = opaque;
529
530 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
544 } else {
545 printf("Trying to write an unknown exception vector %d %03x\n",
546 sprn, sprn);
547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
548 }
549 }
550 #endif
551
552 static inline void vscr_init (CPUPPCState *env, uint32_t val)
553 {
554 env->vscr = val;
555 /* Altivec always uses round-to-nearest */
556 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
557 set_flush_to_zero(vscr_nj, &env->vec_status);
558 }
559
560 #if defined(CONFIG_USER_ONLY)
561 #define spr_register(env, num, name, uea_read, uea_write, \
562 oea_read, oea_write, initial_value) \
563 do { \
564 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
565 } while (0)
566 static inline void _spr_register (CPUPPCState *env, int num,
567 const char *name,
568 void (*uea_read)(void *opaque, int gprn, int sprn),
569 void (*uea_write)(void *opaque, int sprn, int gprn),
570 target_ulong initial_value)
571 #else
572 static inline void spr_register (CPUPPCState *env, int num,
573 const char *name,
574 void (*uea_read)(void *opaque, int gprn, int sprn),
575 void (*uea_write)(void *opaque, int sprn, int gprn),
576 void (*oea_read)(void *opaque, int gprn, int sprn),
577 void (*oea_write)(void *opaque, int sprn, int gprn),
578 target_ulong initial_value)
579 #endif
580 {
581 ppc_spr_t *spr;
582
583 spr = &env->spr_cb[num];
584 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
585 #if !defined(CONFIG_USER_ONLY)
586 spr->oea_read != NULL || spr->oea_write != NULL ||
587 #endif
588 spr->uea_read != NULL || spr->uea_write != NULL) {
589 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
590 exit(1);
591 }
592 #if defined(PPC_DEBUG_SPR)
593 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
594 name, initial_value);
595 #endif
596 spr->name = name;
597 spr->uea_read = uea_read;
598 spr->uea_write = uea_write;
599 #if !defined(CONFIG_USER_ONLY)
600 spr->oea_read = oea_read;
601 spr->oea_write = oea_write;
602 #endif
603 env->spr[num] = initial_value;
604 }
605
606 /* Generic PowerPC SPRs */
607 static void gen_spr_generic (CPUPPCState *env)
608 {
609 /* Integer processing */
610 spr_register(env, SPR_XER, "XER",
611 &spr_read_xer, &spr_write_xer,
612 &spr_read_xer, &spr_write_xer,
613 0x00000000);
614 /* Branch contol */
615 spr_register(env, SPR_LR, "LR",
616 &spr_read_lr, &spr_write_lr,
617 &spr_read_lr, &spr_write_lr,
618 0x00000000);
619 spr_register(env, SPR_CTR, "CTR",
620 &spr_read_ctr, &spr_write_ctr,
621 &spr_read_ctr, &spr_write_ctr,
622 0x00000000);
623 /* Interrupt processing */
624 spr_register(env, SPR_SRR0, "SRR0",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628 spr_register(env, SPR_SRR1, "SRR1",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632 /* Processor control */
633 spr_register(env, SPR_SPRG0, "SPRG0",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_generic,
636 0x00000000);
637 spr_register(env, SPR_SPRG1, "SPRG1",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SPRG2, "SPRG2",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 spr_register(env, SPR_SPRG3, "SPRG3",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 }
650
651 /* SPR common to all non-embedded PowerPC, including 601 */
652 static void gen_spr_ne_601 (CPUPPCState *env)
653 {
654 /* Exception processing */
655 spr_register(env, SPR_DSISR, "DSISR",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_DAR, "DAR",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Timer */
664 spr_register(env, SPR_DECR, "DECR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_decr, &spr_write_decr,
667 0x00000000);
668 /* Memory management */
669 spr_register(env, SPR_SDR1, "SDR1",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, &spr_write_sdr1,
672 0x00000000);
673 }
674
675 /* BATs 0-3 */
676 static void gen_low_BATs (CPUPPCState *env)
677 {
678 #if !defined(CONFIG_USER_ONLY)
679 spr_register(env, SPR_IBAT0U, "IBAT0U",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat, &spr_write_ibatu,
682 0x00000000);
683 spr_register(env, SPR_IBAT0L, "IBAT0L",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat, &spr_write_ibatl,
686 0x00000000);
687 spr_register(env, SPR_IBAT1U, "IBAT1U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat, &spr_write_ibatu,
690 0x00000000);
691 spr_register(env, SPR_IBAT1L, "IBAT1L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat, &spr_write_ibatl,
694 0x00000000);
695 spr_register(env, SPR_IBAT2U, "IBAT2U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat, &spr_write_ibatu,
698 0x00000000);
699 spr_register(env, SPR_IBAT2L, "IBAT2L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatl,
702 0x00000000);
703 spr_register(env, SPR_IBAT3U, "IBAT3U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatu,
706 0x00000000);
707 spr_register(env, SPR_IBAT3L, "IBAT3L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatl,
710 0x00000000);
711 spr_register(env, SPR_DBAT0U, "DBAT0U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat, &spr_write_dbatu,
714 0x00000000);
715 spr_register(env, SPR_DBAT0L, "DBAT0L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat, &spr_write_dbatl,
718 0x00000000);
719 spr_register(env, SPR_DBAT1U, "DBAT1U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat, &spr_write_dbatu,
722 0x00000000);
723 spr_register(env, SPR_DBAT1L, "DBAT1L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat, &spr_write_dbatl,
726 0x00000000);
727 spr_register(env, SPR_DBAT2U, "DBAT2U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat, &spr_write_dbatu,
730 0x00000000);
731 spr_register(env, SPR_DBAT2L, "DBAT2L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatl,
734 0x00000000);
735 spr_register(env, SPR_DBAT3U, "DBAT3U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatu,
738 0x00000000);
739 spr_register(env, SPR_DBAT3L, "DBAT3L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatl,
742 0x00000000);
743 env->nb_BATs += 4;
744 #endif
745 }
746
747 /* BATs 4-7 */
748 static void gen_high_BATs (CPUPPCState *env)
749 {
750 #if !defined(CONFIG_USER_ONLY)
751 spr_register(env, SPR_IBAT4U, "IBAT4U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat_h, &spr_write_ibatu_h,
754 0x00000000);
755 spr_register(env, SPR_IBAT4L, "IBAT4L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat_h, &spr_write_ibatl_h,
758 0x00000000);
759 spr_register(env, SPR_IBAT5U, "IBAT5U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat_h, &spr_write_ibatu_h,
762 0x00000000);
763 spr_register(env, SPR_IBAT5L, "IBAT5L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat_h, &spr_write_ibatl_h,
766 0x00000000);
767 spr_register(env, SPR_IBAT6U, "IBAT6U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat_h, &spr_write_ibatu_h,
770 0x00000000);
771 spr_register(env, SPR_IBAT6L, "IBAT6L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatl_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT7U, "IBAT7U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatu_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT7L, "IBAT7L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatl_h,
782 0x00000000);
783 spr_register(env, SPR_DBAT4U, "DBAT4U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat_h, &spr_write_dbatu_h,
786 0x00000000);
787 spr_register(env, SPR_DBAT4L, "DBAT4L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat_h, &spr_write_dbatl_h,
790 0x00000000);
791 spr_register(env, SPR_DBAT5U, "DBAT5U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat_h, &spr_write_dbatu_h,
794 0x00000000);
795 spr_register(env, SPR_DBAT5L, "DBAT5L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat_h, &spr_write_dbatl_h,
798 0x00000000);
799 spr_register(env, SPR_DBAT6U, "DBAT6U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat_h, &spr_write_dbatu_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT6L, "DBAT6L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatl_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT7U, "DBAT7U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatu_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT7L, "DBAT7L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatl_h,
814 0x00000000);
815 env->nb_BATs += 4;
816 #endif
817 }
818
819 /* Generic PowerPC time base */
820 static void gen_tbl (CPUPPCState *env)
821 {
822 spr_register(env, SPR_VTBL, "TBL",
823 &spr_read_tbl, SPR_NOACCESS,
824 &spr_read_tbl, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_TBL, "TBL",
827 &spr_read_tbl, SPR_NOACCESS,
828 &spr_read_tbl, &spr_write_tbl,
829 0x00000000);
830 spr_register(env, SPR_VTBU, "TBU",
831 &spr_read_tbu, SPR_NOACCESS,
832 &spr_read_tbu, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_TBU, "TBU",
835 &spr_read_tbu, SPR_NOACCESS,
836 &spr_read_tbu, &spr_write_tbu,
837 0x00000000);
838 }
839
840 /* Softare table search registers */
841 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
842 {
843 #if !defined(CONFIG_USER_ONLY)
844 env->nb_tlb = nb_tlbs;
845 env->nb_ways = nb_ways;
846 env->id_tlbs = 1;
847 spr_register(env, SPR_DMISS, "DMISS",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, SPR_NOACCESS,
850 0x00000000);
851 spr_register(env, SPR_DCMP, "DCMP",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_generic, SPR_NOACCESS,
854 0x00000000);
855 spr_register(env, SPR_HASH1, "HASH1",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, SPR_NOACCESS,
858 0x00000000);
859 spr_register(env, SPR_HASH2, "HASH2",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic, SPR_NOACCESS,
862 0x00000000);
863 spr_register(env, SPR_IMISS, "IMISS",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_ICMP, "ICMP",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, SPR_NOACCESS,
870 0x00000000);
871 spr_register(env, SPR_RPA, "RPA",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
874 0x00000000);
875 #endif
876 }
877
878 /* SPR common to MPC755 and G2 */
879 static void gen_spr_G2_755 (CPUPPCState *env)
880 {
881 /* SGPRs */
882 spr_register(env, SPR_SPRG4, "SPRG4",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 spr_register(env, SPR_SPRG5, "SPRG5",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, &spr_write_generic,
889 0x00000000);
890 spr_register(env, SPR_SPRG6, "SPRG6",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
894 spr_register(env, SPR_SPRG7, "SPRG7",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 }
899
900 /* SPR common to all 7xx PowerPC implementations */
901 static void gen_spr_7xx (CPUPPCState *env)
902 {
903 /* Breakpoints */
904 /* XXX : not implemented */
905 spr_register(env, SPR_DABR, "DABR",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 /* XXX : not implemented */
910 spr_register(env, SPR_IABR, "IABR",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* Cache management */
915 /* XXX : not implemented */
916 spr_register(env, SPR_ICTC, "ICTC",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
920 /* Performance monitors */
921 /* XXX : not implemented */
922 spr_register(env, SPR_MMCR0, "MMCR0",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 /* XXX : not implemented */
927 spr_register(env, SPR_MMCR1, "MMCR1",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
932 spr_register(env, SPR_PMC1, "PMC1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* XXX : not implemented */
937 spr_register(env, SPR_PMC2, "PMC2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_PMC3, "PMC3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* XXX : not implemented */
947 spr_register(env, SPR_PMC4, "PMC4",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951 /* XXX : not implemented */
952 spr_register(env, SPR_SIAR, "SIAR",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, SPR_NOACCESS,
955 0x00000000);
956 /* XXX : not implemented */
957 spr_register(env, SPR_UMMCR0, "UMMCR0",
958 &spr_read_ureg, SPR_NOACCESS,
959 &spr_read_ureg, SPR_NOACCESS,
960 0x00000000);
961 /* XXX : not implemented */
962 spr_register(env, SPR_UMMCR1, "UMMCR1",
963 &spr_read_ureg, SPR_NOACCESS,
964 &spr_read_ureg, SPR_NOACCESS,
965 0x00000000);
966 /* XXX : not implemented */
967 spr_register(env, SPR_UPMC1, "UPMC1",
968 &spr_read_ureg, SPR_NOACCESS,
969 &spr_read_ureg, SPR_NOACCESS,
970 0x00000000);
971 /* XXX : not implemented */
972 spr_register(env, SPR_UPMC2, "UPMC2",
973 &spr_read_ureg, SPR_NOACCESS,
974 &spr_read_ureg, SPR_NOACCESS,
975 0x00000000);
976 /* XXX : not implemented */
977 spr_register(env, SPR_UPMC3, "UPMC3",
978 &spr_read_ureg, SPR_NOACCESS,
979 &spr_read_ureg, SPR_NOACCESS,
980 0x00000000);
981 /* XXX : not implemented */
982 spr_register(env, SPR_UPMC4, "UPMC4",
983 &spr_read_ureg, SPR_NOACCESS,
984 &spr_read_ureg, SPR_NOACCESS,
985 0x00000000);
986 /* XXX : not implemented */
987 spr_register(env, SPR_USIAR, "USIAR",
988 &spr_read_ureg, SPR_NOACCESS,
989 &spr_read_ureg, SPR_NOACCESS,
990 0x00000000);
991 /* External access control */
992 /* XXX : not implemented */
993 spr_register(env, SPR_EAR, "EAR",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
997 }
998
999 static void gen_spr_thrm (CPUPPCState *env)
1000 {
1001 /* Thermal management */
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_THRM1, "THRM1",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 /* XXX : not implemented */
1008 spr_register(env, SPR_THRM2, "THRM2",
1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_THRM3, "THRM3",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
1017 }
1018
1019 /* SPR specific to PowerPC 604 implementation */
1020 static void gen_spr_604 (CPUPPCState *env)
1021 {
1022 /* Processor identification */
1023 spr_register(env, SPR_PIR, "PIR",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_pir,
1026 0x00000000);
1027 /* Breakpoints */
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_IABR, "IABR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_DABR, "DABR",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* Performance counters */
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_MMCR0, "MMCR0",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_PMC1, "PMC1",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_PMC2, "PMC2",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_SIAR, "SIAR",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, SPR_NOACCESS,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_SDA, "SDA",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, SPR_NOACCESS,
1063 0x00000000);
1064 /* External access control */
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_EAR, "EAR",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070 }
1071
1072 /* SPR specific to PowerPC 603 implementation */
1073 static void gen_spr_603 (CPUPPCState *env)
1074 {
1075 /* External access control */
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_EAR, "EAR",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 }
1082
1083 /* SPR specific to PowerPC G2 implementation */
1084 static void gen_spr_G2 (CPUPPCState *env)
1085 {
1086 /* Memory base address */
1087 /* MBAR */
1088 /* XXX : not implemented */
1089 spr_register(env, SPR_MBAR, "MBAR",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093 /* Exception processing */
1094 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_generic,
1097 0x00000000);
1098 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* Breakpoints */
1103 /* XXX : not implemented */
1104 spr_register(env, SPR_DABR, "DABR",
1105 SPR_NOACCESS, SPR_NOACCESS,
1106 &spr_read_generic, &spr_write_generic,
1107 0x00000000);
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_DABR2, "DABR2",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register(env, SPR_IABR, "IABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 /* XXX : not implemented */
1119 spr_register(env, SPR_IABR2, "IABR2",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_generic, &spr_write_generic,
1122 0x00000000);
1123 /* XXX : not implemented */
1124 spr_register(env, SPR_IBCR, "IBCR",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 /* XXX : not implemented */
1129 spr_register(env, SPR_DBCR, "DBCR",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, &spr_write_generic,
1132 0x00000000);
1133 }
1134
1135 /* SPR specific to PowerPC 602 implementation */
1136 static void gen_spr_602 (CPUPPCState *env)
1137 {
1138 /* ESA registers */
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_SER, "SER",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1143 0x00000000);
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_SEBR, "SEBR",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_generic,
1148 0x00000000);
1149 /* XXX : not implemented */
1150 spr_register(env, SPR_ESASRR, "ESASRR",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_generic,
1153 0x00000000);
1154 /* Floating point status */
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_SP, "SP",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_LT, "LT",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 /* Watchdog timer */
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_TCR, "TCR",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* Interrupt base */
1172 spr_register(env, SPR_IBR, "IBR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_IABR, "IABR",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 }
1182
1183 /* SPR specific to PowerPC 601 implementation */
1184 static void gen_spr_601 (CPUPPCState *env)
1185 {
1186 /* Multiplication/division register */
1187 /* MQ */
1188 spr_register(env, SPR_MQ, "MQ",
1189 &spr_read_generic, &spr_write_generic,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* RTC registers */
1193 spr_register(env, SPR_601_RTCU, "RTCU",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 SPR_NOACCESS, &spr_write_601_rtcu,
1196 0x00000000);
1197 spr_register(env, SPR_601_VRTCU, "RTCU",
1198 &spr_read_601_rtcu, SPR_NOACCESS,
1199 &spr_read_601_rtcu, SPR_NOACCESS,
1200 0x00000000);
1201 spr_register(env, SPR_601_RTCL, "RTCL",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 SPR_NOACCESS, &spr_write_601_rtcl,
1204 0x00000000);
1205 spr_register(env, SPR_601_VRTCL, "RTCL",
1206 &spr_read_601_rtcl, SPR_NOACCESS,
1207 &spr_read_601_rtcl, SPR_NOACCESS,
1208 0x00000000);
1209 /* Timer */
1210 #if 0 /* ? */
1211 spr_register(env, SPR_601_UDECR, "UDECR",
1212 &spr_read_decr, SPR_NOACCESS,
1213 &spr_read_decr, SPR_NOACCESS,
1214 0x00000000);
1215 #endif
1216 /* External access control */
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_EAR, "EAR",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* Memory management */
1223 #if !defined(CONFIG_USER_ONLY)
1224 spr_register(env, SPR_IBAT0U, "IBAT0U",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_601_ubat, &spr_write_601_ubatu,
1227 0x00000000);
1228 spr_register(env, SPR_IBAT0L, "IBAT0L",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_601_ubat, &spr_write_601_ubatl,
1231 0x00000000);
1232 spr_register(env, SPR_IBAT1U, "IBAT1U",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_601_ubat, &spr_write_601_ubatu,
1235 0x00000000);
1236 spr_register(env, SPR_IBAT1L, "IBAT1L",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_601_ubat, &spr_write_601_ubatl,
1239 0x00000000);
1240 spr_register(env, SPR_IBAT2U, "IBAT2U",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_601_ubat, &spr_write_601_ubatu,
1243 0x00000000);
1244 spr_register(env, SPR_IBAT2L, "IBAT2L",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_601_ubat, &spr_write_601_ubatl,
1247 0x00000000);
1248 spr_register(env, SPR_IBAT3U, "IBAT3U",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_601_ubat, &spr_write_601_ubatu,
1251 0x00000000);
1252 spr_register(env, SPR_IBAT3L, "IBAT3L",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_601_ubat, &spr_write_601_ubatl,
1255 0x00000000);
1256 env->nb_BATs = 4;
1257 #endif
1258 }
1259
1260 static void gen_spr_74xx (CPUPPCState *env)
1261 {
1262 /* Processor identification */
1263 spr_register(env, SPR_PIR, "PIR",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_pir,
1266 0x00000000);
1267 /* XXX : not implemented */
1268 spr_register(env, SPR_MMCR2, "MMCR2",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 0x00000000);
1272 /* XXX : not implemented */
1273 spr_register(env, SPR_UMMCR2, "UMMCR2",
1274 &spr_read_ureg, SPR_NOACCESS,
1275 &spr_read_ureg, SPR_NOACCESS,
1276 0x00000000);
1277 /* XXX: not implemented */
1278 spr_register(env, SPR_BAMR, "BAMR",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
1282 /* XXX : not implemented */
1283 spr_register(env, SPR_MSSCR0, "MSSCR0",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287 /* Hardware implementation registers */
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_HID0, "HID0",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_HID1, "HID1",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* Altivec */
1299 spr_register(env, SPR_VRSAVE, "VRSAVE",
1300 &spr_read_generic, &spr_write_generic,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_L2CR, "L2CR",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* Not strictly an SPR */
1309 vscr_init(env, 0x00010000);
1310 }
1311
1312 static void gen_l3_ctrl (CPUPPCState *env)
1313 {
1314 /* L3CR */
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_L3CR, "L3CR",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* L3ITCR0 */
1321 /* XXX : not implemented */
1322 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
1326 /* L3PM */
1327 /* XXX : not implemented */
1328 spr_register(env, SPR_L3PM, "L3PM",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332 }
1333
1334 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1335 {
1336 #if !defined(CONFIG_USER_ONLY)
1337 env->nb_tlb = nb_tlbs;
1338 env->nb_ways = nb_ways;
1339 env->id_tlbs = 1;
1340 /* XXX : not implemented */
1341 spr_register(env, SPR_PTEHI, "PTEHI",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_PTELO, "PTELO",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_TLBMISS, "TLBMISS",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 #endif
1356 }
1357
1358 static void gen_spr_usprgh (CPUPPCState *env)
1359 {
1360 spr_register(env, SPR_USPRG4, "USPRG4",
1361 &spr_read_ureg, SPR_NOACCESS,
1362 &spr_read_ureg, SPR_NOACCESS,
1363 0x00000000);
1364 spr_register(env, SPR_USPRG5, "USPRG5",
1365 &spr_read_ureg, SPR_NOACCESS,
1366 &spr_read_ureg, SPR_NOACCESS,
1367 0x00000000);
1368 spr_register(env, SPR_USPRG6, "USPRG6",
1369 &spr_read_ureg, SPR_NOACCESS,
1370 &spr_read_ureg, SPR_NOACCESS,
1371 0x00000000);
1372 spr_register(env, SPR_USPRG7, "USPRG7",
1373 &spr_read_ureg, SPR_NOACCESS,
1374 &spr_read_ureg, SPR_NOACCESS,
1375 0x00000000);
1376 }
1377
1378 /* PowerPC BookE SPR */
1379 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1380 {
1381 const char *ivor_names[64] = {
1382 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1383 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1384 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1385 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1386 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1387 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1388 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1389 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1390 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1391 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1392 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1393 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1394 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1395 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1396 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1397 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1398 };
1399 #define SPR_BOOKE_IVORxx (-1)
1400 int ivor_sprn[64] = {
1401 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1402 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1403 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1404 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1405 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1406 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1407 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1408 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1409 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1410 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1411 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1412 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1413 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1414 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1415 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1416 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1417 };
1418 int i;
1419
1420 /* Interrupt processing */
1421 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_generic,
1428 0x00000000);
1429 /* Debug */
1430 /* XXX : not implemented */
1431 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435 /* XXX : not implemented */
1436 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440 /* XXX : not implemented */
1441 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_generic,
1444 0x00000000);
1445 /* XXX : not implemented */
1446 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_generic,
1449 0x00000000);
1450 /* XXX : not implemented */
1451 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_generic, &spr_write_generic,
1454 0x00000000);
1455 /* XXX : not implemented */
1456 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460 /* XXX : not implemented */
1461 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465 /* XXX : not implemented */
1466 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_clear,
1469 0x00000000);
1470 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 spr_register(env, SPR_BOOKE_ESR, "ESR",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_excp_prefix,
1481 0x00000000);
1482 /* Exception vectors */
1483 for (i = 0; i < 64; i++) {
1484 if (ivor_mask & (1ULL << i)) {
1485 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1486 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1487 exit(1);
1488 }
1489 spr_register(env, ivor_sprn[i], ivor_names[i],
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_excp_vector,
1492 0x00000000);
1493 }
1494 }
1495 spr_register(env, SPR_BOOKE_PID, "PID",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 spr_register(env, SPR_BOOKE_TCR, "TCR",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_booke_tcr,
1502 0x00000000);
1503 spr_register(env, SPR_BOOKE_TSR, "TSR",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_booke_tsr,
1506 0x00000000);
1507 /* Timer */
1508 spr_register(env, SPR_DECR, "DECR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_decr, &spr_write_decr,
1511 0x00000000);
1512 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1513 SPR_NOACCESS, SPR_NOACCESS,
1514 SPR_NOACCESS, &spr_write_generic,
1515 0x00000000);
1516 /* SPRGs */
1517 spr_register(env, SPR_USPRG0, "USPRG0",
1518 &spr_read_generic, &spr_write_generic,
1519 &spr_read_generic, &spr_write_generic,
1520 0x00000000);
1521 spr_register(env, SPR_SPRG4, "SPRG4",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525 spr_register(env, SPR_SPRG5, "SPRG5",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, &spr_write_generic,
1528 0x00000000);
1529 spr_register(env, SPR_SPRG6, "SPRG6",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
1533 spr_register(env, SPR_SPRG7, "SPRG7",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537 }
1538
1539 /* FSL storage control registers */
1540 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1541 {
1542 #if !defined(CONFIG_USER_ONLY)
1543 const char *mas_names[8] = {
1544 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1545 };
1546 int mas_sprn[8] = {
1547 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1548 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1549 };
1550 int i;
1551
1552 /* TLB assist registers */
1553 /* XXX : not implemented */
1554 for (i = 0; i < 8; i++) {
1555 if (mas_mask & (1 << i)) {
1556 spr_register(env, mas_sprn[i], mas_names[i],
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 }
1561 }
1562 if (env->nb_pids > 1) {
1563 /* XXX : not implemented */
1564 spr_register(env, SPR_BOOKE_PID1, "PID1",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 }
1569 if (env->nb_pids > 2) {
1570 /* XXX : not implemented */
1571 spr_register(env, SPR_BOOKE_PID2, "PID2",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 }
1576 /* XXX : not implemented */
1577 spr_register(env, SPR_MMUCFG, "MMUCFG",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, SPR_NOACCESS,
1580 0x00000000); /* TOFIX */
1581 /* XXX : not implemented */
1582 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000); /* TOFIX */
1586 switch (env->nb_ways) {
1587 case 4:
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, SPR_NOACCESS,
1592 0x00000000); /* TOFIX */
1593 /* Fallthru */
1594 case 3:
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, SPR_NOACCESS,
1599 0x00000000); /* TOFIX */
1600 /* Fallthru */
1601 case 2:
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, SPR_NOACCESS,
1606 0x00000000); /* TOFIX */
1607 /* Fallthru */
1608 case 1:
1609 /* XXX : not implemented */
1610 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, SPR_NOACCESS,
1613 0x00000000); /* TOFIX */
1614 /* Fallthru */
1615 case 0:
1616 default:
1617 break;
1618 }
1619 #endif
1620 }
1621
1622 /* SPR specific to PowerPC 440 implementation */
1623 static void gen_spr_440 (CPUPPCState *env)
1624 {
1625 /* Cache control */
1626 /* XXX : not implemented */
1627 spr_register(env, SPR_440_DNV0, "DNV0",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 /* XXX : not implemented */
1632 spr_register(env, SPR_440_DNV1, "DNV1",
1633 SPR_NOACCESS, SPR_NOACCESS,
1634 &spr_read_generic, &spr_write_generic,
1635 0x00000000);
1636 /* XXX : not implemented */
1637 spr_register(env, SPR_440_DNV2, "DNV2",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, &spr_write_generic,
1640 0x00000000);
1641 /* XXX : not implemented */
1642 spr_register(env, SPR_440_DNV3, "DNV3",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 /* XXX : not implemented */
1647 spr_register(env, SPR_440_DTV0, "DTV0",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 /* XXX : not implemented */
1652 spr_register(env, SPR_440_DTV1, "DTV1",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 /* XXX : not implemented */
1657 spr_register(env, SPR_440_DTV2, "DTV2",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* XXX : not implemented */
1662 spr_register(env, SPR_440_DTV3, "DTV3",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_generic,
1665 0x00000000);
1666 /* XXX : not implemented */
1667 spr_register(env, SPR_440_DVLIM, "DVLIM",
1668 SPR_NOACCESS, SPR_NOACCESS,
1669 &spr_read_generic, &spr_write_generic,
1670 0x00000000);
1671 /* XXX : not implemented */
1672 spr_register(env, SPR_440_INV0, "INV0",
1673 SPR_NOACCESS, SPR_NOACCESS,
1674 &spr_read_generic, &spr_write_generic,
1675 0x00000000);
1676 /* XXX : not implemented */
1677 spr_register(env, SPR_440_INV1, "INV1",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_generic,
1680 0x00000000);
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_440_INV2, "INV2",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1685 0x00000000);
1686 /* XXX : not implemented */
1687 spr_register(env, SPR_440_INV3, "INV3",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_generic,
1690 0x00000000);
1691 /* XXX : not implemented */
1692 spr_register(env, SPR_440_ITV0, "ITV0",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696 /* XXX : not implemented */
1697 spr_register(env, SPR_440_ITV1, "ITV1",
1698 SPR_NOACCESS, SPR_NOACCESS,
1699 &spr_read_generic, &spr_write_generic,
1700 0x00000000);
1701 /* XXX : not implemented */
1702 spr_register(env, SPR_440_ITV2, "ITV2",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 /* XXX : not implemented */
1707 spr_register(env, SPR_440_ITV3, "ITV3",
1708 SPR_NOACCESS, SPR_NOACCESS,
1709 &spr_read_generic, &spr_write_generic,
1710 0x00000000);
1711 /* XXX : not implemented */
1712 spr_register(env, SPR_440_IVLIM, "IVLIM",
1713 SPR_NOACCESS, SPR_NOACCESS,
1714 &spr_read_generic, &spr_write_generic,
1715 0x00000000);
1716 /* Cache debug */
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, SPR_NOACCESS,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, SPR_NOACCESS,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, SPR_NOACCESS,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, SPR_NOACCESS,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, SPR_NOACCESS,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_DBDR, "DBDR",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Processor control */
1748 spr_register(env, SPR_4xx_CCR0, "CCR0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, SPR_NOACCESS,
1755 0x00000000);
1756 /* Storage control */
1757 spr_register(env, SPR_440_MMUCR, "MMUCR",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 }
1762
1763 /* SPR shared between PowerPC 40x implementations */
1764 static void gen_spr_40x (CPUPPCState *env)
1765 {
1766 /* Cache */
1767 /* not emulated, as Qemu do not emulate caches */
1768 spr_register(env, SPR_40x_DCCR, "DCCR",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* not emulated, as Qemu do not emulate caches */
1773 spr_register(env, SPR_40x_ICCR, "ICCR",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* not emulated, as Qemu do not emulate caches */
1778 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, SPR_NOACCESS,
1781 0x00000000);
1782 /* Exception */
1783 spr_register(env, SPR_40x_DEAR, "DEAR",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 spr_register(env, SPR_40x_ESR, "ESR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 spr_register(env, SPR_40x_EVPR, "EVPR",
1792 SPR_NOACCESS, SPR_NOACCESS,
1793 &spr_read_generic, &spr_write_excp_prefix,
1794 0x00000000);
1795 spr_register(env, SPR_40x_SRR2, "SRR2",
1796 &spr_read_generic, &spr_write_generic,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 spr_register(env, SPR_40x_SRR3, "SRR3",
1800 &spr_read_generic, &spr_write_generic,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* Timers */
1804 spr_register(env, SPR_40x_PIT, "PIT",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_40x_pit, &spr_write_40x_pit,
1807 0x00000000);
1808 spr_register(env, SPR_40x_TCR, "TCR",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_booke_tcr,
1811 0x00000000);
1812 spr_register(env, SPR_40x_TSR, "TSR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_booke_tsr,
1815 0x00000000);
1816 }
1817
1818 /* SPR specific to PowerPC 405 implementation */
1819 static void gen_spr_405 (CPUPPCState *env)
1820 {
1821 /* MMU */
1822 spr_register(env, SPR_40x_PID, "PID",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 spr_register(env, SPR_4xx_CCR0, "CCR0",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00700000);
1830 /* Debug interface */
1831 /* XXX : not implemented */
1832 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_40x_dbcr0,
1835 0x00000000);
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_405_DBCR1, "DBCR1",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_40x_DBSR, "DBSR",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_clear,
1845 /* Last reset was system reset */
1846 0x00000300);
1847 /* XXX : not implemented */
1848 spr_register(env, SPR_40x_DAC1, "DAC1",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
1852 spr_register(env, SPR_40x_DAC2, "DAC2",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 /* XXX : not implemented */
1857 spr_register(env, SPR_405_DVC1, "DVC1",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00000000);
1861 /* XXX : not implemented */
1862 spr_register(env, SPR_405_DVC2, "DVC2",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 /* XXX : not implemented */
1867 spr_register(env, SPR_40x_IAC1, "IAC1",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, &spr_write_generic,
1870 0x00000000);
1871 spr_register(env, SPR_40x_IAC2, "IAC2",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875 /* XXX : not implemented */
1876 spr_register(env, SPR_405_IAC3, "IAC3",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_405_IAC4, "IAC4",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* Storage control */
1886 /* XXX: TODO: not implemented */
1887 spr_register(env, SPR_405_SLER, "SLER",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_40x_sler,
1890 0x00000000);
1891 spr_register(env, SPR_40x_ZPR, "ZPR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* XXX : not implemented */
1896 spr_register(env, SPR_405_SU0R, "SU0R",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 /* SPRG */
1901 spr_register(env, SPR_USPRG0, "USPRG0",
1902 &spr_read_ureg, SPR_NOACCESS,
1903 &spr_read_ureg, SPR_NOACCESS,
1904 0x00000000);
1905 spr_register(env, SPR_SPRG4, "SPRG4",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_SPRG5, "SPRG5",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 spr_read_generic, &spr_write_generic,
1912 0x00000000);
1913 spr_register(env, SPR_SPRG6, "SPRG6",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_SPRG7, "SPRG7",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 gen_spr_usprgh(env);
1922 }
1923
1924 /* SPR shared between PowerPC 401 & 403 implementations */
1925 static void gen_spr_401_403 (CPUPPCState *env)
1926 {
1927 /* Time base */
1928 spr_register(env, SPR_403_VTBL, "TBL",
1929 &spr_read_tbl, SPR_NOACCESS,
1930 &spr_read_tbl, SPR_NOACCESS,
1931 0x00000000);
1932 spr_register(env, SPR_403_TBL, "TBL",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 SPR_NOACCESS, &spr_write_tbl,
1935 0x00000000);
1936 spr_register(env, SPR_403_VTBU, "TBU",
1937 &spr_read_tbu, SPR_NOACCESS,
1938 &spr_read_tbu, SPR_NOACCESS,
1939 0x00000000);
1940 spr_register(env, SPR_403_TBU, "TBU",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 SPR_NOACCESS, &spr_write_tbu,
1943 0x00000000);
1944 /* Debug */
1945 /* not emulated, as Qemu do not emulate caches */
1946 spr_register(env, SPR_403_CDBCR, "CDBCR",
1947 SPR_NOACCESS, SPR_NOACCESS,
1948 &spr_read_generic, &spr_write_generic,
1949 0x00000000);
1950 }
1951
1952 /* SPR specific to PowerPC 401 implementation */
1953 static void gen_spr_401 (CPUPPCState *env)
1954 {
1955 /* Debug interface */
1956 /* XXX : not implemented */
1957 spr_register(env, SPR_40x_DBCR0, "DBCR",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_40x_dbcr0,
1960 0x00000000);
1961 /* XXX : not implemented */
1962 spr_register(env, SPR_40x_DBSR, "DBSR",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_clear,
1965 /* Last reset was system reset */
1966 0x00000300);
1967 /* XXX : not implemented */
1968 spr_register(env, SPR_40x_DAC1, "DAC",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, &spr_write_generic,
1971 0x00000000);
1972 /* XXX : not implemented */
1973 spr_register(env, SPR_40x_IAC1, "IAC",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_generic,
1976 0x00000000);
1977 /* Storage control */
1978 /* XXX: TODO: not implemented */
1979 spr_register(env, SPR_405_SLER, "SLER",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_generic, &spr_write_40x_sler,
1982 0x00000000);
1983 /* not emulated, as Qemu never does speculative access */
1984 spr_register(env, SPR_40x_SGR, "SGR",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, &spr_write_generic,
1987 0xFFFFFFFF);
1988 /* not emulated, as Qemu do not emulate caches */
1989 spr_register(env, SPR_40x_DCWR, "DCWR",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_generic,
1992 0x00000000);
1993 }
1994
1995 static void gen_spr_401x2 (CPUPPCState *env)
1996 {
1997 gen_spr_401(env);
1998 spr_register(env, SPR_40x_PID, "PID",
1999 SPR_NOACCESS, SPR_NOACCESS,
2000 &spr_read_generic, &spr_write_generic,
2001 0x00000000);
2002 spr_register(env, SPR_40x_ZPR, "ZPR",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 }
2007
2008 /* SPR specific to PowerPC 403 implementation */
2009 static void gen_spr_403 (CPUPPCState *env)
2010 {
2011 /* Debug interface */
2012 /* XXX : not implemented */
2013 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_40x_dbcr0,
2016 0x00000000);
2017 /* XXX : not implemented */
2018 spr_register(env, SPR_40x_DBSR, "DBSR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_clear,
2021 /* Last reset was system reset */
2022 0x00000300);
2023 /* XXX : not implemented */
2024 spr_register(env, SPR_40x_DAC1, "DAC1",
2025 SPR_NOACCESS, SPR_NOACCESS,
2026 &spr_read_generic, &spr_write_generic,
2027 0x00000000);
2028 /* XXX : not implemented */
2029 spr_register(env, SPR_40x_DAC2, "DAC2",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_40x_IAC1, "IAC1",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_40x_IAC2, "IAC2",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 }
2044
2045 static void gen_spr_403_real (CPUPPCState *env)
2046 {
2047 spr_register(env, SPR_403_PBL1, "PBL1",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_403_pbr, &spr_write_403_pbr,
2050 0x00000000);
2051 spr_register(env, SPR_403_PBU1, "PBU1",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 &spr_read_403_pbr, &spr_write_403_pbr,
2054 0x00000000);
2055 spr_register(env, SPR_403_PBL2, "PBL2",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_403_pbr, &spr_write_403_pbr,
2058 0x00000000);
2059 spr_register(env, SPR_403_PBU2, "PBU2",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_403_pbr, &spr_write_403_pbr,
2062 0x00000000);
2063 }
2064
2065 static void gen_spr_403_mmu (CPUPPCState *env)
2066 {
2067 /* MMU */
2068 spr_register(env, SPR_40x_PID, "PID",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 spr_register(env, SPR_40x_ZPR, "ZPR",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
2076 }
2077
2078 /* SPR specific to PowerPC compression coprocessor extension */
2079 static void gen_spr_compress (CPUPPCState *env)
2080 {
2081 /* XXX : not implemented */
2082 spr_register(env, SPR_401_SKR, "SKR",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_generic, &spr_write_generic,
2085 0x00000000);
2086 }
2087
2088 #if defined (TARGET_PPC64)
2089 /* SPR specific to PowerPC 620 */
2090 static void gen_spr_620 (CPUPPCState *env)
2091 {
2092 /* Processor identification */
2093 spr_register(env, SPR_PIR, "PIR",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, &spr_write_pir,
2096 0x00000000);
2097 spr_register(env, SPR_ASR, "ASR",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_asr, &spr_write_asr,
2100 0x00000000);
2101 /* Breakpoints */
2102 /* XXX : not implemented */
2103 spr_register(env, SPR_IABR, "IABR",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 /* XXX : not implemented */
2108 spr_register(env, SPR_DABR, "DABR",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
2112 /* XXX : not implemented */
2113 spr_register(env, SPR_SIAR, "SIAR",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, SPR_NOACCESS,
2116 0x00000000);
2117 /* XXX : not implemented */
2118 spr_register(env, SPR_SDA, "SDA",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, SPR_NOACCESS,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_620_PMC1R, "PMC1",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, SPR_NOACCESS,
2126 0x00000000);
2127 spr_register(env, SPR_620_PMC1W, "PMC1",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 SPR_NOACCESS, &spr_write_generic,
2130 0x00000000);
2131 /* XXX : not implemented */
2132 spr_register(env, SPR_620_PMC2R, "PMC2",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, SPR_NOACCESS,
2135 0x00000000);
2136 spr_register(env, SPR_620_PMC2W, "PMC2",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 SPR_NOACCESS, &spr_write_generic,
2139 0x00000000);
2140 /* XXX : not implemented */
2141 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, SPR_NOACCESS,
2144 0x00000000);
2145 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 SPR_NOACCESS, &spr_write_generic,
2148 0x00000000);
2149 /* External access control */
2150 /* XXX : not implemented */
2151 spr_register(env, SPR_EAR, "EAR",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_generic,
2154 0x00000000);
2155 #if 0 // XXX: check this
2156 /* XXX : not implemented */
2157 spr_register(env, SPR_620_PMR0, "PMR0",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, &spr_write_generic,
2160 0x00000000);
2161 /* XXX : not implemented */
2162 spr_register(env, SPR_620_PMR1, "PMR1",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_generic, &spr_write_generic,
2165 0x00000000);
2166 /* XXX : not implemented */
2167 spr_register(env, SPR_620_PMR2, "PMR2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_620_PMR3, "PMR3",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, &spr_write_generic,
2175 0x00000000);
2176 /* XXX : not implemented */
2177 spr_register(env, SPR_620_PMR4, "PMR4",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_620_PMR5, "PMR5",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186 /* XXX : not implemented */
2187 spr_register(env, SPR_620_PMR6, "PMR6",
2188 SPR_NOACCESS, SPR_NOACCESS,
2189 &spr_read_generic, &spr_write_generic,
2190 0x00000000);
2191 /* XXX : not implemented */
2192 spr_register(env, SPR_620_PMR7, "PMR7",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 &spr_read_generic, &spr_write_generic,
2195 0x00000000);
2196 /* XXX : not implemented */
2197 spr_register(env, SPR_620_PMR8, "PMR8",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_generic, &spr_write_generic,
2200 0x00000000);
2201 /* XXX : not implemented */
2202 spr_register(env, SPR_620_PMR9, "PMR9",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 /* XXX : not implemented */
2207 spr_register(env, SPR_620_PMRA, "PMR10",
2208 SPR_NOACCESS, SPR_NOACCESS,
2209 &spr_read_generic, &spr_write_generic,
2210 0x00000000);
2211 /* XXX : not implemented */
2212 spr_register(env, SPR_620_PMRB, "PMR11",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 0x00000000);
2216 /* XXX : not implemented */
2217 spr_register(env, SPR_620_PMRC, "PMR12",
2218 SPR_NOACCESS, SPR_NOACCESS,
2219 &spr_read_generic, &spr_write_generic,
2220 0x00000000);
2221 /* XXX : not implemented */
2222 spr_register(env, SPR_620_PMRD, "PMR13",
2223 SPR_NOACCESS, SPR_NOACCESS,
2224 &spr_read_generic, &spr_write_generic,
2225 0x00000000);
2226 /* XXX : not implemented */
2227 spr_register(env, SPR_620_PMRE, "PMR14",
2228 SPR_NOACCESS, SPR_NOACCESS,
2229 &spr_read_generic, &spr_write_generic,
2230 0x00000000);
2231 /* XXX : not implemented */
2232 spr_register(env, SPR_620_PMRF, "PMR15",
2233 SPR_NOACCESS, SPR_NOACCESS,
2234 &spr_read_generic, &spr_write_generic,
2235 0x00000000);
2236 #endif
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_620_L2CR, "L2CR",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_620_L2SR, "L2SR",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 }
2253 #endif /* defined (TARGET_PPC64) */
2254
2255 static void gen_spr_5xx_8xx (CPUPPCState *env)
2256 {
2257 /* Exception processing */
2258 spr_register(env, SPR_DSISR, "DSISR",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 spr_register(env, SPR_DAR, "DAR",
2263 SPR_NOACCESS, SPR_NOACCESS,
2264 &spr_read_generic, &spr_write_generic,
2265 0x00000000);
2266 /* Timer */
2267 spr_register(env, SPR_DECR, "DECR",
2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_decr, &spr_write_decr,
2270 0x00000000);
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_MPC_EIE, "EIE",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_MPC_EID, "EID",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_MPC_NRI, "NRI",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 /* XXX : not implemented */
2287 spr_register(env, SPR_MPC_CMPA, "CMPA",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 /* XXX : not implemented */
2292 spr_register(env, SPR_MPC_CMPB, "CMPB",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
2296 /* XXX : not implemented */
2297 spr_register(env, SPR_MPC_CMPC, "CMPC",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 &spr_read_generic, &spr_write_generic,
2300 0x00000000);
2301 /* XXX : not implemented */
2302 spr_register(env, SPR_MPC_CMPD, "CMPD",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2305 0x00000000);
2306 /* XXX : not implemented */
2307 spr_register(env, SPR_MPC_ECR, "ECR",
2308 SPR_NOACCESS, SPR_NOACCESS,
2309 &spr_read_generic, &spr_write_generic,
2310 0x00000000);
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_MPC_DER, "DER",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* XXX : not implemented */
2317 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
2321 /* XXX : not implemented */
2322 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_MPC_CMPE, "CMPE",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_MPC_CMPF, "CMPF",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_MPC_CMPG, "CMPG",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 /* XXX : not implemented */
2342 spr_register(env, SPR_MPC_CMPH, "CMPH",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 /* XXX : not implemented */
2347 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_MPC_BAR, "BAR",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_MPC_DPDR, "DPDR",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_MPC_IMMR, "IMMR",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 }
2372
2373 static void gen_spr_5xx (CPUPPCState *env)
2374 {
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 }
2481
2482 static void gen_spr_8xx (CPUPPCState *env)
2483 {
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 /* XXX : not implemented */
2545 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2546 SPR_NOACCESS, SPR_NOACCESS,
2547 &spr_read_generic, &spr_write_generic,
2548 0x00000000);
2549 /* XXX : not implemented */
2550 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2551 SPR_NOACCESS, SPR_NOACCESS,
2552 &spr_read_generic, &spr_write_generic,
2553 0x00000000);
2554 /* XXX : not implemented */
2555 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2556 SPR_NOACCESS, SPR_NOACCESS,
2557 &spr_read_generic, &spr_write_generic,
2558 0x00000000);
2559 /* XXX : not implemented */
2560 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2561 SPR_NOACCESS, SPR_NOACCESS,
2562 &spr_read_generic, &spr_write_generic,
2563 0x00000000);
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 /* XXX : not implemented */
2580 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2581 SPR_NOACCESS, SPR_NOACCESS,
2582 &spr_read_generic, &spr_write_generic,
2583 0x00000000);
2584 /* XXX : not implemented */
2585 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2586 SPR_NOACCESS, SPR_NOACCESS,
2587 &spr_read_generic, &spr_write_generic,
2588 0x00000000);
2589 /* XXX : not implemented */
2590 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2591 SPR_NOACCESS, SPR_NOACCESS,
2592 &spr_read_generic, &spr_write_generic,
2593 0x00000000);
2594 /* XXX : not implemented */
2595 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2596 SPR_NOACCESS, SPR_NOACCESS,
2597 &spr_read_generic, &spr_write_generic,
2598 0x00000000);
2599 /* XXX : not implemented */
2600 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2601 SPR_NOACCESS, SPR_NOACCESS,
2602 &spr_read_generic, &spr_write_generic,
2603 0x00000000);
2604 /* XXX : not implemented */
2605 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2606 SPR_NOACCESS, SPR_NOACCESS,
2607 &spr_read_generic, &spr_write_generic,
2608 0x00000000);
2609 }
2610
2611 // XXX: TODO
2612 /*
2613 * AMR => SPR 29 (Power 2.04)
2614 * CTRL => SPR 136 (Power 2.04)
2615 * CTRL => SPR 152 (Power 2.04)
2616 * SCOMC => SPR 276 (64 bits ?)
2617 * SCOMD => SPR 277 (64 bits ?)
2618 * TBU40 => SPR 286 (Power 2.04 hypv)
2619 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2620 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2621 * HDSISR => SPR 306 (Power 2.04 hypv)
2622 * HDAR => SPR 307 (Power 2.04 hypv)
2623 * PURR => SPR 309 (Power 2.04 hypv)
2624 * HDEC => SPR 310 (Power 2.04 hypv)
2625 * HIOR => SPR 311 (hypv)
2626 * RMOR => SPR 312 (970)
2627 * HRMOR => SPR 313 (Power 2.04 hypv)
2628 * HSRR0 => SPR 314 (Power 2.04 hypv)
2629 * HSRR1 => SPR 315 (Power 2.04 hypv)
2630 * LPCR => SPR 316 (970)
2631 * LPIDR => SPR 317 (970)
2632 * EPR => SPR 702 (Power 2.04 emb)
2633 * perf => 768-783 (Power 2.04)
2634 * perf => 784-799 (Power 2.04)
2635 * PPR => SPR 896 (Power 2.04)
2636 * EPLC => SPR 947 (Power 2.04 emb)
2637 * EPSC => SPR 948 (Power 2.04 emb)
2638 * DABRX => 1015 (Power 2.04 hypv)
2639 * FPECR => SPR 1022 (?)
2640 * ... and more (thermal management, performance counters, ...)
2641 */
2642
2643 /*****************************************************************************/
2644 /* Exception vectors models */
2645 static void init_excp_4xx_real (CPUPPCState *env)
2646 {
2647 #if !defined(CONFIG_USER_ONLY)
2648 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2649 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2650 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2651 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2652 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2653 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2654 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2655 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2656 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2657 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2658 env->hreset_excp_prefix = 0x00000000UL;
2659 env->ivor_mask = 0x0000FFF0UL;
2660 env->ivpr_mask = 0xFFFF0000UL;
2661 /* Hardware reset vector */
2662 env->hreset_vector = 0xFFFFFFFCUL;
2663 #endif
2664 }
2665
2666 static void init_excp_4xx_softmmu (CPUPPCState *env)
2667 {
2668 #if !defined(CONFIG_USER_ONLY)
2669 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2670 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2671 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2672 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2673 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2674 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2675 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2676 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2677 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2678 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2679 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2680 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2681 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2682 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2683 env->hreset_excp_prefix = 0x00000000UL;
2684 env->ivor_mask = 0x0000FFF0UL;
2685 env->ivpr_mask = 0xFFFF0000UL;
2686 /* Hardware reset vector */
2687 env->hreset_vector = 0xFFFFFFFCUL;
2688 #endif
2689 }
2690
2691 static void init_excp_MPC5xx (CPUPPCState *env)
2692 {
2693 #if !defined(CONFIG_USER_ONLY)
2694 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2695 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2696 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2697 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2698 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2699 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2700 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2701 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2702 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2703 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2704 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2705 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2706 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2707 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2708 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2709 env->hreset_excp_prefix = 0x00000000UL;
2710 env->ivor_mask = 0x0000FFF0UL;
2711 env->ivpr_mask = 0xFFFF0000UL;
2712 /* Hardware reset vector */
2713 env->hreset_vector = 0xFFFFFFFCUL;
2714 #endif
2715 }
2716
2717 static void init_excp_MPC8xx (CPUPPCState *env)
2718 {
2719 #if !defined(CONFIG_USER_ONLY)
2720 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2721 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2722 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2723 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2724 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2725 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2726 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2727 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2728 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2729 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2730 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2731 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2732 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2733 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2734 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2735 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2736 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2737 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2739 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2740 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2741 env->hreset_excp_prefix = 0x00000000UL;
2742 env->ivor_mask = 0x0000FFF0UL;
2743 env->ivpr_mask = 0xFFFF0000UL;
2744 /* Hardware reset vector */
2745 env->hreset_vector = 0xFFFFFFFCUL;
2746 #endif
2747 }
2748
2749 static void init_excp_G2 (CPUPPCState *env)
2750 {
2751 #if !defined(CONFIG_USER_ONLY)
2752 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2753 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2754 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2755 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2756 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2757 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2758 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2759 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2760 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2761 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2762 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2763 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2764 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2765 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2766 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2767 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2768 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2769 env->hreset_excp_prefix = 0x00000000UL;
2770 /* Hardware reset vector */
2771 env->hreset_vector = 0xFFFFFFFCUL;
2772 #endif
2773 }
2774
2775 static void init_excp_e200 (CPUPPCState *env)
2776 {
2777 #if !defined(CONFIG_USER_ONLY)
2778 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2779 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2780 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2781 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2782 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2783 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2784 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2785 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2786 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2787 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2788 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2789 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2790 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2791 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2792 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2793 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2794 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2795 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2796 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2797 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2798 env->hreset_excp_prefix = 0x00000000UL;
2799 env->ivor_mask = 0x0000FFF7UL;
2800 env->ivpr_mask = 0xFFFF0000UL;
2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
2803 #endif
2804 }
2805
2806 static void init_excp_BookE (CPUPPCState *env)
2807 {
2808 #if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2810 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2811 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2825 env->hreset_excp_prefix = 0x00000000UL;
2826 env->ivor_mask = 0x0000FFE0UL;
2827 env->ivpr_mask = 0xFFFF0000UL;
2828 /* Hardware reset vector */
2829 env->hreset_vector = 0xFFFFFFFCUL;
2830 #endif
2831 }
2832
2833 static void init_excp_601 (CPUPPCState *env)
2834 {
2835 #if !defined(CONFIG_USER_ONLY)
2836 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2837 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2838 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2839 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2840 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2841 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2842 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2843 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2844 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2845 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2846 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2847 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2848 env->hreset_excp_prefix = 0xFFF00000UL;
2849 /* Hardware reset vector */
2850 env->hreset_vector = 0x00000100UL;
2851 #endif
2852 }
2853
2854 static void init_excp_602 (CPUPPCState *env)
2855 {
2856 #if !defined(CONFIG_USER_ONLY)
2857 /* XXX: exception prefix has a special behavior on 602 */
2858 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2859 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2860 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2861 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2862 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2863 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2864 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2865 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2866 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2867 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2868 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2869 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2870 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2871 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2872 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2873 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2874 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2875 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2876 env->hreset_excp_prefix = 0xFFF00000UL;
2877 /* Hardware reset vector */
2878 env->hreset_vector = 0xFFFFFFFCUL;
2879 #endif
2880 }
2881
2882 static void init_excp_603 (CPUPPCState *env)
2883 {
2884 #if !defined(CONFIG_USER_ONLY)
2885 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2886 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2887 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2888 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2889 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2890 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2891 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2892 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2893 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2894 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2895 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2896 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2897 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2898 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2899 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2900 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2901 env->hreset_excp_prefix = 0x00000000UL;
2902 /* Hardware reset vector */
2903 env->hreset_vector = 0xFFFFFFFCUL;
2904 #endif
2905 }
2906
2907 static void init_excp_604 (CPUPPCState *env)
2908 {
2909 #if !defined(CONFIG_USER_ONLY)
2910 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2911 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2912 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2913 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2914 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2915 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2916 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2917 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2918 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2919 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2920 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2921 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2922 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2923 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2924 env->hreset_excp_prefix = 0xFFF00000UL;
2925 /* Hardware reset vector */
2926 env->hreset_vector = 0x00000100UL;
2927 #endif
2928 }
2929
2930 #if defined(TARGET_PPC64)
2931 static void init_excp_620 (CPUPPCState *env)
2932 {
2933 #if !defined(CONFIG_USER_ONLY)
2934 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2935 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2936 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2937 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2938 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2939 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2940 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2941 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2942 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2943 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2944 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2945 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2946 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2947 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2948 env->hreset_excp_prefix = 0xFFF00000UL;
2949 /* Hardware reset vector */
2950 env->hreset_vector = 0x0000000000000100ULL;
2951 #endif
2952 }
2953 #endif /* defined(TARGET_PPC64) */
2954
2955 static void init_excp_7x0 (CPUPPCState *env)
2956 {
2957 #if !defined(CONFIG_USER_ONLY)
2958 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2959 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2960 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2961 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2962 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2963 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2964 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2965 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2966 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2967 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2968 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2969 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2970 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2971 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2972 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2973 env->hreset_excp_prefix = 0x00000000UL;
2974 /* Hardware reset vector */
2975 env->hreset_vector = 0xFFFFFFFCUL;
2976 #endif
2977 }
2978
2979 static void init_excp_750cl (CPUPPCState *env)
2980 {
2981 #if !defined(CONFIG_USER_ONLY)
2982 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2983 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2984 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2985 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2986 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2987 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2988 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2989 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2990 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2991 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2992 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2993 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2994 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2995 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2996 env->hreset_excp_prefix = 0x00000000UL;
2997 /* Hardware reset vector */
2998 env->hreset_vector = 0xFFFFFFFCUL;
2999 #endif
3000 }
3001
3002 static void init_excp_750cx (CPUPPCState *env)
3003 {
3004 #if !defined(CONFIG_USER_ONLY)
3005 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3006 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3007 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3008 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3009 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3010 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3011 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3012 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3013 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3014 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3015 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3016 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3017 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3018 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3019 env->hreset_excp_prefix = 0x00000000UL;
3020 /* Hardware reset vector */
3021 env->hreset_vector = 0xFFFFFFFCUL;
3022 #endif
3023 }
3024
3025 /* XXX: Check if this is correct */
3026 static void init_excp_7x5 (CPUPPCState *env)
3027 {
3028 #if !defined(CONFIG_USER_ONLY)
3029 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3030 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3031 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3032 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3033 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3034 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3035 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3036 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3037 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3038 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3039 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3040 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3041 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3042 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3043 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3044 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3045 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3046 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3047 env->hreset_excp_prefix = 0x00000000UL;
3048 /* Hardware reset vector */
3049 env->hreset_vector = 0xFFFFFFFCUL;
3050 #endif
3051 }
3052
3053 static void init_excp_7400 (CPUPPCState *env)
3054 {
3055 #if !defined(CONFIG_USER_ONLY)
3056 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3057 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3058 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3059 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3060 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3061 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3062 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3063 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3064 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3065 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3066 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3067 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3068 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3069 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3070 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3071 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3072 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3073 env->hreset_excp_prefix = 0x00000000UL;
3074 /* Hardware reset vector */
3075 env->hreset_vector = 0xFFFFFFFCUL;
3076 #endif
3077 }
3078
3079 static void init_excp_7450 (CPUPPCState *env)
3080 {
3081 #if !defined(CONFIG_USER_ONLY)
3082 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3083 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3084 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3085 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3086 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3087 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3088 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3089 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3090 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3091 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3092 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3093 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3094 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3095 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3096 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3097 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3098 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3099 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3100 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3101 env->hreset_excp_prefix = 0x00000000UL;
3102 /* Hardware reset vector */
3103 env->hreset_vector = 0xFFFFFFFCUL;
3104 #endif
3105 }
3106
3107 #if defined (TARGET_PPC64)
3108 static void init_excp_970 (CPUPPCState *env)
3109 {
3110 #if !defined(CONFIG_USER_ONLY)
3111 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;