Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
25 #include "dis-asm.h"
26 #include "gdbstub.h"
27
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DUMP_SPR_ACCESSES
31 #if defined(CONFIG_USER_ONLY)
32 #define TODO_USER_ONLY 1
33 #endif
34
35 struct ppc_def_t {
36 const char *name;
37 uint32_t pvr;
38 uint32_t svr;
39 uint64_t insns_flags;
40 uint64_t insns_flags2;
41 uint64_t msr_mask;
42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
45 uint32_t flags;
46 int bfd_mach;
47 void (*init_proc)(CPUPPCState *env);
48 int (*check_pow)(CPUPPCState *env);
49 };
50
51 /* For user-mode emulation, we don't emulate any IRQ controller */
52 #if defined(CONFIG_USER_ONLY)
53 #define PPC_IRQ_INIT_FN(name) \
54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55 { \
56 }
57 #else
58 #define PPC_IRQ_INIT_FN(name) \
59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60 #endif
61
62 PPC_IRQ_INIT_FN(40x);
63 PPC_IRQ_INIT_FN(6xx);
64 PPC_IRQ_INIT_FN(970);
65 PPC_IRQ_INIT_FN(POWER7);
66 PPC_IRQ_INIT_FN(e500);
67
68 /* Generic callbacks:
69 * do nothing but store/retrieve spr value
70 */
71 static void spr_read_generic (void *opaque, int gprn, int sprn)
72 {
73 gen_load_spr(cpu_gpr[gprn], sprn);
74 #ifdef PPC_DUMP_SPR_ACCESSES
75 {
76 TCGv t0 = tcg_const_i32(sprn);
77 gen_helper_load_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 }
80 #endif
81 }
82
83 static void spr_write_generic (void *opaque, int sprn, int gprn)
84 {
85 gen_store_spr(sprn, cpu_gpr[gprn]);
86 #ifdef PPC_DUMP_SPR_ACCESSES
87 {
88 TCGv t0 = tcg_const_i32(sprn);
89 gen_helper_store_dump_spr(t0);
90 tcg_temp_free_i32(t0);
91 }
92 #endif
93 }
94
95 #if !defined(CONFIG_USER_ONLY)
96 static void spr_write_clear (void *opaque, int sprn, int gprn)
97 {
98 TCGv t0 = tcg_temp_new();
99 TCGv t1 = tcg_temp_new();
100 gen_load_spr(t0, sprn);
101 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
102 tcg_gen_and_tl(t0, t0, t1);
103 gen_store_spr(sprn, t0);
104 tcg_temp_free(t0);
105 tcg_temp_free(t1);
106 }
107 #endif
108
109 /* SPR common to all PowerPC */
110 /* XER */
111 static void spr_read_xer (void *opaque, int gprn, int sprn)
112 {
113 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
114 }
115
116 static void spr_write_xer (void *opaque, int sprn, int gprn)
117 {
118 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
119 }
120
121 /* LR */
122 static void spr_read_lr (void *opaque, int gprn, int sprn)
123 {
124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
125 }
126
127 static void spr_write_lr (void *opaque, int sprn, int gprn)
128 {
129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
130 }
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 if (use_icount) {
160 gen_io_start();
161 }
162 gen_helper_load_decr(cpu_gpr[gprn]);
163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
167 }
168
169 static void spr_write_decr (void *opaque, int sprn, int gprn)
170 {
171 if (use_icount) {
172 gen_io_start();
173 }
174 gen_helper_store_decr(cpu_gpr[gprn]);
175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC, except 601 */
183 /* Time base */
184 static void spr_read_tbl (void *opaque, int gprn, int sprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_load_tbl(cpu_gpr[gprn]);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195
196 static void spr_read_tbu (void *opaque, int gprn, int sprn)
197 {
198 if (use_icount) {
199 gen_io_start();
200 }
201 gen_helper_load_tbu(cpu_gpr[gprn]);
202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
206 }
207
208 __attribute__ (( unused ))
209 static void spr_read_atbl (void *opaque, int gprn, int sprn)
210 {
211 gen_helper_load_atbl(cpu_gpr[gprn]);
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbu (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbu(cpu_gpr[gprn]);
218 }
219
220 #if !defined(CONFIG_USER_ONLY)
221 static void spr_write_tbl (void *opaque, int sprn, int gprn)
222 {
223 if (use_icount) {
224 gen_io_start();
225 }
226 gen_helper_store_tbl(cpu_gpr[gprn]);
227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
231 }
232
233 static void spr_write_tbu (void *opaque, int sprn, int gprn)
234 {
235 if (use_icount) {
236 gen_io_start();
237 }
238 gen_helper_store_tbu(cpu_gpr[gprn]);
239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
243 }
244
245 __attribute__ (( unused ))
246 static void spr_write_atbl (void *opaque, int sprn, int gprn)
247 {
248 gen_helper_store_atbl(cpu_gpr[gprn]);
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbu (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbu(cpu_gpr[gprn]);
255 }
256
257 #if defined(TARGET_PPC64)
258 __attribute__ (( unused ))
259 static void spr_read_purr (void *opaque, int gprn, int sprn)
260 {
261 gen_helper_load_purr(cpu_gpr[gprn]);
262 }
263 #endif
264 #endif
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* IBAT0U...IBAT0U */
268 /* IBAT0L...IBAT7L */
269 static void spr_read_ibat (void *opaque, int gprn, int sprn)
270 {
271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
272 }
273
274 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
275 {
276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
277 }
278
279 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
280 {
281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
284 }
285
286 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
287 {
288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
291 }
292
293 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 /* DBAT0U...DBAT7U */
308 /* DBAT0L...DBAT7L */
309 static void spr_read_dbat (void *opaque, int gprn, int sprn)
310 {
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
312 }
313
314 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
315 {
316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
317 }
318
319 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 /* SDR1 */
348 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
349 {
350 gen_helper_store_sdr1(cpu_gpr[gprn]);
351 }
352
353 /* 64 bits PowerPC specific SPRs */
354 /* ASR */
355 #if defined(TARGET_PPC64)
356 static void spr_read_hior (void *opaque, int gprn, int sprn)
357 {
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
359 }
360
361 static void spr_write_hior (void *opaque, int sprn, int gprn)
362 {
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
366 tcg_temp_free(t0);
367 }
368
369 static void spr_read_asr (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
372 }
373
374 static void spr_write_asr (void *opaque, int sprn, int gprn)
375 {
376 gen_helper_store_asr(cpu_gpr[gprn]);
377 }
378 #endif
379 #endif
380
381 /* PowerPC 601 specific registers */
382 /* RTC */
383 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
384 {
385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
386 }
387
388 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
391 }
392
393 #if !defined(CONFIG_USER_ONLY)
394 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
397 }
398
399 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
402 }
403
404 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
405 {
406 DisasContext *ctx = opaque;
407
408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
409 /* Must stop the translation as endianness may have changed */
410 gen_stop_exception(ctx);
411 }
412 #endif
413
414 /* Unified bats */
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
417 {
418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
419 }
420
421 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
422 {
423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
426 }
427
428 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
429 {
430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
433 }
434 #endif
435
436 /* PowerPC 40x specific registers */
437 #if !defined(CONFIG_USER_ONLY)
438 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
439 {
440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
441 }
442
443 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
444 {
445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
446 }
447
448 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
449 {
450 DisasContext *ctx = opaque;
451
452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
453 /* We must stop translation as we may have rebooted */
454 gen_stop_exception(ctx);
455 }
456
457 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
460 }
461
462 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
470 }
471 #endif
472
473 /* PowerPC 403 specific registers */
474 /* PBL1 / PBU1 / PBL2 / PBU2 */
475 #if !defined(CONFIG_USER_ONLY)
476 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
477 {
478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
479 }
480
481 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
482 {
483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
486 }
487
488 static void spr_write_pir (void *opaque, int sprn, int gprn)
489 {
490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
494 }
495 #endif
496
497 /* SPE specific registers */
498 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499 {
500 TCGv_i32 t0 = tcg_temp_new_i32();
501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507 {
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
511 tcg_temp_free_i32(t0);
512 }
513
514 #if !defined(CONFIG_USER_ONLY)
515 /* Callback used to write the exception vector base */
516 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
522 gen_store_spr(sprn, t0);
523 tcg_temp_free(t0);
524 }
525
526 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
527 {
528 DisasContext *ctx = opaque;
529
530 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
544 } else {
545 printf("Trying to write an unknown exception vector %d %03x\n",
546 sprn, sprn);
547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
548 }
549 }
550 #endif
551
552 static inline void vscr_init (CPUPPCState *env, uint32_t val)
553 {
554 env->vscr = val;
555 /* Altivec always uses round-to-nearest */
556 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
557 set_flush_to_zero(vscr_nj, &env->vec_status);
558 }
559
560 #if defined(CONFIG_USER_ONLY)
561 #define spr_register(env, num, name, uea_read, uea_write, \
562 oea_read, oea_write, initial_value) \
563 do { \
564 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
565 } while (0)
566 static inline void _spr_register (CPUPPCState *env, int num,
567 const char *name,
568 void (*uea_read)(void *opaque, int gprn, int sprn),
569 void (*uea_write)(void *opaque, int sprn, int gprn),
570 target_ulong initial_value)
571 #else
572 static inline void spr_register (CPUPPCState *env, int num,
573 const char *name,
574 void (*uea_read)(void *opaque, int gprn, int sprn),
575 void (*uea_write)(void *opaque, int sprn, int gprn),
576 void (*oea_read)(void *opaque, int gprn, int sprn),
577 void (*oea_write)(void *opaque, int sprn, int gprn),
578 target_ulong initial_value)
579 #endif
580 {
581 ppc_spr_t *spr;
582
583 spr = &env->spr_cb[num];
584 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
585 #if !defined(CONFIG_USER_ONLY)
586 spr->oea_read != NULL || spr->oea_write != NULL ||
587 #endif
588 spr->uea_read != NULL || spr->uea_write != NULL) {
589 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
590 exit(1);
591 }
592 #if defined(PPC_DEBUG_SPR)
593 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
594 name, initial_value);
595 #endif
596 spr->name = name;
597 spr->uea_read = uea_read;
598 spr->uea_write = uea_write;
599 #if !defined(CONFIG_USER_ONLY)
600 spr->oea_read = oea_read;
601 spr->oea_write = oea_write;
602 #endif
603 env->spr[num] = initial_value;
604 }
605
606 /* Generic PowerPC SPRs */
607 static void gen_spr_generic (CPUPPCState *env)
608 {
609 /* Integer processing */
610 spr_register(env, SPR_XER, "XER",
611 &spr_read_xer, &spr_write_xer,
612 &spr_read_xer, &spr_write_xer,
613 0x00000000);
614 /* Branch contol */
615 spr_register(env, SPR_LR, "LR",
616 &spr_read_lr, &spr_write_lr,
617 &spr_read_lr, &spr_write_lr,
618 0x00000000);
619 spr_register(env, SPR_CTR, "CTR",
620 &spr_read_ctr, &spr_write_ctr,
621 &spr_read_ctr, &spr_write_ctr,
622 0x00000000);
623 /* Interrupt processing */
624 spr_register(env, SPR_SRR0, "SRR0",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628 spr_register(env, SPR_SRR1, "SRR1",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632 /* Processor control */
633 spr_register(env, SPR_SPRG0, "SPRG0",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_generic,
636 0x00000000);
637 spr_register(env, SPR_SPRG1, "SPRG1",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SPRG2, "SPRG2",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 spr_register(env, SPR_SPRG3, "SPRG3",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 }
650
651 /* SPR common to all non-embedded PowerPC, including 601 */
652 static void gen_spr_ne_601 (CPUPPCState *env)
653 {
654 /* Exception processing */
655 spr_register(env, SPR_DSISR, "DSISR",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_DAR, "DAR",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Timer */
664 spr_register(env, SPR_DECR, "DECR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_decr, &spr_write_decr,
667 0x00000000);
668 /* Memory management */
669 spr_register(env, SPR_SDR1, "SDR1",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, &spr_write_sdr1,
672 0x00000000);
673 }
674
675 /* BATs 0-3 */
676 static void gen_low_BATs (CPUPPCState *env)
677 {
678 #if !defined(CONFIG_USER_ONLY)
679 spr_register(env, SPR_IBAT0U, "IBAT0U",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat, &spr_write_ibatu,
682 0x00000000);
683 spr_register(env, SPR_IBAT0L, "IBAT0L",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat, &spr_write_ibatl,
686 0x00000000);
687 spr_register(env, SPR_IBAT1U, "IBAT1U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat, &spr_write_ibatu,
690 0x00000000);
691 spr_register(env, SPR_IBAT1L, "IBAT1L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat, &spr_write_ibatl,
694 0x00000000);
695 spr_register(env, SPR_IBAT2U, "IBAT2U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat, &spr_write_ibatu,
698 0x00000000);
699 spr_register(env, SPR_IBAT2L, "IBAT2L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatl,
702 0x00000000);
703 spr_register(env, SPR_IBAT3U, "IBAT3U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatu,
706 0x00000000);
707 spr_register(env, SPR_IBAT3L, "IBAT3L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatl,
710 0x00000000);
711 spr_register(env, SPR_DBAT0U, "DBAT0U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat, &spr_write_dbatu,
714 0x00000000);
715 spr_register(env, SPR_DBAT0L, "DBAT0L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat, &spr_write_dbatl,
718 0x00000000);
719 spr_register(env, SPR_DBAT1U, "DBAT1U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat, &spr_write_dbatu,
722 0x00000000);
723 spr_register(env, SPR_DBAT1L, "DBAT1L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat, &spr_write_dbatl,
726 0x00000000);
727 spr_register(env, SPR_DBAT2U, "DBAT2U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat, &spr_write_dbatu,
730 0x00000000);
731 spr_register(env, SPR_DBAT2L, "DBAT2L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatl,
734 0x00000000);
735 spr_register(env, SPR_DBAT3U, "DBAT3U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatu,
738 0x00000000);
739 spr_register(env, SPR_DBAT3L, "DBAT3L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatl,
742 0x00000000);
743 env->nb_BATs += 4;
744 #endif
745 }
746
747 /* BATs 4-7 */
748 static void gen_high_BATs (CPUPPCState *env)
749 {
750 #if !defined(CONFIG_USER_ONLY)
751 spr_register(env, SPR_IBAT4U, "IBAT4U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat_h, &spr_write_ibatu_h,
754 0x00000000);
755 spr_register(env, SPR_IBAT4L, "IBAT4L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat_h, &spr_write_ibatl_h,
758 0x00000000);
759 spr_register(env, SPR_IBAT5U, "IBAT5U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat_h, &spr_write_ibatu_h,
762 0x00000000);
763 spr_register(env, SPR_IBAT5L, "IBAT5L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat_h, &spr_write_ibatl_h,
766 0x00000000);
767 spr_register(env, SPR_IBAT6U, "IBAT6U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat_h, &spr_write_ibatu_h,
770 0x00000000);
771 spr_register(env, SPR_IBAT6L, "IBAT6L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatl_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT7U, "IBAT7U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatu_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT7L, "IBAT7L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatl_h,
782 0x00000000);
783 spr_register(env, SPR_DBAT4U, "DBAT4U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat_h, &spr_write_dbatu_h,
786 0x00000000);
787 spr_register(env, SPR_DBAT4L, "DBAT4L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat_h, &spr_write_dbatl_h,
790 0x00000000);
791 spr_register(env, SPR_DBAT5U, "DBAT5U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat_h, &spr_write_dbatu_h,
794 0x00000000);
795 spr_register(env, SPR_DBAT5L, "DBAT5L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat_h, &spr_write_dbatl_h,
798 0x00000000);
799 spr_register(env, SPR_DBAT6U, "DBAT6U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat_h, &spr_write_dbatu_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT6L, "DBAT6L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatl_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT7U, "DBAT7U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatu_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT7L, "DBAT7L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatl_h,
814 0x00000000);
815 env->nb_BATs += 4;
816 #endif
817 }
818
819 /* Generic PowerPC time base */
820 static void gen_tbl (CPUPPCState *env)
821 {
822 spr_register(env, SPR_VTBL, "TBL",
823 &spr_read_tbl, SPR_NOACCESS,
824 &spr_read_tbl, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_TBL, "TBL",
827 &spr_read_tbl, SPR_NOACCESS,
828 &spr_read_tbl, &spr_write_tbl,
829 0x00000000);
830 spr_register(env, SPR_VTBU, "TBU",
831 &spr_read_tbu, SPR_NOACCESS,
832 &spr_read_tbu, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_TBU, "TBU",
835 &spr_read_tbu, SPR_NOACCESS,
836 &spr_read_tbu, &spr_write_tbu,
837 0x00000000);
838 }
839
840 /* Softare table search registers */
841 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
842 {
843 #if !defined(CONFIG_USER_ONLY)
844 env->nb_tlb = nb_tlbs;
845 env->nb_ways = nb_ways;
846 env->id_tlbs = 1;
847 spr_register(env, SPR_DMISS, "DMISS",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, SPR_NOACCESS,
850 0x00000000);
851 spr_register(env, SPR_DCMP, "DCMP",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_generic, SPR_NOACCESS,
854 0x00000000);
855 spr_register(env, SPR_HASH1, "HASH1",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, SPR_NOACCESS,
858 0x00000000);
859 spr_register(env, SPR_HASH2, "HASH2",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic, SPR_NOACCESS,
862 0x00000000);
863 spr_register(env, SPR_IMISS, "IMISS",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_ICMP, "ICMP",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, SPR_NOACCESS,
870 0x00000000);
871 spr_register(env, SPR_RPA, "RPA",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
874 0x00000000);
875 #endif
876 }
877
878 /* SPR common to MPC755 and G2 */
879 static void gen_spr_G2_755 (CPUPPCState *env)
880 {
881 /* SGPRs */
882 spr_register(env, SPR_SPRG4, "SPRG4",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 spr_register(env, SPR_SPRG5, "SPRG5",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, &spr_write_generic,
889 0x00000000);
890 spr_register(env, SPR_SPRG6, "SPRG6",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
894 spr_register(env, SPR_SPRG7, "SPRG7",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 }
899
900 /* SPR common to all 7xx PowerPC implementations */
901 static void gen_spr_7xx (CPUPPCState *env)
902 {
903 /* Breakpoints */
904 /* XXX : not implemented */
905 spr_register(env, SPR_DABR, "DABR",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 /* XXX : not implemented */
910 spr_register(env, SPR_IABR, "IABR",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* Cache management */
915 /* XXX : not implemented */
916 spr_register(env, SPR_ICTC, "ICTC",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
920 /* Performance monitors */
921 /* XXX : not implemented */
922 spr_register(env, SPR_MMCR0, "MMCR0",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 /* XXX : not implemented */
927 spr_register(env, SPR_MMCR1, "MMCR1",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
932 spr_register(env, SPR_PMC1, "PMC1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* XXX : not implemented */
937 spr_register(env, SPR_PMC2, "PMC2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_PMC3, "PMC3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* XXX : not implemented */
947 spr_register(env, SPR_PMC4, "PMC4",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951 /* XXX : not implemented */
952 spr_register(env, SPR_SIAR, "SIAR",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, SPR_NOACCESS,
955 0x00000000);
956 /* XXX : not implemented */
957 spr_register(env, SPR_UMMCR0, "UMMCR0",
958 &spr_read_ureg, SPR_NOACCESS,
959 &spr_read_ureg, SPR_NOACCESS,
960 0x00000000);
961 /* XXX : not implemented */
962 spr_register(env, SPR_UMMCR1, "UMMCR1",
963 &spr_read_ureg, SPR_NOACCESS,
964 &spr_read_ureg, SPR_NOACCESS,
965 0x00000000);
966 /* XXX : not implemented */
967 spr_register(env, SPR_UPMC1, "UPMC1",
968 &spr_read_ureg, SPR_NOACCESS,
969 &spr_read_ureg, SPR_NOACCESS,
970 0x00000000);
971 /* XXX : not implemented */
972 spr_register(env, SPR_UPMC2, "UPMC2",
973 &spr_read_ureg, SPR_NOACCESS,
974 &spr_read_ureg, SPR_NOACCESS,
975 0x00000000);
976 /* XXX : not implemented */
977 spr_register(env, SPR_UPMC3, "UPMC3",
978 &spr_read_ureg, SPR_NOACCESS,
979 &spr_read_ureg, SPR_NOACCESS,
980 0x00000000);
981 /* XXX : not implemented */
982 spr_register(env, SPR_UPMC4, "UPMC4",
983 &spr_read_ureg, SPR_NOACCESS,
984 &spr_read_ureg, SPR_NOACCESS,
985 0x00000000);
986 /* XXX : not implemented */
987 spr_register(env, SPR_USIAR, "USIAR",
988 &spr_read_ureg, SPR_NOACCESS,
989 &spr_read_ureg, SPR_NOACCESS,
990 0x00000000);
991 /* External access control */
992 /* XXX : not implemented */
993 spr_register(env, SPR_EAR, "EAR",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
997 }
998
999 static void gen_spr_thrm (CPUPPCState *env)
1000 {
1001 /* Thermal management */
1002 /* XXX : not implemented */
1003 spr_register(env, SPR_THRM1, "THRM1",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 /* XXX : not implemented */
1008 spr_register(env, SPR_THRM2, "THRM2",
1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
1012 /* XXX : not implemented */
1013 spr_register(env, SPR_THRM3, "THRM3",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
1017 }
1018
1019 /* SPR specific to PowerPC 604 implementation */
1020 static void gen_spr_604 (CPUPPCState *env)
1021 {
1022 /* Processor identification */
1023 spr_register(env, SPR_PIR, "PIR",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_pir,
1026 0x00000000);
1027 /* Breakpoints */
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_IABR, "IABR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_DABR, "DABR",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* Performance counters */
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_MMCR0, "MMCR0",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_PMC1, "PMC1",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_PMC2, "PMC2",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_SIAR, "SIAR",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, SPR_NOACCESS,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_SDA, "SDA",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, SPR_NOACCESS,
1063 0x00000000);
1064 /* External access control */
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_EAR, "EAR",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070 }
1071
1072 /* SPR specific to PowerPC 603 implementation */
1073 static void gen_spr_603 (CPUPPCState *env)
1074 {
1075 /* External access control */
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_EAR, "EAR",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081 }
1082
1083 /* SPR specific to PowerPC G2 implementation */
1084 static void gen_spr_G2 (CPUPPCState *env)
1085 {
1086 /* Memory base address */
1087 /* MBAR */
1088 /* XXX : not implemented */
1089 spr_register(env, SPR_MBAR, "MBAR",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093 /* Exception processing */
1094 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_generic,
1097 0x00000000);
1098 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* Breakpoints */
1103 /* XXX : not implemented */
1104 spr_register(env, SPR_DABR, "DABR",
1105 SPR_NOACCESS, SPR_NOACCESS,
1106 &spr_read_generic, &spr_write_generic,
1107 0x00000000);
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_DABR2, "DABR2",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register(env, SPR_IABR, "IABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 /* XXX : not implemented */
1119 spr_register(env, SPR_IABR2, "IABR2",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_generic, &spr_write_generic,
1122 0x00000000);
1123 /* XXX : not implemented */
1124 spr_register(env, SPR_IBCR, "IBCR",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 /* XXX : not implemented */
1129 spr_register(env, SPR_DBCR, "DBCR",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, &spr_write_generic,
1132 0x00000000);
1133 }
1134
1135 /* SPR specific to PowerPC 602 implementation */
1136 static void gen_spr_602 (CPUPPCState *env)
1137 {
1138 /* ESA registers */
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_SER, "SER",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1143 0x00000000);
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_SEBR, "SEBR",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_generic,
1148 0x00000000);
1149 /* XXX : not implemented */
1150 spr_register(env, SPR_ESASRR, "ESASRR",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_generic,
1153 0x00000000);
1154 /* Floating point status */
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_SP, "SP",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_LT, "LT",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 /* Watchdog timer */
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_TCR, "TCR",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* Interrupt base */
1172 spr_register(env, SPR_IBR, "IBR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* XXX : not implemented */
1177 spr_register(env, SPR_IABR, "IABR",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
1181 }
1182
1183 /* SPR specific to PowerPC 601 implementation */
1184 static void gen_spr_601 (CPUPPCState *env)
1185 {
1186 /* Multiplication/division register */
1187 /* MQ */
1188 spr_register(env, SPR_MQ, "MQ",
1189 &spr_read_generic, &spr_write_generic,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* RTC registers */
1193 spr_register(env, SPR_601_RTCU, "RTCU",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 SPR_NOACCESS, &spr_write_601_rtcu,
1196 0x00000000);
1197 spr_register(env, SPR_601_VRTCU, "RTCU",
1198 &spr_read_601_rtcu, SPR_NOACCESS,
1199 &spr_read_601_rtcu, SPR_NOACCESS,
1200 0x00000000);
1201 spr_register(env, SPR_601_RTCL, "RTCL",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 SPR_NOACCESS, &spr_write_601_rtcl,
1204 0x00000000);
1205 spr_register(env, SPR_601_VRTCL, "RTCL",
1206 &spr_read_601_rtcl, SPR_NOACCESS,
1207 &spr_read_601_rtcl, SPR_NOACCESS,
1208 0x00000000);
1209 /* Timer */
1210 #if 0 /* ? */
1211 spr_register(env, SPR_601_UDECR, "UDECR",
1212 &spr_read_decr, SPR_NOACCESS,
1213 &spr_read_decr, SPR_NOACCESS,
1214 0x00000000);
1215 #endif
1216 /* External access control */
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_EAR, "EAR",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* Memory management */
1223 #if !defined(CONFIG_USER_ONLY)
1224 spr_register(env, SPR_IBAT0U, "IBAT0U",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_601_ubat, &spr_write_601_ubatu,
1227 0x00000000);
1228 spr_register(env, SPR_IBAT0L, "IBAT0L",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_601_ubat, &spr_write_601_ubatl,
1231 0x00000000);
1232 spr_register(env, SPR_IBAT1U, "IBAT1U",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_601_ubat, &spr_write_601_ubatu,
1235 0x00000000);
1236 spr_register(env, SPR_IBAT1L, "IBAT1L",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_601_ubat, &spr_write_601_ubatl,
1239 0x00000000);
1240 spr_register(env, SPR_IBAT2U, "IBAT2U",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_601_ubat, &spr_write_601_ubatu,
1243 0x00000000);
1244 spr_register(env, SPR_IBAT2L, "IBAT2L",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_601_ubat, &spr_write_601_ubatl,
1247 0x00000000);
1248 spr_register(env, SPR_IBAT3U, "IBAT3U",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_601_ubat, &spr_write_601_ubatu,
1251 0x00000000);
1252 spr_register(env, SPR_IBAT3L, "IBAT3L",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_601_ubat, &spr_write_601_ubatl,
1255 0x00000000);
1256 env->nb_BATs = 4;
1257 #endif
1258 }
1259
1260 static void gen_spr_74xx (CPUPPCState *env)
1261 {
1262 /* Processor identification */
1263 spr_register(env, SPR_PIR, "PIR",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_pir,
1266 0x00000000);
1267 /* XXX : not implemented */
1268 spr_register(env, SPR_MMCR2, "MMCR2",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 0x00000000);
1272 /* XXX : not implemented */
1273 spr_register(env, SPR_UMMCR2, "UMMCR2",
1274 &spr_read_ureg, SPR_NOACCESS,
1275 &spr_read_ureg, SPR_NOACCESS,
1276 0x00000000);
1277 /* XXX: not implemented */
1278 spr_register(env, SPR_BAMR, "BAMR",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
1282 /* XXX : not implemented */
1283 spr_register(env, SPR_MSSCR0, "MSSCR0",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287 /* Hardware implementation registers */
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_HID0, "HID0",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_HID1, "HID1",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* Altivec */
1299 spr_register(env, SPR_VRSAVE, "VRSAVE",
1300 &spr_read_generic, &spr_write_generic,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_L2CR, "L2CR",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* Not strictly an SPR */
1309 vscr_init(env, 0x00010000);
1310 }
1311
1312 static void gen_l3_ctrl (CPUPPCState *env)
1313 {
1314 /* L3CR */
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_L3CR, "L3CR",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* L3ITCR0 */
1321 /* XXX : not implemented */
1322 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
1326 /* L3PM */
1327 /* XXX : not implemented */
1328 spr_register(env, SPR_L3PM, "L3PM",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332 }
1333
1334 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1335 {
1336 #if !defined(CONFIG_USER_ONLY)
1337 env->nb_tlb = nb_tlbs;
1338 env->nb_ways = nb_ways;
1339 env->id_tlbs = 1;
1340 /* XXX : not implemented */
1341 spr_register(env, SPR_PTEHI, "PTEHI",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_PTELO, "PTELO",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_TLBMISS, "TLBMISS",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 #endif
1356 }
1357
1358 #if !defined(CONFIG_USER_ONLY)
1359 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1360 {
1361 TCGv t0 = tcg_temp_new();
1362
1363 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1364 gen_store_spr(sprn, t0);
1365 tcg_temp_free(t0);
1366 }
1367
1368 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1369 {
1370 TCGv t0 = tcg_const_i32(sprn);
1371 gen_helper_booke206_tlbflush(t0);
1372 tcg_temp_free(t0);
1373 }
1374
1375 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1376 {
1377 TCGv t0 = tcg_const_i32(sprn);
1378 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1379 tcg_temp_free(t0);
1380 }
1381 #endif
1382
1383 static void gen_spr_usprgh (CPUPPCState *env)
1384 {
1385 spr_register(env, SPR_USPRG4, "USPRG4",
1386 &spr_read_ureg, SPR_NOACCESS,
1387 &spr_read_ureg, SPR_NOACCESS,
1388 0x00000000);
1389 spr_register(env, SPR_USPRG5, "USPRG5",
1390 &spr_read_ureg, SPR_NOACCESS,
1391 &spr_read_ureg, SPR_NOACCESS,
1392 0x00000000);
1393 spr_register(env, SPR_USPRG6, "USPRG6",
1394 &spr_read_ureg, SPR_NOACCESS,
1395 &spr_read_ureg, SPR_NOACCESS,
1396 0x00000000);
1397 spr_register(env, SPR_USPRG7, "USPRG7",
1398 &spr_read_ureg, SPR_NOACCESS,
1399 &spr_read_ureg, SPR_NOACCESS,
1400 0x00000000);
1401 }
1402
1403 /* PowerPC BookE SPR */
1404 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1405 {
1406 const char *ivor_names[64] = {
1407 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1408 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1409 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1410 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1411 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1412 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1413 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1414 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1415 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1416 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1417 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1418 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1419 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1420 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1421 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1422 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1423 };
1424 #define SPR_BOOKE_IVORxx (-1)
1425 int ivor_sprn[64] = {
1426 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1427 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1428 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1429 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1430 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1431 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1432 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1435 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1437 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1438 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1439 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 };
1443 int i;
1444
1445 /* Interrupt processing */
1446 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_generic,
1449 0x00000000);
1450 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1453 0x00000000);
1454 /* Debug */
1455 /* XXX : not implemented */
1456 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460 /* XXX : not implemented */
1461 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465 /* XXX : not implemented */
1466 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 /* XXX : not implemented */
1471 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* XXX : not implemented */
1476 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 /* XXX : not implemented */
1481 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_clear,
1494 0x00000000);
1495 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 spr_register(env, SPR_BOOKE_ESR, "ESR",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_excp_prefix,
1506 0x00000000);
1507 /* Exception vectors */
1508 for (i = 0; i < 64; i++) {
1509 if (ivor_mask & (1ULL << i)) {
1510 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1511 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1512 exit(1);
1513 }
1514 spr_register(env, ivor_sprn[i], ivor_names[i],
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_excp_vector,
1517 0x00000000);
1518 }
1519 }
1520 spr_register(env, SPR_BOOKE_PID, "PID",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_booke_pid,
1523 0x00000000);
1524 spr_register(env, SPR_BOOKE_TCR, "TCR",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_booke_tcr,
1527 0x00000000);
1528 spr_register(env, SPR_BOOKE_TSR, "TSR",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_booke_tsr,
1531 0x00000000);
1532 /* Timer */
1533 spr_register(env, SPR_DECR, "DECR",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_decr, &spr_write_decr,
1536 0x00000000);
1537 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 SPR_NOACCESS, &spr_write_generic,
1540 0x00000000);
1541 /* SPRGs */
1542 spr_register(env, SPR_USPRG0, "USPRG0",
1543 &spr_read_generic, &spr_write_generic,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
1546 spr_register(env, SPR_SPRG4, "SPRG4",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 spr_register(env, SPR_SPRG5, "SPRG5",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 spr_register(env, SPR_SPRG6, "SPRG6",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 spr_register(env, SPR_SPRG7, "SPRG7",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 }
1563
1564 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1565 uint32_t maxsize, uint32_t flags,
1566 uint32_t nentries)
1567 {
1568 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1569 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1570 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1571 flags | nentries;
1572 }
1573
1574 /* BookE 2.06 storage control registers */
1575 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1576 uint32_t *tlbncfg)
1577 {
1578 #if !defined(CONFIG_USER_ONLY)
1579 const char *mas_names[8] = {
1580 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1581 };
1582 int mas_sprn[8] = {
1583 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1584 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1585 };
1586 int i;
1587
1588 /* TLB assist registers */
1589 /* XXX : not implemented */
1590 for (i = 0; i < 8; i++) {
1591 if (mas_mask & (1 << i)) {
1592 spr_register(env, mas_sprn[i], mas_names[i],
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000);
1596 }
1597 }
1598 if (env->nb_pids > 1) {
1599 /* XXX : not implemented */
1600 spr_register(env, SPR_BOOKE_PID1, "PID1",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_booke_pid,
1603 0x00000000);
1604 }
1605 if (env->nb_pids > 2) {
1606 /* XXX : not implemented */
1607 spr_register(env, SPR_BOOKE_PID2, "PID2",
1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, &spr_write_booke_pid,
1610 0x00000000);
1611 }
1612 /* XXX : not implemented */
1613 spr_register(env, SPR_MMUCFG, "MMUCFG",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, SPR_NOACCESS,
1616 0x00000000); /* TOFIX */
1617 switch (env->nb_ways) {
1618 case 4:
1619 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, SPR_NOACCESS,
1622 tlbncfg[3]);
1623 /* Fallthru */
1624 case 3:
1625 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, SPR_NOACCESS,
1628 tlbncfg[2]);
1629 /* Fallthru */
1630 case 2:
1631 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, SPR_NOACCESS,
1634 tlbncfg[1]);
1635 /* Fallthru */
1636 case 1:
1637 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, SPR_NOACCESS,
1640 tlbncfg[0]);
1641 /* Fallthru */
1642 case 0:
1643 default:
1644 break;
1645 }
1646 #endif
1647
1648 gen_spr_usprgh(env);
1649 }
1650
1651 /* SPR specific to PowerPC 440 implementation */
1652 static void gen_spr_440 (CPUPPCState *env)
1653 {
1654 /* Cache control */
1655 /* XXX : not implemented */
1656 spr_register(env, SPR_440_DNV0, "DNV0",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_generic,
1659 0x00000000);
1660 /* XXX : not implemented */
1661 spr_register(env, SPR_440_DNV1, "DNV1",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665 /* XXX : not implemented */
1666 spr_register(env, SPR_440_DNV2, "DNV2",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1669 0x00000000);
1670 /* XXX : not implemented */
1671 spr_register(env, SPR_440_DNV3, "DNV3",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 /* XXX : not implemented */
1676 spr_register(env, SPR_440_DTV0, "DTV0",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_440_DTV1, "DTV1",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 /* XXX : not implemented */
1686 spr_register(env, SPR_440_DTV2, "DTV2",
1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
1690 /* XXX : not implemented */
1691 spr_register(env, SPR_440_DTV3, "DTV3",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_440_DVLIM, "DVLIM",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_440_INV0, "INV0",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 /* XXX : not implemented */
1706 spr_register(env, SPR_440_INV1, "INV1",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 /* XXX : not implemented */
1711 spr_register(env, SPR_440_INV2, "INV2",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, &spr_write_generic,
1714 0x00000000);
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_440_INV3, "INV3",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1719 0x00000000);
1720 /* XXX : not implemented */
1721 spr_register(env, SPR_440_ITV0, "ITV0",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1724 0x00000000);
1725 /* XXX : not implemented */
1726 spr_register(env, SPR_440_ITV1, "ITV1",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
1730 /* XXX : not implemented */
1731 spr_register(env, SPR_440_ITV2, "ITV2",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 /* XXX : not implemented */
1736 spr_register(env, SPR_440_ITV3, "ITV3",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 /* XXX : not implemented */
1741 spr_register(env, SPR_440_IVLIM, "IVLIM",
1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
1745 /* Cache debug */
1746 /* XXX : not implemented */
1747 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_generic, SPR_NOACCESS,
1750 0x00000000);
1751 /* XXX : not implemented */
1752 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, SPR_NOACCESS,
1755 0x00000000);
1756 /* XXX : not implemented */
1757 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, SPR_NOACCESS,
1760 0x00000000);
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, SPR_NOACCESS,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, SPR_NOACCESS,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_440_DBDR, "DBDR",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* Processor control */
1777 spr_register(env, SPR_4xx_CCR0, "CCR0",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, SPR_NOACCESS,
1784 0x00000000);
1785 /* Storage control */
1786 spr_register(env, SPR_440_MMUCR, "MMUCR",
1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
1790 }
1791
1792 /* SPR shared between PowerPC 40x implementations */
1793 static void gen_spr_40x (CPUPPCState *env)
1794 {
1795 /* Cache */
1796 /* not emulated, as Qemu do not emulate caches */
1797 spr_register(env, SPR_40x_DCCR, "DCCR",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 /* not emulated, as Qemu do not emulate caches */
1802 spr_register(env, SPR_40x_ICCR, "ICCR",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* not emulated, as Qemu do not emulate caches */
1807 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, SPR_NOACCESS,
1810 0x00000000);
1811 /* Exception */
1812 spr_register(env, SPR_40x_DEAR, "DEAR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 spr_register(env, SPR_40x_ESR, "ESR",
1817 SPR_NOACCESS, SPR_NOACCESS,
1818 &spr_read_generic, &spr_write_generic,
1819 0x00000000);
1820 spr_register(env, SPR_40x_EVPR, "EVPR",
1821 SPR_NOACCESS, SPR_NOACCESS,
1822 &spr_read_generic, &spr_write_excp_prefix,
1823 0x00000000);
1824 spr_register(env, SPR_40x_SRR2, "SRR2",
1825 &spr_read_generic, &spr_write_generic,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 spr_register(env, SPR_40x_SRR3, "SRR3",
1829 &spr_read_generic, &spr_write_generic,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 /* Timers */
1833 spr_register(env, SPR_40x_PIT, "PIT",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_40x_pit, &spr_write_40x_pit,
1836 0x00000000);
1837 spr_register(env, SPR_40x_TCR, "TCR",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_booke_tcr,
1840 0x00000000);
1841 spr_register(env, SPR_40x_TSR, "TSR",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_booke_tsr,
1844 0x00000000);
1845 }
1846
1847 /* SPR specific to PowerPC 405 implementation */
1848 static void gen_spr_405 (CPUPPCState *env)
1849 {
1850 /* MMU */
1851 spr_register(env, SPR_40x_PID, "PID",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
1855 spr_register(env, SPR_4xx_CCR0, "CCR0",
1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, &spr_write_generic,
1858 0x00700000);
1859 /* Debug interface */
1860 /* XXX : not implemented */
1861 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_generic, &spr_write_40x_dbcr0,
1864 0x00000000);
1865 /* XXX : not implemented */
1866 spr_register(env, SPR_405_DBCR1, "DBCR1",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 /* XXX : not implemented */
1871 spr_register(env, SPR_40x_DBSR, "DBSR",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_clear,
1874 /* Last reset was system reset */
1875 0x00000300);
1876 /* XXX : not implemented */
1877 spr_register(env, SPR_40x_DAC1, "DAC1",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
1881 spr_register(env, SPR_40x_DAC2, "DAC2",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_405_DVC1, "DVC1",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 /* XXX : not implemented */
1891 spr_register(env, SPR_405_DVC2, "DVC2",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* XXX : not implemented */
1896 spr_register(env, SPR_40x_IAC1, "IAC1",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900 spr_register(env, SPR_40x_IAC2, "IAC2",
1901 SPR_NOACCESS, SPR_NOACCESS,
1902 &spr_read_generic, &spr_write_generic,
1903 0x00000000);
1904 /* XXX : not implemented */
1905 spr_register(env, SPR_405_IAC3, "IAC3",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 /* XXX : not implemented */
1910 spr_register(env, SPR_405_IAC4, "IAC4",
1911 SPR_NOACCESS, SPR_NOACCESS,
1912 &spr_read_generic, &spr_write_generic,
1913 0x00000000);
1914 /* Storage control */
1915 /* XXX: TODO: not implemented */
1916 spr_register(env, SPR_405_SLER, "SLER",
1917 SPR_NOACCESS, SPR_NOACCESS,
1918 &spr_read_generic, &spr_write_40x_sler,
1919 0x00000000);
1920 spr_register(env, SPR_40x_ZPR, "ZPR",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* XXX : not implemented */
1925 spr_register(env, SPR_405_SU0R, "SU0R",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 /* SPRG */
1930 spr_register(env, SPR_USPRG0, "USPRG0",
1931 &spr_read_ureg, SPR_NOACCESS,
1932 &spr_read_ureg, SPR_NOACCESS,
1933 0x00000000);
1934 spr_register(env, SPR_SPRG4, "SPRG4",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_generic, &spr_write_generic,
1937 0x00000000);
1938 spr_register(env, SPR_SPRG5, "SPRG5",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 spr_register(env, SPR_SPRG6, "SPRG6",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 spr_register(env, SPR_SPRG7, "SPRG7",
1947 SPR_NOACCESS, SPR_NOACCESS,
1948 spr_read_generic, &spr_write_generic,
1949 0x00000000);
1950 gen_spr_usprgh(env);
1951 }
1952
1953 /* SPR shared between PowerPC 401 & 403 implementations */
1954 static void gen_spr_401_403 (CPUPPCState *env)
1955 {
1956 /* Time base */
1957 spr_register(env, SPR_403_VTBL, "TBL",
1958 &spr_read_tbl, SPR_NOACCESS,
1959 &spr_read_tbl, SPR_NOACCESS,
1960 0x00000000);
1961 spr_register(env, SPR_403_TBL, "TBL",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 SPR_NOACCESS, &spr_write_tbl,
1964 0x00000000);
1965 spr_register(env, SPR_403_VTBU, "TBU",
1966 &spr_read_tbu, SPR_NOACCESS,
1967 &spr_read_tbu, SPR_NOACCESS,
1968 0x00000000);
1969 spr_register(env, SPR_403_TBU, "TBU",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 SPR_NOACCESS, &spr_write_tbu,
1972 0x00000000);
1973 /* Debug */
1974 /* not emulated, as Qemu do not emulate caches */
1975 spr_register(env, SPR_403_CDBCR, "CDBCR",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 }
1980
1981 /* SPR specific to PowerPC 401 implementation */
1982 static void gen_spr_401 (CPUPPCState *env)
1983 {
1984 /* Debug interface */
1985 /* XXX : not implemented */
1986 spr_register(env, SPR_40x_DBCR0, "DBCR",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_40x_dbcr0,
1989 0x00000000);
1990 /* XXX : not implemented */
1991 spr_register(env, SPR_40x_DBSR, "DBSR",
1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_generic, &spr_write_clear,
1994 /* Last reset was system reset */
1995 0x00000300);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_40x_DAC1, "DAC",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* XXX : not implemented */
2002 spr_register(env, SPR_40x_IAC1, "IAC",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 /* Storage control */
2007 /* XXX: TODO: not implemented */
2008 spr_register(env, SPR_405_SLER, "SLER",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_40x_sler,
2011 0x00000000);
2012 /* not emulated, as Qemu never does speculative access */
2013 spr_register(env, SPR_40x_SGR, "SGR",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0xFFFFFFFF);
2017 /* not emulated, as Qemu do not emulate caches */
2018 spr_register(env, SPR_40x_DCWR, "DCWR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2022 }
2023
2024 static void gen_spr_401x2 (CPUPPCState *env)
2025 {
2026 gen_spr_401(env);
2027 spr_register(env, SPR_40x_PID, "PID",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 spr_register(env, SPR_40x_ZPR, "ZPR",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, &spr_write_generic,
2034 0x00000000);
2035 }
2036
2037 /* SPR specific to PowerPC 403 implementation */
2038 static void gen_spr_403 (CPUPPCState *env)
2039 {
2040 /* Debug interface */
2041 /* XXX : not implemented */
2042 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_40x_dbcr0,
2045 0x00000000);
2046 /* XXX : not implemented */
2047 spr_register(env, SPR_40x_DBSR, "DBSR",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_generic, &spr_write_clear,
2050 /* Last reset was system reset */
2051 0x00000300);
2052 /* XXX : not implemented */
2053 spr_register(env, SPR_40x_DAC1, "DAC1",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057 /* XXX : not implemented */
2058 spr_register(env, SPR_40x_DAC2, "DAC2",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_40x_IAC1, "IAC1",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_generic,
2066 0x00000000);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_40x_IAC2, "IAC2",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 }
2073
2074 static void gen_spr_403_real (CPUPPCState *env)
2075 {
2076 spr_register(env, SPR_403_PBL1, "PBL1",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_403_pbr, &spr_write_403_pbr,
2079 0x00000000);
2080 spr_register(env, SPR_403_PBU1, "PBU1",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_403_pbr, &spr_write_403_pbr,
2083 0x00000000);
2084 spr_register(env, SPR_403_PBL2, "PBL2",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_403_pbr, &spr_write_403_pbr,
2087 0x00000000);
2088 spr_register(env, SPR_403_PBU2, "PBU2",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_403_pbr, &spr_write_403_pbr,
2091 0x00000000);
2092 }
2093
2094 static void gen_spr_403_mmu (CPUPPCState *env)
2095 {
2096 /* MMU */
2097 spr_register(env, SPR_40x_PID, "PID",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101 spr_register(env, SPR_40x_ZPR, "ZPR",
2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_generic, &spr_write_generic,
2104 0x00000000);
2105 }
2106
2107 /* SPR specific to PowerPC compression coprocessor extension */
2108 static void gen_spr_compress (CPUPPCState *env)
2109 {
2110 /* XXX : not implemented */
2111 spr_register(env, SPR_401_SKR, "SKR",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115 }
2116
2117 #if defined (TARGET_PPC64)
2118 /* SPR specific to PowerPC 620 */
2119 static void gen_spr_620 (CPUPPCState *env)
2120 {
2121 /* Processor identification */
2122 spr_register(env, SPR_PIR, "PIR",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_pir,
2125 0x00000000);
2126 spr_register(env, SPR_ASR, "ASR",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_asr, &spr_write_asr,
2129 0x00000000);
2130 /* Breakpoints */
2131 /* XXX : not implemented */
2132 spr_register(env, SPR_IABR, "IABR",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 /* XXX : not implemented */
2137 spr_register(env, SPR_DABR, "DABR",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_generic,
2140 0x00000000);
2141 /* XXX : not implemented */
2142 spr_register(env, SPR_SIAR, "SIAR",
2143 SPR_NOACCESS, SPR_NOACCESS,
2144 &spr_read_generic, SPR_NOACCESS,
2145 0x00000000);
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_SDA, "SDA",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, SPR_NOACCESS,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_620_PMC1R, "PMC1",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, SPR_NOACCESS,
2155 0x00000000);
2156 spr_register(env, SPR_620_PMC1W, "PMC1",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 SPR_NOACCESS, &spr_write_generic,
2159 0x00000000);
2160 /* XXX : not implemented */
2161 spr_register(env, SPR_620_PMC2R, "PMC2",
2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, SPR_NOACCESS,
2164 0x00000000);
2165 spr_register(env, SPR_620_PMC2W, "PMC2",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 SPR_NOACCESS, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, SPR_NOACCESS,
2173 0x00000000);
2174 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 SPR_NOACCESS, &spr_write_generic,
2177 0x00000000);
2178 /* External access control */
2179 /* XXX : not implemented */
2180 spr_register(env, SPR_EAR, "EAR",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
2184 #if 0 // XXX: check this
2185 /* XXX : not implemented */
2186 spr_register(env, SPR_620_PMR0, "PMR0",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 &spr_read_generic, &spr_write_generic,
2189 0x00000000);
2190 /* XXX : not implemented */
2191 spr_register(env, SPR_620_PMR1, "PMR1",
2192 SPR_NOACCESS, SPR_NOACCESS,
2193 &spr_read_generic, &spr_write_generic,
2194 0x00000000);
2195 /* XXX : not implemented */
2196 spr_register(env, SPR_620_PMR2, "PMR2",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 0x00000000);
2200 /* XXX : not implemented */
2201 spr_register(env, SPR_620_PMR3, "PMR3",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
2205 /* XXX : not implemented */
2206 spr_register(env, SPR_620_PMR4, "PMR4",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 /* XXX : not implemented */
2211 spr_register(env, SPR_620_PMR5, "PMR5",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215 /* XXX : not implemented */
2216 spr_register(env, SPR_620_PMR6, "PMR6",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220 /* XXX : not implemented */
2221 spr_register(env, SPR_620_PMR7, "PMR7",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 0x00000000);
2225 /* XXX : not implemented */
2226 spr_register(env, SPR_620_PMR8, "PMR8",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_generic,
2229 0x00000000);
2230 /* XXX : not implemented */
2231 spr_register(env, SPR_620_PMR9, "PMR9",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0x00000000);
2235 /* XXX : not implemented */
2236 spr_register(env, SPR_620_PMRA, "PMR10",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_620_PMRB, "PMR11",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_620_PMRC, "PMR12",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_620_PMRD, "PMR13",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 /* XXX : not implemented */
2256 spr_register(env, SPR_620_PMRE, "PMR14",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_620_PMRF, "PMR15",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 #endif
2266 /* XXX : not implemented */
2267 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_generic, &spr_write_generic,
2270 0x00000000);
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_620_L2CR, "L2CR",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_620_L2SR, "L2SR",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281 }
2282 #endif /* defined (TARGET_PPC64) */
2283
2284 static void gen_spr_5xx_8xx (CPUPPCState *env)
2285 {
2286 /* Exception processing */
2287 spr_register(env, SPR_DSISR, "DSISR",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 spr_register(env, SPR_DAR, "DAR",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 /* Timer */
2296 spr_register(env, SPR_DECR, "DECR",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_decr, &spr_write_decr,
2299 0x00000000);
2300 /* XXX : not implemented */
2301 spr_register(env, SPR_MPC_EIE, "EIE",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 /* XXX : not implemented */
2306 spr_register(env, SPR_MPC_EID, "EID",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* XXX : not implemented */
2311 spr_register(env, SPR_MPC_NRI, "NRI",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_generic, &spr_write_generic,
2314 0x00000000);
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_MPC_CMPA, "CMPA",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_generic,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_MPC_CMPB, "CMPB",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325 /* XXX : not implemented */
2326 spr_register(env, SPR_MPC_CMPC, "CMPC",
2327 SPR_NOACCESS, SPR_NOACCESS,
2328 &spr_read_generic, &spr_write_generic,
2329 0x00000000);
2330 /* XXX : not implemented */
2331 spr_register(env, SPR_MPC_CMPD, "CMPD",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_generic, &spr_write_generic,
2334 0x00000000);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_MPC_ECR, "ECR",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_MPC_DER, "DER",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_MPC_CMPE, "CMPE",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_MPC_CMPF, "CMPF",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_MPC_CMPG, "CMPG",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_MPC_CMPH, "CMPH",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_BAR, "BAR",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_DPDR, "DPDR",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_IMMR, "IMMR",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 }
2401
2402 static void gen_spr_5xx (CPUPPCState *env)
2403 {
2404 /* XXX : not implemented */
2405 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2406 SPR_NOACCESS, SPR_NOACCESS,
2407 &spr_read_generic, &spr_write_generic,
2408 0x00000000);
2409 /* XXX : not implemented */
2410 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_generic, &spr_write_generic,
2413 0x00000000);
2414 /* XXX : not implemented */
2415 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2416 SPR_NOACCESS, SPR_NOACCESS,
2417 &spr_read_generic, &spr_write_generic,
2418 0x00000000);
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* XXX : not implemented */
2435 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_generic, &spr_write_generic,
2438 0x00000000);
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 }
2510
2511 static void gen_spr_8xx (CPUPPCState *env)
2512 {
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 /* XXX : not implemented */
2519 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2520 SPR_NOACCESS, SPR_NOACCESS,
2521 &spr_read_generic, &spr_write_generic,
2522 0x00000000);
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 }
2639
2640 // XXX: TODO
2641 /*
2642 * AMR => SPR 29 (Power 2.04)
2643 * CTRL => SPR 136 (Power 2.04)
2644 * CTRL => SPR 152 (Power 2.04)
2645 * SCOMC => SPR 276 (64 bits ?)
2646 * SCOMD => SPR 277 (64 bits ?)
2647 * TBU40 => SPR 286 (Power 2.04 hypv)
2648 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2649 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2650 * HDSISR => SPR 306 (Power 2.04 hypv)
2651 * HDAR => SPR 307 (Power 2.04 hypv)
2652 * PURR => SPR 309 (Power 2.04 hypv)
2653 * HDEC => SPR 310 (Power 2.04 hypv)
2654 * HIOR => SPR 311 (hypv)
2655 * RMOR => SPR 312 (970)
2656 * HRMOR => SPR 313 (Power 2.04 hypv)
2657 * HSRR0 => SPR 314 (Power 2.04 hypv)
2658 * HSRR1 => SPR 315 (Power 2.04 hypv)
2659 * LPCR => SPR 316 (970)
2660 * LPIDR => SPR 317 (970)
2661 * EPR => SPR 702 (Power 2.04 emb)
2662 * perf => 768-783 (Power 2.04)
2663 * perf => 784-799 (Power 2.04)
2664 * PPR => SPR 896 (Power 2.04)
2665 * EPLC => SPR 947 (Power 2.04 emb)
2666 * EPSC => SPR 948 (Power 2.04 emb)
2667 * DABRX => 1015 (Power 2.04 hypv)
2668 * FPECR => SPR 1022 (?)
2669 * ... and more (thermal management, performance counters, ...)
2670 */
2671
2672 /*****************************************************************************/
2673 /* Exception vectors models */
2674 static void init_excp_4xx_real (CPUPPCState *env)
2675 {
2676 #if !defined(CONFIG_USER_ONLY)
2677 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2678 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2679 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2680 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2681 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2682 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2683 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2684 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2685 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2686 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2687 env->hreset_excp_prefix = 0x00000000UL;
2688 env->ivor_mask = 0x0000FFF0UL;
2689 env->ivpr_mask = 0xFFFF0000UL;
2690 /* Hardware reset vector */
2691 env->hreset_vector = 0xFFFFFFFCUL;
2692 #endif
2693 }
2694
2695 static void init_excp_4xx_softmmu (CPUPPCState *env)
2696 {
2697 #if !defined(CONFIG_USER_ONLY)
2698 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2699 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2700 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2701 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2702 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2703 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2704 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2705 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2706 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2707 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2708 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2709 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2710 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2711 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2712 env->hreset_excp_prefix = 0x00000000UL;
2713 env->ivor_mask = 0x0000FFF0UL;
2714 env->ivpr_mask = 0xFFFF0000UL;
2715 /* Hardware reset vector */
2716 env->hreset_vector = 0xFFFFFFFCUL;
2717 #endif
2718 }
2719
2720 static void init_excp_MPC5xx (CPUPPCState *env)
2721 {
2722 #if !defined(CONFIG_USER_ONLY)
2723 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2724 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2725 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2726 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2727 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2728 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2729 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2730 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2731 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2732 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2733 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2734 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2735 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2736 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2737 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2738 env->hreset_excp_prefix = 0x00000000UL;
2739 env->ivor_mask = 0x0000FFF0UL;
2740 env->ivpr_mask = 0xFFFF0000UL;
2741 /* Hardware reset vector */
2742 env->hreset_vector = 0xFFFFFFFCUL;
2743 #endif
2744 }
2745
2746 static void init_excp_MPC8xx (CPUPPCState *env)
2747 {
2748 #if !defined(CONFIG_USER_ONLY)
2749 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2750 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2751 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2752 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2753 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2754 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2755 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2756 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2757 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2758 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2759 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2760 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2761 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2762 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2763 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2764 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2765 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2766 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2767 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2768 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2769 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2770 env->hreset_excp_prefix = 0x00000000UL;
2771 env->ivor_mask = 0x0000FFF0UL;
2772 env->ivpr_mask = 0xFFFF0000UL;
2773 /* Hardware reset vector */
2774 env->hreset_vector = 0xFFFFFFFCUL;
2775 #endif
2776 }
2777
2778 static void init_excp_G2 (CPUPPCState *env)
2779 {
2780 #if !defined(CONFIG_USER_ONLY)
2781 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2782 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2783 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2784 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2785 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2786 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2787 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2788 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2789 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2790 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2791 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2792 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2793 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2794 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2795 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2796 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2797 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2798 env->hreset_excp_prefix = 0x00000000UL;
2799 /* Hardware reset vector */
2800 env->hreset_vector = 0xFFFFFFFCUL;
2801 #endif
2802 }
2803
2804 static void init_excp_e200 (CPUPPCState *env)
2805 {
2806 #if !defined(CONFIG_USER_ONLY)
2807 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2808 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2809 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2810 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2811 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2827 env->hreset_excp_prefix = 0x00000000UL;
2828 env->ivor_mask = 0x0000FFF7UL;
2829 env->ivpr_mask = 0xFFFF0000UL;
2830 /* Hardware reset vector */
2831 env->hreset_vector = 0xFFFFFFFCUL;
2832 #endif
2833 }
2834
2835 static void init_excp_BookE (CPUPPCState *env)
2836 {
2837 #if !defined(CONFIG_USER_ONLY)
2838 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2854 env->hreset_excp_prefix = 0x00000000UL;
2855 env->ivor_mask = 0x0000FFE0UL;
2856 env->ivpr_mask = 0xFFFF0000UL;
2857 /* Hardware reset vector */
2858 env->hreset_vector = 0xFFFFFFFCUL;
2859 #endif
2860 }
2861
2862 static void init_excp_601 (CPUPPCState *env)
2863 {
2864 #if !defined(CONFIG_USER_ONLY)
2865 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2866 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2867 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2868 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2869 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2870 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2871 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2872 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2873 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2874 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2875 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2876 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2877 env->hreset_excp_prefix = 0xFFF00000UL;
2878 /* Hardware reset vector */
2879 env->hreset_vector = 0x00000100UL;
2880 #endif
2881 }
2882
2883 static void init_excp_602 (CPUPPCState *env)
2884 {
2885 #if !defined(CONFIG_USER_ONLY)
2886 /* XXX: exception prefix has a special behavior on 602 */
2887 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2888 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2889 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2890 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2891 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2892 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2893 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2894 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2895 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2896 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2897 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2898 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2899 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2900 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2901 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2902 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2903 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2904 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2905 env->hreset_excp_prefix = 0xFFF00000UL;
2906 /* Hardware reset vector */
2907 env->hreset_vector = 0xFFFFFFFCUL;
2908 #endif
2909 }
2910
2911 static void init_excp_603 (CPUPPCState *env)
2912 {
2913 #if !defined(CONFIG_USER_ONLY)
2914 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2915 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2916 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2917 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2918 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2919 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2920 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2921 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2922 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2923 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2924 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2925 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2926 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2927 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2928 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2929 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2930 env->hreset_excp_prefix = 0x00000000UL;
2931 /* Hardware reset vector */
2932 env->hreset_vector = 0xFFFFFFFCUL;
2933 #endif
2934 }
2935
2936 static void init_excp_604 (CPUPPCState *env)
2937 {
2938 #if !defined(CONFIG_USER_ONLY)
2939 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2940 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2941 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2942 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2943 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2944 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2945 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2946 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2947 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2948 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2949 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2950 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2951 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2952 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2953 env->hreset_excp_prefix = 0xFFF00000UL;
2954 /* Hardware reset vector */
2955 env->hreset_vector = 0x00000100UL;
2956 #endif
2957 }
2958
2959 #if defined(TARGET_PPC64)
2960 static void init_excp_620 (CPUPPCState *env)
2961 {
2962 #if !defined(CONFIG_USER_ONLY)
2963 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2964 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2965 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2966 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2967 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2968 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2969 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2970 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2971 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2972 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2973 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2974 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2975 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2976 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2977 env->hreset_excp_prefix = 0xFFF00000UL;
2978 /* Hardware reset vector */
2979 env->hreset_vector = 0x0000000000000100ULL;
2980 #endif
2981 }
2982 #endif /* defined(TARGET_PPC64) */
2983
2984 static void init_excp_7x0 (CPUPPCState *env)
2985 {
2986 #if !defined(CONFIG_USER_ONLY)
2987 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2988 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2989 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2990 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2991 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2992 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2993 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2994 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2995 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2996 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2997 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2998 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2999 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3000 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3001 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3002 env->hreset_excp_prefix = 0x00000000UL;
3003 /* Hardware reset vector */
3004 env->hreset_vector = 0xFFFFFFFCUL;
3005 #endif
3006 }
3007
3008 static void init_excp_750cl (CPUPPCState *env)
3009 {
3010 #if !defined(CONFIG_USER_ONLY)
3011 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3012 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3013 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3014 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3015 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3016 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3017 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3018 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3019 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3020 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3021 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3022 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3024 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3025 env->hreset_excp_prefix = 0x00000000UL;
3026 /* Hardware reset vector */
3027 env->hreset_vector = 0xFFFFFFFCUL;
3028 #endif
3029 }
3030
3031 static void init_excp_750cx (CPUPPCState *env)
3032 {
3033 #if !defined(CONFIG_USER_ONLY)
3034 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3035 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3036 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3037 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3038 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3039 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3040 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3041 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3042 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3043 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3044 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3045 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3046 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3047 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3048 env->hreset_excp_prefix = 0x00000000UL;
3049 /* Hardware reset vector */
3050 env->hreset_vector = 0xFFFFFFFCUL;
3051 #endif
3052 }
3053
3054 /* XXX: Check if this is correct */
3055 static void init_excp_7x5 (CPUPPCState *env)
3056 {
3057 #if !defined(CONFIG_USER_ONLY)
3058 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3059 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3060 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3061 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3062 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3063 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3064 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3065 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3066 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3067 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3068 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3069 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3070 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3071 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3072 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3073 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3074 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3075 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3076 env->hreset_excp_prefix = 0x00000000UL;
3077 /* Hardware reset vector */
3078 env->hreset_vector = 0xFFFFFFFCUL;
3079 #endif
3080 }
3081
3082 static void init_excp_7400 (CPUPPCState *env)
3083 {
3084 #if !defined(CONFIG_USER_ONLY)
3085 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3086 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3087 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3088 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3089 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3090 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3091 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3092 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3093 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3094 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3095 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3096 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3097 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3098 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3099 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3100 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3101 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3102 env->hreset_excp_prefix = 0x00000000UL;
3103 /* Hardware reset vector */
3104 env->hreset_vector = 0xFFFFFFFCUL;
3105 #endif
3106 }
3107
3108 static void init_excp_7450 (CPUPPCState *env)
3109 {
3110 #if !defined(CONFIG_USER_ONLY)
3111 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3112 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3113 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3114 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
31