exec: Make ldl_*_phys input an AddressSpace
[qemu.git] / target-ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31
32 //#define PPC_DUMP_CPU
33 //#define PPC_DEBUG_SPR
34 //#define PPC_DUMP_SPR_ACCESSES
35
36 /* For user-mode emulation, we don't emulate any IRQ controller */
37 #if defined(CONFIG_USER_ONLY)
38 #define PPC_IRQ_INIT_FN(name) \
39 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
40 { \
41 }
42 #else
43 #define PPC_IRQ_INIT_FN(name) \
44 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
45 #endif
46
47 PPC_IRQ_INIT_FN(40x);
48 PPC_IRQ_INIT_FN(6xx);
49 PPC_IRQ_INIT_FN(970);
50 PPC_IRQ_INIT_FN(POWER7);
51 PPC_IRQ_INIT_FN(e500);
52
53 /* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
56 static void spr_load_dump_spr(int sprn)
57 {
58 #ifdef PPC_DUMP_SPR_ACCESSES
59 TCGv_i32 t0 = tcg_const_i32(sprn);
60 gen_helper_load_dump_spr(cpu_env, t0);
61 tcg_temp_free_i32(t0);
62 #endif
63 }
64
65 static void spr_read_generic (void *opaque, int gprn, int sprn)
66 {
67 gen_load_spr(cpu_gpr[gprn], sprn);
68 spr_load_dump_spr(sprn);
69 }
70
71 static void spr_store_dump_spr(int sprn)
72 {
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 TCGv_i32 t0 = tcg_const_i32(sprn);
75 gen_helper_store_dump_spr(cpu_env, t0);
76 tcg_temp_free_i32(t0);
77 #endif
78 }
79
80 static void spr_write_generic (void *opaque, int sprn, int gprn)
81 {
82 gen_store_spr(sprn, cpu_gpr[gprn]);
83 spr_store_dump_spr(sprn);
84 }
85
86 #if !defined(CONFIG_USER_ONLY)
87 static void spr_write_generic32(void *opaque, int sprn, int gprn)
88 {
89 #ifdef TARGET_PPC64
90 TCGv t0 = tcg_temp_new();
91 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
92 gen_store_spr(sprn, t0);
93 tcg_temp_free(t0);
94 spr_store_dump_spr(sprn);
95 #else
96 spr_write_generic(opaque, sprn, gprn);
97 #endif
98 }
99
100 static void spr_write_clear (void *opaque, int sprn, int gprn)
101 {
102 TCGv t0 = tcg_temp_new();
103 TCGv t1 = tcg_temp_new();
104 gen_load_spr(t0, sprn);
105 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
106 tcg_gen_and_tl(t0, t0, t1);
107 gen_store_spr(sprn, t0);
108 tcg_temp_free(t0);
109 tcg_temp_free(t1);
110 }
111
112 static void spr_access_nop(void *opaque, int sprn, int gprn)
113 {
114 }
115
116 #endif
117
118 /* SPR common to all PowerPC */
119 /* XER */
120 static void spr_read_xer (void *opaque, int gprn, int sprn)
121 {
122 gen_read_xer(cpu_gpr[gprn]);
123 }
124
125 static void spr_write_xer (void *opaque, int sprn, int gprn)
126 {
127 gen_write_xer(cpu_gpr[gprn]);
128 }
129
130 /* LR */
131 static void spr_read_lr (void *opaque, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
134 }
135
136 static void spr_write_lr (void *opaque, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
139 }
140
141 /* CFAR */
142 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
143 static void spr_read_cfar (void *opaque, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
146 }
147
148 static void spr_write_cfar (void *opaque, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
151 }
152 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
153
154 /* CTR */
155 static void spr_read_ctr (void *opaque, int gprn, int sprn)
156 {
157 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
158 }
159
160 static void spr_write_ctr (void *opaque, int sprn, int gprn)
161 {
162 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
163 }
164
165 /* User read access to SPR */
166 /* USPRx */
167 /* UMMCRx */
168 /* UPMCx */
169 /* USIA */
170 /* UDECR */
171 static void spr_read_ureg (void *opaque, int gprn, int sprn)
172 {
173 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
174 }
175
176 /* SPR common to all non-embedded PowerPC */
177 /* DECR */
178 #if !defined(CONFIG_USER_ONLY)
179 static void spr_read_decr (void *opaque, int gprn, int sprn)
180 {
181 if (use_icount) {
182 gen_io_start();
183 }
184 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
185 if (use_icount) {
186 gen_io_end();
187 gen_stop_exception(opaque);
188 }
189 }
190
191 static void spr_write_decr (void *opaque, int sprn, int gprn)
192 {
193 if (use_icount) {
194 gen_io_start();
195 }
196 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
197 if (use_icount) {
198 gen_io_end();
199 gen_stop_exception(opaque);
200 }
201 }
202 #endif
203
204 /* SPR common to all non-embedded PowerPC, except 601 */
205 /* Time base */
206 static void spr_read_tbl (void *opaque, int gprn, int sprn)
207 {
208 if (use_icount) {
209 gen_io_start();
210 }
211 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
212 if (use_icount) {
213 gen_io_end();
214 gen_stop_exception(opaque);
215 }
216 }
217
218 static void spr_read_tbu (void *opaque, int gprn, int sprn)
219 {
220 if (use_icount) {
221 gen_io_start();
222 }
223 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
224 if (use_icount) {
225 gen_io_end();
226 gen_stop_exception(opaque);
227 }
228 }
229
230 __attribute__ (( unused ))
231 static void spr_read_atbl (void *opaque, int gprn, int sprn)
232 {
233 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
234 }
235
236 __attribute__ (( unused ))
237 static void spr_read_atbu (void *opaque, int gprn, int sprn)
238 {
239 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
240 }
241
242 #if !defined(CONFIG_USER_ONLY)
243 static void spr_write_tbl (void *opaque, int sprn, int gprn)
244 {
245 if (use_icount) {
246 gen_io_start();
247 }
248 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
249 if (use_icount) {
250 gen_io_end();
251 gen_stop_exception(opaque);
252 }
253 }
254
255 static void spr_write_tbu (void *opaque, int sprn, int gprn)
256 {
257 if (use_icount) {
258 gen_io_start();
259 }
260 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
261 if (use_icount) {
262 gen_io_end();
263 gen_stop_exception(opaque);
264 }
265 }
266
267 __attribute__ (( unused ))
268 static void spr_write_atbl (void *opaque, int sprn, int gprn)
269 {
270 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
271 }
272
273 __attribute__ (( unused ))
274 static void spr_write_atbu (void *opaque, int sprn, int gprn)
275 {
276 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
277 }
278
279 #if defined(TARGET_PPC64)
280 __attribute__ (( unused ))
281 static void spr_read_purr (void *opaque, int gprn, int sprn)
282 {
283 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
284 }
285 #endif
286 #endif
287
288 #if !defined(CONFIG_USER_ONLY)
289 /* IBAT0U...IBAT0U */
290 /* IBAT0L...IBAT7L */
291 static void spr_read_ibat (void *opaque, int gprn, int sprn)
292 {
293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
294 }
295
296 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
297 {
298 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
299 }
300
301 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
302 {
303 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
304 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
305 tcg_temp_free_i32(t0);
306 }
307
308 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
309 {
310 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
311 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
312 tcg_temp_free_i32(t0);
313 }
314
315 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
316 {
317 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
318 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
319 tcg_temp_free_i32(t0);
320 }
321
322 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
323 {
324 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
325 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
326 tcg_temp_free_i32(t0);
327 }
328
329 /* DBAT0U...DBAT7U */
330 /* DBAT0L...DBAT7L */
331 static void spr_read_dbat (void *opaque, int gprn, int sprn)
332 {
333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
334 }
335
336 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
337 {
338 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
339 }
340
341 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
342 {
343 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
344 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
345 tcg_temp_free_i32(t0);
346 }
347
348 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
349 {
350 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
351 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
352 tcg_temp_free_i32(t0);
353 }
354
355 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
356 {
357 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
358 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
359 tcg_temp_free_i32(t0);
360 }
361
362 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
363 {
364 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
365 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
367 }
368
369 /* SDR1 */
370 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
371 {
372 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
373 }
374
375 /* 64 bits PowerPC specific SPRs */
376 #if defined(TARGET_PPC64)
377 static void spr_read_hior (void *opaque, int gprn, int sprn)
378 {
379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
380 }
381
382 static void spr_write_hior (void *opaque, int sprn, int gprn)
383 {
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
387 tcg_temp_free(t0);
388 }
389 #endif
390 #endif
391
392 /* PowerPC 601 specific registers */
393 /* RTC */
394 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
397 }
398
399 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
400 {
401 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
402 }
403
404 #if !defined(CONFIG_USER_ONLY)
405 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
411 {
412 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
413 }
414
415 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
416 {
417 DisasContext *ctx = opaque;
418
419 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
420 /* Must stop the translation as endianness may have changed */
421 gen_stop_exception(ctx);
422 }
423 #endif
424
425 /* Unified bats */
426 #if !defined(CONFIG_USER_ONLY)
427 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
428 {
429 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
430 }
431
432 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
433 {
434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
435 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
436 tcg_temp_free_i32(t0);
437 }
438
439 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
440 {
441 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
442 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
443 tcg_temp_free_i32(t0);
444 }
445 #endif
446
447 /* PowerPC 40x specific registers */
448 #if !defined(CONFIG_USER_ONLY)
449 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
450 {
451 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
452 }
453
454 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
455 {
456 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
457 }
458
459 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
460 {
461 DisasContext *ctx = opaque;
462
463 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
464 /* We must stop translation as we may have rebooted */
465 gen_stop_exception(ctx);
466 }
467
468 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
469 {
470 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
471 }
472
473 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
474 {
475 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
476 }
477
478 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
479 {
480 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
481 }
482 #endif
483
484 /* PowerPC 403 specific registers */
485 /* PBL1 / PBU1 / PBL2 / PBU2 */
486 #if !defined(CONFIG_USER_ONLY)
487 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
488 {
489 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
490 }
491
492 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
493 {
494 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
495 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
496 tcg_temp_free_i32(t0);
497 }
498
499 static void spr_write_pir (void *opaque, int sprn, int gprn)
500 {
501 TCGv t0 = tcg_temp_new();
502 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
503 gen_store_spr(SPR_PIR, t0);
504 tcg_temp_free(t0);
505 }
506 #endif
507
508 /* SPE specific registers */
509 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
510 {
511 TCGv_i32 t0 = tcg_temp_new_i32();
512 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
513 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
514 tcg_temp_free_i32(t0);
515 }
516
517 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
518 {
519 TCGv_i32 t0 = tcg_temp_new_i32();
520 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
521 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
522 tcg_temp_free_i32(t0);
523 }
524
525 #if !defined(CONFIG_USER_ONLY)
526 /* Callback used to write the exception vector base */
527 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
528 {
529 TCGv t0 = tcg_temp_new();
530 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
531 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
532 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
533 gen_store_spr(sprn, t0);
534 tcg_temp_free(t0);
535 }
536
537 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
538 {
539 DisasContext *ctx = opaque;
540 int sprn_offs;
541
542 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
543 sprn_offs = sprn - SPR_BOOKE_IVOR0;
544 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
545 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
546 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
547 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
548 } else {
549 printf("Trying to write an unknown exception vector %d %03x\n",
550 sprn, sprn);
551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
552 return;
553 }
554
555 TCGv t0 = tcg_temp_new();
556 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
557 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
558 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
559 gen_store_spr(sprn, t0);
560 tcg_temp_free(t0);
561 }
562 #endif
563
564 static inline void vscr_init (CPUPPCState *env, uint32_t val)
565 {
566 env->vscr = val;
567 /* Altivec always uses round-to-nearest */
568 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
569 set_flush_to_zero(vscr_nj, &env->vec_status);
570 }
571
572 #ifdef CONFIG_USER_ONLY
573 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
574 oea_read, oea_write, one_reg_id, initial_value) \
575 _spr_register(env, num, name, uea_read, uea_write, initial_value)
576 #else
577 #if !defined(CONFIG_KVM)
578 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
579 oea_read, oea_write, one_reg_id, initial_value) \
580 _spr_register(env, num, name, uea_read, uea_write, \
581 oea_read, oea_write, initial_value)
582 #else
583 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, \
586 oea_read, oea_write, one_reg_id, initial_value)
587 #endif
588 #endif
589
590 #define spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, initial_value) \
592 spr_register_kvm(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, 0, initial_value)
594
595 static inline void _spr_register(CPUPPCState *env, int num,
596 const char *name,
597 void (*uea_read)(void *opaque, int gprn, int sprn),
598 void (*uea_write)(void *opaque, int sprn, int gprn),
599 #if !defined(CONFIG_USER_ONLY)
600
601 void (*oea_read)(void *opaque, int gprn, int sprn),
602 void (*oea_write)(void *opaque, int sprn, int gprn),
603 #endif
604 #if defined(CONFIG_KVM)
605 uint64_t one_reg_id,
606 #endif
607 target_ulong initial_value)
608 {
609 ppc_spr_t *spr;
610
611 spr = &env->spr_cb[num];
612 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
613 #if !defined(CONFIG_USER_ONLY)
614 spr->oea_read != NULL || spr->oea_write != NULL ||
615 #endif
616 spr->uea_read != NULL || spr->uea_write != NULL) {
617 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
618 exit(1);
619 }
620 #if defined(PPC_DEBUG_SPR)
621 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
622 name, initial_value);
623 #endif
624 spr->name = name;
625 spr->uea_read = uea_read;
626 spr->uea_write = uea_write;
627 #if !defined(CONFIG_USER_ONLY)
628 spr->oea_read = oea_read;
629 spr->oea_write = oea_write;
630 #endif
631 env->spr[num] = initial_value;
632 }
633
634 /* Generic PowerPC SPRs */
635 static void gen_spr_generic (CPUPPCState *env)
636 {
637 /* Integer processing */
638 spr_register(env, SPR_XER, "XER",
639 &spr_read_xer, &spr_write_xer,
640 &spr_read_xer, &spr_write_xer,
641 0x00000000);
642 /* Branch contol */
643 spr_register(env, SPR_LR, "LR",
644 &spr_read_lr, &spr_write_lr,
645 &spr_read_lr, &spr_write_lr,
646 0x00000000);
647 spr_register(env, SPR_CTR, "CTR",
648 &spr_read_ctr, &spr_write_ctr,
649 &spr_read_ctr, &spr_write_ctr,
650 0x00000000);
651 /* Interrupt processing */
652 spr_register(env, SPR_SRR0, "SRR0",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0x00000000);
656 spr_register(env, SPR_SRR1, "SRR1",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_generic, &spr_write_generic,
659 0x00000000);
660 /* Processor control */
661 spr_register(env, SPR_SPRG0, "SPRG0",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_generic, &spr_write_generic,
664 0x00000000);
665 spr_register(env, SPR_SPRG1, "SPRG1",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_generic, &spr_write_generic,
668 0x00000000);
669 spr_register(env, SPR_SPRG2, "SPRG2",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, &spr_write_generic,
672 0x00000000);
673 spr_register(env, SPR_SPRG3, "SPRG3",
674 SPR_NOACCESS, SPR_NOACCESS,
675 &spr_read_generic, &spr_write_generic,
676 0x00000000);
677 }
678
679 /* SPR common to all non-embedded PowerPC, including 601 */
680 static void gen_spr_ne_601 (CPUPPCState *env)
681 {
682 /* Exception processing */
683 spr_register_kvm(env, SPR_DSISR, "DSISR",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_generic, &spr_write_generic,
686 KVM_REG_PPC_DSISR, 0x00000000);
687 spr_register_kvm(env, SPR_DAR, "DAR",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_generic, &spr_write_generic,
690 KVM_REG_PPC_DAR, 0x00000000);
691 /* Timer */
692 spr_register(env, SPR_DECR, "DECR",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_decr, &spr_write_decr,
695 0x00000000);
696 /* Memory management */
697 spr_register(env, SPR_SDR1, "SDR1",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_generic, &spr_write_sdr1,
700 0x00000000);
701 }
702
703 /* BATs 0-3 */
704 static void gen_low_BATs (CPUPPCState *env)
705 {
706 #if !defined(CONFIG_USER_ONLY)
707 spr_register(env, SPR_IBAT0U, "IBAT0U",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatu,
710 0x00000000);
711 spr_register(env, SPR_IBAT0L, "IBAT0L",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_ibat, &spr_write_ibatl,
714 0x00000000);
715 spr_register(env, SPR_IBAT1U, "IBAT1U",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_ibat, &spr_write_ibatu,
718 0x00000000);
719 spr_register(env, SPR_IBAT1L, "IBAT1L",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_ibat, &spr_write_ibatl,
722 0x00000000);
723 spr_register(env, SPR_IBAT2U, "IBAT2U",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_ibat, &spr_write_ibatu,
726 0x00000000);
727 spr_register(env, SPR_IBAT2L, "IBAT2L",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_ibat, &spr_write_ibatl,
730 0x00000000);
731 spr_register(env, SPR_IBAT3U, "IBAT3U",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_ibat, &spr_write_ibatu,
734 0x00000000);
735 spr_register(env, SPR_IBAT3L, "IBAT3L",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_ibat, &spr_write_ibatl,
738 0x00000000);
739 spr_register(env, SPR_DBAT0U, "DBAT0U",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatu,
742 0x00000000);
743 spr_register(env, SPR_DBAT0L, "DBAT0L",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_dbat, &spr_write_dbatl,
746 0x00000000);
747 spr_register(env, SPR_DBAT1U, "DBAT1U",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_dbat, &spr_write_dbatu,
750 0x00000000);
751 spr_register(env, SPR_DBAT1L, "DBAT1L",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_dbat, &spr_write_dbatl,
754 0x00000000);
755 spr_register(env, SPR_DBAT2U, "DBAT2U",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_dbat, &spr_write_dbatu,
758 0x00000000);
759 spr_register(env, SPR_DBAT2L, "DBAT2L",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_dbat, &spr_write_dbatl,
762 0x00000000);
763 spr_register(env, SPR_DBAT3U, "DBAT3U",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_dbat, &spr_write_dbatu,
766 0x00000000);
767 spr_register(env, SPR_DBAT3L, "DBAT3L",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_dbat, &spr_write_dbatl,
770 0x00000000);
771 env->nb_BATs += 4;
772 #endif
773 }
774
775 /* BATs 4-7 */
776 static void gen_high_BATs (CPUPPCState *env)
777 {
778 #if !defined(CONFIG_USER_ONLY)
779 spr_register(env, SPR_IBAT4U, "IBAT4U",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatu_h,
782 0x00000000);
783 spr_register(env, SPR_IBAT4L, "IBAT4L",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_ibat_h, &spr_write_ibatl_h,
786 0x00000000);
787 spr_register(env, SPR_IBAT5U, "IBAT5U",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_ibat_h, &spr_write_ibatu_h,
790 0x00000000);
791 spr_register(env, SPR_IBAT5L, "IBAT5L",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_ibat_h, &spr_write_ibatl_h,
794 0x00000000);
795 spr_register(env, SPR_IBAT6U, "IBAT6U",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_ibat_h, &spr_write_ibatu_h,
798 0x00000000);
799 spr_register(env, SPR_IBAT6L, "IBAT6L",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat_h, &spr_write_ibatl_h,
802 0x00000000);
803 spr_register(env, SPR_IBAT7U, "IBAT7U",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_ibat_h, &spr_write_ibatu_h,
806 0x00000000);
807 spr_register(env, SPR_IBAT7L, "IBAT7L",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_ibat_h, &spr_write_ibatl_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT4U, "DBAT4U",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatu_h,
814 0x00000000);
815 spr_register(env, SPR_DBAT4L, "DBAT4L",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_dbat_h, &spr_write_dbatl_h,
818 0x00000000);
819 spr_register(env, SPR_DBAT5U, "DBAT5U",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_dbat_h, &spr_write_dbatu_h,
822 0x00000000);
823 spr_register(env, SPR_DBAT5L, "DBAT5L",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_dbat_h, &spr_write_dbatl_h,
826 0x00000000);
827 spr_register(env, SPR_DBAT6U, "DBAT6U",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_dbat_h, &spr_write_dbatu_h,
830 0x00000000);
831 spr_register(env, SPR_DBAT6L, "DBAT6L",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat_h, &spr_write_dbatl_h,
834 0x00000000);
835 spr_register(env, SPR_DBAT7U, "DBAT7U",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_dbat_h, &spr_write_dbatu_h,
838 0x00000000);
839 spr_register(env, SPR_DBAT7L, "DBAT7L",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_dbat_h, &spr_write_dbatl_h,
842 0x00000000);
843 env->nb_BATs += 4;
844 #endif
845 }
846
847 /* Generic PowerPC time base */
848 static void gen_tbl (CPUPPCState *env)
849 {
850 spr_register(env, SPR_VTBL, "TBL",
851 &spr_read_tbl, SPR_NOACCESS,
852 &spr_read_tbl, SPR_NOACCESS,
853 0x00000000);
854 spr_register(env, SPR_TBL, "TBL",
855 &spr_read_tbl, SPR_NOACCESS,
856 &spr_read_tbl, &spr_write_tbl,
857 0x00000000);
858 spr_register(env, SPR_VTBU, "TBU",
859 &spr_read_tbu, SPR_NOACCESS,
860 &spr_read_tbu, SPR_NOACCESS,
861 0x00000000);
862 spr_register(env, SPR_TBU, "TBU",
863 &spr_read_tbu, SPR_NOACCESS,
864 &spr_read_tbu, &spr_write_tbu,
865 0x00000000);
866 }
867
868 /* Softare table search registers */
869 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
870 {
871 #if !defined(CONFIG_USER_ONLY)
872 env->nb_tlb = nb_tlbs;
873 env->nb_ways = nb_ways;
874 env->id_tlbs = 1;
875 env->tlb_type = TLB_6XX;
876 spr_register(env, SPR_DMISS, "DMISS",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, SPR_NOACCESS,
879 0x00000000);
880 spr_register(env, SPR_DCMP, "DCMP",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, SPR_NOACCESS,
883 0x00000000);
884 spr_register(env, SPR_HASH1, "HASH1",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, SPR_NOACCESS,
887 0x00000000);
888 spr_register(env, SPR_HASH2, "HASH2",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, SPR_NOACCESS,
891 0x00000000);
892 spr_register(env, SPR_IMISS, "IMISS",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, SPR_NOACCESS,
895 0x00000000);
896 spr_register(env, SPR_ICMP, "ICMP",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, SPR_NOACCESS,
899 0x00000000);
900 spr_register(env, SPR_RPA, "RPA",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, &spr_write_generic,
903 0x00000000);
904 #endif
905 }
906
907 /* SPR common to MPC755 and G2 */
908 static void gen_spr_G2_755 (CPUPPCState *env)
909 {
910 /* SGPRs */
911 spr_register(env, SPR_SPRG4, "SPRG4",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 spr_register(env, SPR_SPRG5, "SPRG5",
916 SPR_NOACCESS, SPR_NOACCESS,
917 &spr_read_generic, &spr_write_generic,
918 0x00000000);
919 spr_register(env, SPR_SPRG6, "SPRG6",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 spr_register(env, SPR_SPRG7, "SPRG7",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 }
928
929 /* SPR common to all 7xx PowerPC implementations */
930 static void gen_spr_7xx (CPUPPCState *env)
931 {
932 /* Breakpoints */
933 /* XXX : not implemented */
934 spr_register_kvm(env, SPR_DABR, "DABR",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 KVM_REG_PPC_DABR, 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_IABR, "IABR",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* Cache management */
944 /* XXX : not implemented */
945 spr_register(env, SPR_ICTC, "ICTC",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* Performance monitors */
950 /* XXX : not implemented */
951 spr_register(env, SPR_MMCR0, "MMCR0",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955 /* XXX : not implemented */
956 spr_register(env, SPR_MMCR1, "MMCR1",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960 /* XXX : not implemented */
961 spr_register(env, SPR_PMC1, "PMC1",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 /* XXX : not implemented */
966 spr_register(env, SPR_PMC2, "PMC2",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970 /* XXX : not implemented */
971 spr_register(env, SPR_PMC3, "PMC3",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_PMC4, "PMC4",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_SIAR, "SIAR",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, SPR_NOACCESS,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_UMMCR0, "UMMCR0",
987 &spr_read_ureg, SPR_NOACCESS,
988 &spr_read_ureg, SPR_NOACCESS,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_UMMCR1, "UMMCR1",
992 &spr_read_ureg, SPR_NOACCESS,
993 &spr_read_ureg, SPR_NOACCESS,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_UPMC1, "UPMC1",
997 &spr_read_ureg, SPR_NOACCESS,
998 &spr_read_ureg, SPR_NOACCESS,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_UPMC2, "UPMC2",
1002 &spr_read_ureg, SPR_NOACCESS,
1003 &spr_read_ureg, SPR_NOACCESS,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_UPMC3, "UPMC3",
1007 &spr_read_ureg, SPR_NOACCESS,
1008 &spr_read_ureg, SPR_NOACCESS,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_UPMC4, "UPMC4",
1012 &spr_read_ureg, SPR_NOACCESS,
1013 &spr_read_ureg, SPR_NOACCESS,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_USIAR, "USIAR",
1017 &spr_read_ureg, SPR_NOACCESS,
1018 &spr_read_ureg, SPR_NOACCESS,
1019 0x00000000);
1020 /* External access control */
1021 /* XXX : not implemented */
1022 spr_register(env, SPR_EAR, "EAR",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, &spr_write_generic,
1025 0x00000000);
1026 }
1027
1028 #ifdef TARGET_PPC64
1029 #ifndef CONFIG_USER_ONLY
1030 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1031 {
1032 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1033 spr_load_dump_spr(SPR_AMR);
1034 }
1035
1036 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1037 {
1038 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1039 spr_store_dump_spr(SPR_AMR);
1040 }
1041
1042 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1043 {
1044 TCGv t0 = tcg_temp_new();
1045
1046 gen_load_spr(t0, SPR_UAMOR);
1047 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1048 gen_store_spr(SPR_AMR, t0);
1049 spr_store_dump_spr(SPR_AMR);
1050 }
1051 #endif /* CONFIG_USER_ONLY */
1052
1053 static void gen_spr_amr (CPUPPCState *env)
1054 {
1055 #ifndef CONFIG_USER_ONLY
1056 /* Virtual Page Class Key protection */
1057 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1058 * userspace accessible, 29 is privileged. So we only need to set
1059 * the kvm ONE_REG id on one of them, we use 29 */
1060 spr_register(env, SPR_UAMR, "UAMR",
1061 &spr_read_uamr, &spr_write_uamr_pr,
1062 &spr_read_uamr, &spr_write_uamr,
1063 0);
1064 spr_register_kvm(env, SPR_AMR, "AMR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 KVM_REG_PPC_AMR, 0xffffffffffffffffULL);
1068 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 KVM_REG_PPC_UAMOR, 0);
1072 #endif /* !CONFIG_USER_ONLY */
1073 }
1074 #endif /* TARGET_PPC64 */
1075
1076 static void gen_spr_thrm (CPUPPCState *env)
1077 {
1078 /* Thermal management */
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_THRM1, "THRM1",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 /* XXX : not implemented */
1085 spr_register(env, SPR_THRM2, "THRM2",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089 /* XXX : not implemented */
1090 spr_register(env, SPR_THRM3, "THRM3",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
1094 }
1095
1096 /* SPR specific to PowerPC 604 implementation */
1097 static void gen_spr_604 (CPUPPCState *env)
1098 {
1099 /* Processor identification */
1100 spr_register(env, SPR_PIR, "PIR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_pir,
1103 0x00000000);
1104 /* Breakpoints */
1105 /* XXX : not implemented */
1106 spr_register(env, SPR_IABR, "IABR",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 /* XXX : not implemented */
1111 spr_register_kvm(env, SPR_DABR, "DABR",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 KVM_REG_PPC_DABR, 0x00000000);
1115 /* Performance counters */
1116 /* XXX : not implemented */
1117 spr_register(env, SPR_MMCR0, "MMCR0",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
1121 /* XXX : not implemented */
1122 spr_register(env, SPR_PMC1, "PMC1",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_PMC2, "PMC2",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_SIAR, "SIAR",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, SPR_NOACCESS,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_SDA, "SDA",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, SPR_NOACCESS,
1140 0x00000000);
1141 /* External access control */
1142 /* XXX : not implemented */
1143 spr_register(env, SPR_EAR, "EAR",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_generic,
1146 0x00000000);
1147 }
1148
1149 /* SPR specific to PowerPC 603 implementation */
1150 static void gen_spr_603 (CPUPPCState *env)
1151 {
1152 /* External access control */
1153 /* XXX : not implemented */
1154 spr_register(env, SPR_EAR, "EAR",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_generic,
1157 0x00000000);
1158 /* Breakpoints */
1159 /* XXX : not implemented */
1160 spr_register(env, SPR_IABR, "IABR",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_generic,
1163 0x00000000);
1164
1165 }
1166
1167 /* SPR specific to PowerPC G2 implementation */
1168 static void gen_spr_G2 (CPUPPCState *env)
1169 {
1170 /* Memory base address */
1171 /* MBAR */
1172 /* XXX : not implemented */
1173 spr_register(env, SPR_MBAR, "MBAR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* Exception processing */
1178 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_generic,
1185 0x00000000);
1186 /* Breakpoints */
1187 /* XXX : not implemented */
1188 spr_register(env, SPR_DABR, "DABR",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_DABR2, "DABR2",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 /* XXX : not implemented */
1198 spr_register(env, SPR_IABR, "IABR",
1199 SPR_NOACCESS, SPR_NOACCESS,
1200 &spr_read_generic, &spr_write_generic,
1201 0x00000000);
1202 /* XXX : not implemented */
1203 spr_register(env, SPR_IABR2, "IABR2",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 &spr_read_generic, &spr_write_generic,
1206 0x00000000);
1207 /* XXX : not implemented */
1208 spr_register(env, SPR_IBCR, "IBCR",
1209 SPR_NOACCESS, SPR_NOACCESS,
1210 &spr_read_generic, &spr_write_generic,
1211 0x00000000);
1212 /* XXX : not implemented */
1213 spr_register(env, SPR_DBCR, "DBCR",
1214 SPR_NOACCESS, SPR_NOACCESS,
1215 &spr_read_generic, &spr_write_generic,
1216 0x00000000);
1217 }
1218
1219 /* SPR specific to PowerPC 602 implementation */
1220 static void gen_spr_602 (CPUPPCState *env)
1221 {
1222 /* ESA registers */
1223 /* XXX : not implemented */
1224 spr_register(env, SPR_SER, "SER",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1227 0x00000000);
1228 /* XXX : not implemented */
1229 spr_register(env, SPR_SEBR, "SEBR",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* XXX : not implemented */
1234 spr_register(env, SPR_ESASRR, "ESASRR",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 /* Floating point status */
1239 /* XXX : not implemented */
1240 spr_register(env, SPR_SP, "SP",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244 /* XXX : not implemented */
1245 spr_register(env, SPR_LT, "LT",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_generic, &spr_write_generic,
1248 0x00000000);
1249 /* Watchdog timer */
1250 /* XXX : not implemented */
1251 spr_register(env, SPR_TCR, "TCR",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255 /* Interrupt base */
1256 spr_register(env, SPR_IBR, "IBR",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, &spr_write_generic,
1259 0x00000000);
1260 /* XXX : not implemented */
1261 spr_register(env, SPR_IABR, "IABR",
1262 SPR_NOACCESS, SPR_NOACCESS,
1263 &spr_read_generic, &spr_write_generic,
1264 0x00000000);
1265 }
1266
1267 /* SPR specific to PowerPC 601 implementation */
1268 static void gen_spr_601 (CPUPPCState *env)
1269 {
1270 /* Multiplication/division register */
1271 /* MQ */
1272 spr_register(env, SPR_MQ, "MQ",
1273 &spr_read_generic, &spr_write_generic,
1274 &spr_read_generic, &spr_write_generic,
1275 0x00000000);
1276 /* RTC registers */
1277 spr_register(env, SPR_601_RTCU, "RTCU",
1278 SPR_NOACCESS, SPR_NOACCESS,
1279 SPR_NOACCESS, &spr_write_601_rtcu,
1280 0x00000000);
1281 spr_register(env, SPR_601_VRTCU, "RTCU",
1282 &spr_read_601_rtcu, SPR_NOACCESS,
1283 &spr_read_601_rtcu, SPR_NOACCESS,
1284 0x00000000);
1285 spr_register(env, SPR_601_RTCL, "RTCL",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 SPR_NOACCESS, &spr_write_601_rtcl,
1288 0x00000000);
1289 spr_register(env, SPR_601_VRTCL, "RTCL",
1290 &spr_read_601_rtcl, SPR_NOACCESS,
1291 &spr_read_601_rtcl, SPR_NOACCESS,
1292 0x00000000);
1293 /* Timer */
1294 #if 0 /* ? */
1295 spr_register(env, SPR_601_UDECR, "UDECR",
1296 &spr_read_decr, SPR_NOACCESS,
1297 &spr_read_decr, SPR_NOACCESS,
1298 0x00000000);
1299 #endif
1300 /* External access control */
1301 /* XXX : not implemented */
1302 spr_register(env, SPR_EAR, "EAR",
1303 SPR_NOACCESS, SPR_NOACCESS,
1304 &spr_read_generic, &spr_write_generic,
1305 0x00000000);
1306 /* Memory management */
1307 #if !defined(CONFIG_USER_ONLY)
1308 spr_register(env, SPR_IBAT0U, "IBAT0U",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_601_ubat, &spr_write_601_ubatu,
1311 0x00000000);
1312 spr_register(env, SPR_IBAT0L, "IBAT0L",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_601_ubat, &spr_write_601_ubatl,
1315 0x00000000);
1316 spr_register(env, SPR_IBAT1U, "IBAT1U",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_601_ubat, &spr_write_601_ubatu,
1319 0x00000000);
1320 spr_register(env, SPR_IBAT1L, "IBAT1L",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_601_ubat, &spr_write_601_ubatl,
1323 0x00000000);
1324 spr_register(env, SPR_IBAT2U, "IBAT2U",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_601_ubat, &spr_write_601_ubatu,
1327 0x00000000);
1328 spr_register(env, SPR_IBAT2L, "IBAT2L",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_601_ubat, &spr_write_601_ubatl,
1331 0x00000000);
1332 spr_register(env, SPR_IBAT3U, "IBAT3U",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_601_ubat, &spr_write_601_ubatu,
1335 0x00000000);
1336 spr_register(env, SPR_IBAT3L, "IBAT3L",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_601_ubat, &spr_write_601_ubatl,
1339 0x00000000);
1340 env->nb_BATs = 4;
1341 #endif
1342 }
1343
1344 static void gen_spr_74xx (CPUPPCState *env)
1345 {
1346 /* Processor identification */
1347 spr_register(env, SPR_PIR, "PIR",
1348 SPR_NOACCESS, SPR_NOACCESS,
1349 &spr_read_generic, &spr_write_pir,
1350 0x00000000);
1351 /* XXX : not implemented */
1352 spr_register(env, SPR_MMCR2, "MMCR2",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
1356 /* XXX : not implemented */
1357 spr_register(env, SPR_UMMCR2, "UMMCR2",
1358 &spr_read_ureg, SPR_NOACCESS,
1359 &spr_read_ureg, SPR_NOACCESS,
1360 0x00000000);
1361 /* XXX: not implemented */
1362 spr_register(env, SPR_BAMR, "BAMR",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1365 0x00000000);
1366 /* XXX : not implemented */
1367 spr_register(env, SPR_MSSCR0, "MSSCR0",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 /* Hardware implementation registers */
1372 /* XXX : not implemented */
1373 spr_register(env, SPR_HID0, "HID0",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 /* XXX : not implemented */
1378 spr_register(env, SPR_HID1, "HID1",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 /* Altivec */
1383 spr_register(env, SPR_VRSAVE, "VRSAVE",
1384 &spr_read_generic, &spr_write_generic,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387 /* XXX : not implemented */
1388 spr_register(env, SPR_L2CR, "L2CR",
1389 SPR_NOACCESS, SPR_NOACCESS,
1390 &spr_read_generic, spr_access_nop,
1391 0x00000000);
1392 /* Not strictly an SPR */
1393 vscr_init(env, 0x00010000);
1394 }
1395
1396 static void gen_l3_ctrl (CPUPPCState *env)
1397 {
1398 /* L3CR */
1399 /* XXX : not implemented */
1400 spr_register(env, SPR_L3CR, "L3CR",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_generic,
1403 0x00000000);
1404 /* L3ITCR0 */
1405 /* XXX : not implemented */
1406 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410 /* L3PM */
1411 /* XXX : not implemented */
1412 spr_register(env, SPR_L3PM, "L3PM",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_generic,
1415 0x00000000);
1416 }
1417
1418 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1419 {
1420 #if !defined(CONFIG_USER_ONLY)
1421 env->nb_tlb = nb_tlbs;
1422 env->nb_ways = nb_ways;
1423 env->id_tlbs = 1;
1424 env->tlb_type = TLB_6XX;
1425 /* XXX : not implemented */
1426 spr_register(env, SPR_PTEHI, "PTEHI",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_generic,
1429 0x00000000);
1430 /* XXX : not implemented */
1431 spr_register(env, SPR_PTELO, "PTELO",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435 /* XXX : not implemented */
1436 spr_register(env, SPR_TLBMISS, "TLBMISS",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440 #endif
1441 }
1442
1443 #if !defined(CONFIG_USER_ONLY)
1444 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1445 {
1446 TCGv t0 = tcg_temp_new();
1447
1448 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1449 gen_store_spr(sprn, t0);
1450 tcg_temp_free(t0);
1451 }
1452
1453 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1454 {
1455 TCGv_i32 t0 = tcg_const_i32(sprn);
1456 gen_helper_booke206_tlbflush(cpu_env, t0);
1457 tcg_temp_free_i32(t0);
1458 }
1459
1460 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1461 {
1462 TCGv_i32 t0 = tcg_const_i32(sprn);
1463 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1464 tcg_temp_free_i32(t0);
1465 }
1466 #endif
1467
1468 static void gen_spr_usprgh (CPUPPCState *env)
1469 {
1470 spr_register(env, SPR_USPRG4, "USPRG4",
1471 &spr_read_ureg, SPR_NOACCESS,
1472 &spr_read_ureg, SPR_NOACCESS,
1473 0x00000000);
1474 spr_register(env, SPR_USPRG5, "USPRG5",
1475 &spr_read_ureg, SPR_NOACCESS,
1476 &spr_read_ureg, SPR_NOACCESS,
1477 0x00000000);
1478 spr_register(env, SPR_USPRG6, "USPRG6",
1479 &spr_read_ureg, SPR_NOACCESS,
1480 &spr_read_ureg, SPR_NOACCESS,
1481 0x00000000);
1482 spr_register(env, SPR_USPRG7, "USPRG7",
1483 &spr_read_ureg, SPR_NOACCESS,
1484 &spr_read_ureg, SPR_NOACCESS,
1485 0x00000000);
1486 }
1487
1488 /* PowerPC BookE SPR */
1489 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1490 {
1491 const char *ivor_names[64] = {
1492 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1493 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1494 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1495 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1496 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1497 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1498 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1499 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1500 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1501 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1502 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1503 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1504 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1505 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1506 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1507 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1508 };
1509 #define SPR_BOOKE_IVORxx (-1)
1510 int ivor_sprn[64] = {
1511 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1512 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1513 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1514 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1515 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1516 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1517 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1518 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1519 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1520 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1521 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1522 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1523 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1524 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1525 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1526 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1527 };
1528 int i;
1529
1530 /* Interrupt processing */
1531 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
1535 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 /* Debug */
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 /* XXX : not implemented */
1551 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 /* XXX : not implemented */
1556 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560 /* XXX : not implemented */
1561 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_40x_dbcr0,
1564 0x00000000);
1565 /* XXX : not implemented */
1566 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 /* XXX : not implemented */
1571 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575 /* XXX : not implemented */
1576 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_clear,
1579 0x00000000);
1580 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584 spr_register(env, SPR_BOOKE_ESR, "ESR",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_excp_prefix,
1591 0x00000000);
1592 /* Exception vectors */
1593 for (i = 0; i < 64; i++) {
1594 if (ivor_mask & (1ULL << i)) {
1595 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1596 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1597 exit(1);
1598 }
1599 spr_register(env, ivor_sprn[i], ivor_names[i],
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_excp_vector,
1602 0x00000000);
1603 }
1604 }
1605 spr_register(env, SPR_BOOKE_PID, "PID",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_booke_pid,
1608 0x00000000);
1609 spr_register(env, SPR_BOOKE_TCR, "TCR",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_booke_tcr,
1612 0x00000000);
1613 spr_register(env, SPR_BOOKE_TSR, "TSR",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_booke_tsr,
1616 0x00000000);
1617 /* Timer */
1618 spr_register(env, SPR_DECR, "DECR",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_decr, &spr_write_decr,
1621 0x00000000);
1622 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 SPR_NOACCESS, &spr_write_generic,
1625 0x00000000);
1626 /* SPRGs */
1627 spr_register(env, SPR_USPRG0, "USPRG0",
1628 &spr_read_generic, &spr_write_generic,
1629 &spr_read_generic, &spr_write_generic,
1630 0x00000000);
1631 spr_register(env, SPR_SPRG4, "SPRG4",
1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, &spr_write_generic,
1634 0x00000000);
1635 spr_register(env, SPR_SPRG5, "SPRG5",
1636 SPR_NOACCESS, SPR_NOACCESS,
1637 &spr_read_generic, &spr_write_generic,
1638 0x00000000);
1639 spr_register(env, SPR_SPRG6, "SPRG6",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 spr_register(env, SPR_SPRG7, "SPRG7",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 }
1648
1649 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1650 uint32_t maxsize, uint32_t flags,
1651 uint32_t nentries)
1652 {
1653 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1654 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1655 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1656 flags | nentries;
1657 }
1658
1659 /* BookE 2.06 storage control registers */
1660 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1661 uint32_t *tlbncfg)
1662 {
1663 #if !defined(CONFIG_USER_ONLY)
1664 const char *mas_names[8] = {
1665 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1666 };
1667 int mas_sprn[8] = {
1668 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1669 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1670 };
1671 int i;
1672
1673 /* TLB assist registers */
1674 /* XXX : not implemented */
1675 for (i = 0; i < 8; i++) {
1676 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1677 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1678 uea_write = &spr_write_generic;
1679 }
1680 if (mas_mask & (1 << i)) {
1681 spr_register(env, mas_sprn[i], mas_names[i],
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, uea_write,
1684 0x00000000);
1685 }
1686 }
1687 if (env->nb_pids > 1) {
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_BOOKE_PID1, "PID1",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_booke_pid,
1692 0x00000000);
1693 }
1694 if (env->nb_pids > 2) {
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_BOOKE_PID2, "PID2",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_booke_pid,
1699 0x00000000);
1700 }
1701 /* XXX : not implemented */
1702 spr_register(env, SPR_MMUCFG, "MMUCFG",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, SPR_NOACCESS,
1705 0x00000000); /* TOFIX */
1706 switch (env->nb_ways) {
1707 case 4:
1708 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, SPR_NOACCESS,
1711 tlbncfg[3]);
1712 /* Fallthru */
1713 case 3:
1714 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, SPR_NOACCESS,
1717 tlbncfg[2]);
1718 /* Fallthru */
1719 case 2:
1720 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, SPR_NOACCESS,
1723 tlbncfg[1]);
1724 /* Fallthru */
1725 case 1:
1726 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, SPR_NOACCESS,
1729 tlbncfg[0]);
1730 /* Fallthru */
1731 case 0:
1732 default:
1733 break;
1734 }
1735 #endif
1736
1737 gen_spr_usprgh(env);
1738 }
1739
1740 /* SPR specific to PowerPC 440 implementation */
1741 static void gen_spr_440 (CPUPPCState *env)
1742 {
1743 /* Cache control */
1744 /* XXX : not implemented */
1745 spr_register(env, SPR_440_DNV0, "DNV0",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749 /* XXX : not implemented */
1750 spr_register(env, SPR_440_DNV1, "DNV1",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
1754 /* XXX : not implemented */
1755 spr_register(env, SPR_440_DNV2, "DNV2",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_generic,
1758 0x00000000);
1759 /* XXX : not implemented */
1760 spr_register(env, SPR_440_DNV3, "DNV3",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764 /* XXX : not implemented */
1765 spr_register(env, SPR_440_DTV0, "DTV0",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769 /* XXX : not implemented */
1770 spr_register(env, SPR_440_DTV1, "DTV1",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_440_DTV2, "DTV2",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 /* XXX : not implemented */
1780 spr_register(env, SPR_440_DTV3, "DTV3",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784 /* XXX : not implemented */
1785 spr_register(env, SPR_440_DVLIM, "DVLIM",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789 /* XXX : not implemented */
1790 spr_register(env, SPR_440_INV0, "INV0",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794 /* XXX : not implemented */
1795 spr_register(env, SPR_440_INV1, "INV1",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_440_INV2, "INV2",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* XXX : not implemented */
1805 spr_register(env, SPR_440_INV3, "INV3",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 /* XXX : not implemented */
1810 spr_register(env, SPR_440_ITV0, "ITV0",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
1814 /* XXX : not implemented */
1815 spr_register(env, SPR_440_ITV1, "ITV1",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 /* XXX : not implemented */
1820 spr_register(env, SPR_440_ITV2, "ITV2",
1821 SPR_NOACCESS, SPR_NOACCESS,
1822 &spr_read_generic, &spr_write_generic,
1823 0x00000000);
1824 /* XXX : not implemented */
1825 spr_register(env, SPR_440_ITV3, "ITV3",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
1829 /* XXX : not implemented */
1830 spr_register(env, SPR_440_IVLIM, "IVLIM",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* Cache debug */
1835 /* XXX : not implemented */
1836 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, SPR_NOACCESS,
1839 0x00000000);
1840 /* XXX : not implemented */
1841 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, SPR_NOACCESS,
1844 0x00000000);
1845 /* XXX : not implemented */
1846 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, SPR_NOACCESS,
1849 0x00000000);
1850 /* XXX : not implemented */
1851 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, SPR_NOACCESS,
1854 0x00000000);
1855 /* XXX : not implemented */
1856 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, SPR_NOACCESS,
1859 0x00000000);
1860 /* XXX : not implemented */
1861 spr_register(env, SPR_440_DBDR, "DBDR",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_generic, &spr_write_generic,
1864 0x00000000);
1865 /* Processor control */
1866 spr_register(env, SPR_4xx_CCR0, "CCR0",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1871 SPR_NOACCESS, SPR_NOACCESS,
1872 &spr_read_generic, SPR_NOACCESS,
1873 0x00000000);
1874 /* Storage control */
1875 spr_register(env, SPR_440_MMUCR, "MMUCR",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_generic, &spr_write_generic,
1878 0x00000000);
1879 }
1880
1881 /* SPR shared between PowerPC 40x implementations */
1882 static void gen_spr_40x (CPUPPCState *env)
1883 {
1884 /* Cache */
1885 /* not emulated, as QEMU do not emulate caches */
1886 spr_register(env, SPR_40x_DCCR, "DCCR",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890 /* not emulated, as QEMU do not emulate caches */
1891 spr_register(env, SPR_40x_ICCR, "ICCR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* not emulated, as QEMU do not emulate caches */
1896 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, SPR_NOACCESS,
1899 0x00000000);
1900 /* Exception */
1901 spr_register(env, SPR_40x_DEAR, "DEAR",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905 spr_register(env, SPR_40x_ESR, "ESR",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_40x_EVPR, "EVPR",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_excp_prefix,
1912 0x00000000);
1913 spr_register(env, SPR_40x_SRR2, "SRR2",
1914 &spr_read_generic, &spr_write_generic,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_40x_SRR3, "SRR3",
1918 &spr_read_generic, &spr_write_generic,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 /* Timers */
1922 spr_register(env, SPR_40x_PIT, "PIT",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_40x_pit, &spr_write_40x_pit,
1925 0x00000000);
1926 spr_register(env, SPR_40x_TCR, "TCR",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_booke_tcr,
1929 0x00000000);
1930 spr_register(env, SPR_40x_TSR, "TSR",
1931 SPR_NOACCESS, SPR_NOACCESS,
1932 &spr_read_generic, &spr_write_booke_tsr,
1933 0x00000000);
1934 }
1935
1936 /* SPR specific to PowerPC 405 implementation */
1937 static void gen_spr_405 (CPUPPCState *env)
1938 {
1939 /* MMU */
1940 spr_register(env, SPR_40x_PID, "PID",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 spr_register(env, SPR_4xx_CCR0, "CCR0",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 &spr_read_generic, &spr_write_generic,
1947 0x00700000);
1948 /* Debug interface */
1949 /* XXX : not implemented */
1950 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1951 SPR_NOACCESS, SPR_NOACCESS,
1952 &spr_read_generic, &spr_write_40x_dbcr0,
1953 0x00000000);
1954 /* XXX : not implemented */
1955 spr_register(env, SPR_405_DBCR1, "DBCR1",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_40x_DBSR, "DBSR",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_clear,
1963 /* Last reset was system reset */
1964 0x00000300);
1965 /* XXX : not implemented */
1966 spr_register(env, SPR_40x_DAC1, "DAC1",
1967 SPR_NOACCESS, SPR_NOACCESS,
1968 &spr_read_generic, &spr_write_generic,
1969 0x00000000);
1970 spr_register(env, SPR_40x_DAC2, "DAC2",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 /* XXX : not implemented */
1975 spr_register(env, SPR_405_DVC1, "DVC1",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 /* XXX : not implemented */
1980 spr_register(env, SPR_405_DVC2, "DVC2",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, &spr_write_generic,
1983 0x00000000);
1984 /* XXX : not implemented */
1985 spr_register(env, SPR_40x_IAC1, "IAC1",
1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989 spr_register(env, SPR_40x_IAC2, "IAC2",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_generic,
1992 0x00000000);
1993 /* XXX : not implemented */
1994 spr_register(env, SPR_405_IAC3, "IAC3",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_generic,
1997 0x00000000);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_405_IAC4, "IAC4",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* Storage control */
2004 /* XXX: TODO: not implemented */
2005 spr_register(env, SPR_405_SLER, "SLER",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_40x_sler,
2008 0x00000000);
2009 spr_register(env, SPR_40x_ZPR, "ZPR",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, &spr_write_generic,
2012 0x00000000);
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_405_SU0R, "SU0R",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 /* SPRG */
2019 spr_register(env, SPR_USPRG0, "USPRG0",
2020 &spr_read_ureg, SPR_NOACCESS,
2021 &spr_read_ureg, SPR_NOACCESS,
2022 0x00000000);
2023 spr_register(env, SPR_SPRG4, "SPRG4",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_generic,
2026 0x00000000);
2027 spr_register(env, SPR_SPRG5, "SPRG5",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 spr_register(env, SPR_SPRG6, "SPRG6",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 spr_read_generic, &spr_write_generic,
2034 0x00000000);
2035 spr_register(env, SPR_SPRG7, "SPRG7",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039 gen_spr_usprgh(env);
2040 }
2041
2042 /* SPR shared between PowerPC 401 & 403 implementations */
2043 static void gen_spr_401_403 (CPUPPCState *env)
2044 {
2045 /* Time base */
2046 spr_register(env, SPR_403_VTBL, "TBL",
2047 &spr_read_tbl, SPR_NOACCESS,
2048 &spr_read_tbl, SPR_NOACCESS,
2049 0x00000000);
2050 spr_register(env, SPR_403_TBL, "TBL",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 SPR_NOACCESS, &spr_write_tbl,
2053 0x00000000);
2054 spr_register(env, SPR_403_VTBU, "TBU",
2055 &spr_read_tbu, SPR_NOACCESS,
2056 &spr_read_tbu, SPR_NOACCESS,
2057 0x00000000);
2058 spr_register(env, SPR_403_TBU, "TBU",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 SPR_NOACCESS, &spr_write_tbu,
2061 0x00000000);
2062 /* Debug */
2063 /* not emulated, as QEMU do not emulate caches */
2064 spr_register(env, SPR_403_CDBCR, "CDBCR",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068 }
2069
2070 /* SPR specific to PowerPC 401 implementation */
2071 static void gen_spr_401 (CPUPPCState *env)
2072 {
2073 /* Debug interface */
2074 /* XXX : not implemented */
2075 spr_register(env, SPR_40x_DBCR0, "DBCR",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_40x_dbcr0,
2078 0x00000000);
2079 /* XXX : not implemented */
2080 spr_register(env, SPR_40x_DBSR, "DBSR",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_clear,
2083 /* Last reset was system reset */
2084 0x00000300);
2085 /* XXX : not implemented */
2086 spr_register(env, SPR_40x_DAC1, "DAC",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_generic, &spr_write_generic,
2089 0x00000000);
2090 /* XXX : not implemented */
2091 spr_register(env, SPR_40x_IAC1, "IAC",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_generic, &spr_write_generic,
2094 0x00000000);
2095 /* Storage control */
2096 /* XXX: TODO: not implemented */
2097 spr_register(env, SPR_405_SLER, "SLER",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_40x_sler,
2100 0x00000000);
2101 /* not emulated, as QEMU never does speculative access */
2102 spr_register(env, SPR_40x_SGR, "SGR",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, &spr_write_generic,
2105 0xFFFFFFFF);
2106 /* not emulated, as QEMU do not emulate caches */
2107 spr_register(env, SPR_40x_DCWR, "DCWR",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 }
2112
2113 static void gen_spr_401x2 (CPUPPCState *env)
2114 {
2115 gen_spr_401(env);
2116 spr_register(env, SPR_40x_PID, "PID",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, &spr_write_generic,
2119 0x00000000);
2120 spr_register(env, SPR_40x_ZPR, "ZPR",
2121 SPR_NOACCESS, SPR_NOACCESS,
2122 &spr_read_generic, &spr_write_generic,
2123 0x00000000);
2124 }
2125
2126 /* SPR specific to PowerPC 403 implementation */
2127 static void gen_spr_403 (CPUPPCState *env)
2128 {
2129 /* Debug interface */
2130 /* XXX : not implemented */
2131 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2132 SPR_NOACCESS, SPR_NOACCESS,
2133 &spr_read_generic, &spr_write_40x_dbcr0,
2134 0x00000000);
2135 /* XXX : not implemented */
2136 spr_register(env, SPR_40x_DBSR, "DBSR",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_clear,
2139 /* Last reset was system reset */
2140 0x00000300);
2141 /* XXX : not implemented */
2142 spr_register(env, SPR_40x_DAC1, "DAC1",
2143 SPR_NOACCESS, SPR_NOACCESS,
2144 &spr_read_generic, &spr_write_generic,
2145 0x00000000);
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_40x_DAC2, "DAC2",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, &spr_write_generic,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_40x_IAC1, "IAC1",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_generic,
2155 0x00000000);
2156 /* XXX : not implemented */
2157 spr_register(env, SPR_40x_IAC2, "IAC2",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, &spr_write_generic,
2160 0x00000000);
2161 }
2162
2163 static void gen_spr_403_real (CPUPPCState *env)
2164 {
2165 spr_register(env, SPR_403_PBL1, "PBL1",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_403_pbr, &spr_write_403_pbr,
2168 0x00000000);
2169 spr_register(env, SPR_403_PBU1, "PBU1",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_403_pbr, &spr_write_403_pbr,
2172 0x00000000);
2173 spr_register(env, SPR_403_PBL2, "PBL2",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_403_pbr, &spr_write_403_pbr,
2176 0x00000000);
2177 spr_register(env, SPR_403_PBU2, "PBU2",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_403_pbr, &spr_write_403_pbr,
2180 0x00000000);
2181 }
2182
2183 static void gen_spr_403_mmu (CPUPPCState *env)
2184 {
2185 /* MMU */
2186 spr_register(env, SPR_40x_PID, "PID",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 &spr_read_generic, &spr_write_generic,
2189 0x00000000);
2190 spr_register(env, SPR_40x_ZPR, "ZPR",
2191 SPR_NOACCESS, SPR_NOACCESS,
2192 &spr_read_generic, &spr_write_generic,
2193 0x00000000);
2194 }
2195
2196 /* SPR specific to PowerPC compression coprocessor extension */
2197 static void gen_spr_compress (CPUPPCState *env)
2198 {
2199 /* XXX : not implemented */
2200 spr_register(env, SPR_401_SKR, "SKR",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 0x00000000);
2204 }
2205
2206 static void gen_spr_5xx_8xx (CPUPPCState *env)
2207 {
2208 /* Exception processing */
2209 spr_register_kvm(env, SPR_DSISR, "DSISR",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 KVM_REG_PPC_DSISR, 0x00000000);
2213 spr_register_kvm(env, SPR_DAR, "DAR",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 KVM_REG_PPC_DAR, 0x00000000);
2217 /* Timer */
2218 spr_register(env, SPR_DECR, "DECR",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_decr, &spr_write_decr,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_MPC_EIE, "EIE",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_MPC_EID, "EID",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_MPC_NRI, "NRI",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_MPC_CMPA, "CMPA",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_MPC_CMPB, "CMPB",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_MPC_CMPC, "CMPC",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_MPC_CMPD, "CMPD",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_MPC_ECR, "ECR",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_MPC_DER, "DER",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 /* XXX : not implemented */
2268 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 /* XXX : not implemented */
2273 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
2277 /* XXX : not implemented */
2278 spr_register(env, SPR_MPC_CMPE, "CMPE",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_MPC_CMPF, "CMPF",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_MPC_CMPG, "CMPG",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* XXX : not implemented */
2293 spr_register(env, SPR_MPC_CMPH, "CMPH",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* XXX : not implemented */
2298 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_generic, &spr_write_generic,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_MPC_BAR, "BAR",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_MPC_DPDR, "DPDR",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_MPC_IMMR, "IMMR",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 }
2323
2324 static void gen_spr_5xx (CPUPPCState *env)
2325 {
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 /* XXX : not implemented */
2342 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 /* XXX : not implemented */
2347 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_generic,
2375 0x00000000);
2376 /* XXX : not implemented */
2377 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_generic,
2380 0x00000000);
2381 /* XXX : not implemented */
2382 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 /* XXX : not implemented */
2387 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 /* XXX : not implemented */
2392 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 }
2432
2433 static void gen_spr_8xx (CPUPPCState *env)
2434 {
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 /* XXX : not implemented */
2506 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 /* XXX : not implemented */
2511 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 }
2561
2562 // XXX: TODO
2563 /*
2564 * AMR => SPR 29 (Power 2.04)
2565 * CTRL => SPR 136 (Power 2.04)
2566 * CTRL => SPR 152 (Power 2.04)
2567 * SCOMC => SPR 276 (64 bits ?)
2568 * SCOMD => SPR 277 (64 bits ?)
2569 * TBU40 => SPR 286 (Power 2.04 hypv)
2570 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2571 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2572 * HDSISR => SPR 306 (Power 2.04 hypv)
2573 * HDAR => SPR 307 (Power 2.04 hypv)
2574 * PURR => SPR 309 (Power 2.04 hypv)
2575 * HDEC => SPR 310 (Power 2.04 hypv)
2576 * HIOR => SPR 311 (hypv)
2577 * RMOR => SPR 312 (970)
2578 * HRMOR => SPR 313 (Power 2.04 hypv)
2579 * HSRR0 => SPR 314 (Power 2.04 hypv)
2580 * HSRR1 => SPR 315 (Power 2.04 hypv)
2581 * LPCR => SPR 316 (970)
2582 * LPIDR => SPR 317 (970)
2583 * EPR => SPR 702 (Power 2.04 emb)
2584 * perf => 768-783 (Power 2.04)
2585 * perf => 784-799 (Power 2.04)
2586 * PPR => SPR 896 (Power 2.04)
2587 * EPLC => SPR 947 (Power 2.04 emb)
2588 * EPSC => SPR 948 (Power 2.04 emb)
2589 * DABRX => 1015 (Power 2.04 hypv)
2590 * FPECR => SPR 1022 (?)
2591 * ... and more (thermal management, performance counters, ...)
2592 */
2593
2594 /*****************************************************************************/
2595 /* Exception vectors models */
2596 static void init_excp_4xx_real (CPUPPCState *env)
2597 {
2598 #if !defined(CONFIG_USER_ONLY)
2599 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2600 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2601 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2602 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2603 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2604 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2605 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2606 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2607 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2608 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2609 env->ivor_mask = 0x0000FFF0UL;
2610 env->ivpr_mask = 0xFFFF0000UL;
2611 /* Hardware reset vector */
2612 env->hreset_vector = 0xFFFFFFFCUL;
2613 #endif
2614 }
2615
2616 static void init_excp_4xx_softmmu (CPUPPCState *env)
2617 {
2618 #if !defined(CONFIG_USER_ONLY)
2619 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2620 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2621 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2622 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2623 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2624 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2625 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2626 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2627 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2628 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2629 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2630 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2631 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2632 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2633 env->ivor_mask = 0x0000FFF0UL;
2634 env->ivpr_mask = 0xFFFF0000UL;
2635 /* Hardware reset vector */
2636 env->hreset_vector = 0xFFFFFFFCUL;
2637 #endif
2638 }
2639
2640 static void init_excp_MPC5xx (CPUPPCState *env)
2641 {
2642 #if !defined(CONFIG_USER_ONLY)
2643 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2644 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2645 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2646 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2647 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2648 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2649 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2650 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2651 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2652 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2653 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2654 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2655 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2656 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2657 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2658 env->ivor_mask = 0x0000FFF0UL;
2659 env->ivpr_mask = 0xFFFF0000UL;
2660 /* Hardware reset vector */
2661 env->hreset_vector = 0x00000100UL;
2662 #endif
2663 }
2664
2665 static void init_excp_MPC8xx (CPUPPCState *env)
2666 {
2667 #if !defined(CONFIG_USER_ONLY)
2668 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2669 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2670 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2671 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2672 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2673 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2674 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2675 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2676 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2677 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2678 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2679 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2680 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2681 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2682 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2683 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2684 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2685 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2686 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2687 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2688 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2689 env->ivor_mask = 0x0000FFF0UL;
2690 env->ivpr_mask = 0xFFFF0000UL;
2691 /* Hardware reset vector */
2692 env->hreset_vector = 0x00000100UL;
2693 #endif
2694 }
2695
2696 static void init_excp_G2 (CPUPPCState *env)
2697 {
2698 #if !defined(CONFIG_USER_ONLY)
2699 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2700 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2701 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2702 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2703 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2704 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2705 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2706 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2707 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2708 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2709 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2710 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2711 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2712 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2713 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2714 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2715 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2716 /* Hardware reset vector */
2717 env->hreset_vector = 0x00000100UL;
2718 #endif
2719 }
2720
2721 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2722 {
2723 #if !defined(CONFIG_USER_ONLY)
2724 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2725 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2726 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2727 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2744 env->ivor_mask = 0x0000FFF7UL;
2745 env->ivpr_mask = ivpr_mask;
2746 /* Hardware reset vector */
2747 env->hreset_vector = 0xFFFFFFFCUL;
2748 #endif
2749 }
2750
2751 static void init_excp_BookE (CPUPPCState *env)
2752 {
2753 #if !defined(CONFIG_USER_ONLY)
2754 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2755 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2756 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2763 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2764 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2765 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2766 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2767 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2768 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2769 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2770 env->ivor_mask = 0x0000FFE0UL;
2771 env->ivpr_mask = 0xFFFF0000UL;
2772 /* Hardware reset vector */
2773 env->hreset_vector = 0xFFFFFFFCUL;
2774 #endif
2775 }
2776
2777 static void init_excp_601 (CPUPPCState *env)
2778 {
2779 #if !defined(CONFIG_USER_ONLY)
2780 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2781 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2782 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2783 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2784 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2785 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2786 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2787 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2788 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2789 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2790 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2791 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2792 /* Hardware reset vector */
2793 env->hreset_vector = 0x00000100UL;
2794 #endif
2795 }
2796
2797 static void init_excp_602 (CPUPPCState *env)
2798 {
2799 #if !defined(CONFIG_USER_ONLY)
2800 /* XXX: exception prefix has a special behavior on 602 */
2801 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2802 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2803 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2804 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2805 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2806 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2807 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2808 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2809 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2810 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2811 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2812 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2813 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2814 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2815 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2816 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2817 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2818 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2819 /* Hardware reset vector */
2820 env->hreset_vector = 0x00000100UL;
2821 #endif
2822 }
2823
2824 static void init_excp_603 (CPUPPCState *env)
2825 {
2826 #if !defined(CONFIG_USER_ONLY)
2827 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2828 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2829 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2830 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2831 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2832 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2833 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2834 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2835 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2836 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2837 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2838 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2839 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2840 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2841 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2842 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2843 /* Hardware reset vector */
2844 env->hreset_vector = 0x00000100UL;
2845 #endif
2846 }
2847
2848 static void init_excp_604 (CPUPPCState *env)
2849 {
2850 #if !defined(CONFIG_USER_ONLY)
2851 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2852 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2853 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2854 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2855 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2856 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2857 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2858 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2859 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2860 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2861 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2862 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2863 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2864 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2865 /* Hardware reset vector */
2866 env->hreset_vector = 0x00000100UL;
2867 #endif
2868 }
2869
2870 static void init_excp_7x0 (CPUPPCState *env)
2871 {
2872 #if !defined(CONFIG_USER_ONLY)
2873 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2874 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2875 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2876 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2877 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2878 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2879 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2880 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2881 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2882 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2883 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2884 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2885 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2886 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2887 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2888 /* Hardware reset vector */
2889 env->hreset_vector = 0x00000100UL;
2890 #endif
2891 }
2892
2893 static void init_excp_750cl (CPUPPCState *env)
2894 {
2895 #if !defined(CONFIG_USER_ONLY)
2896 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2897 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2898 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2899 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2900 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2901 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2902 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2903 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2904 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2905 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2906 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2907 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2908 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2909 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2910 /* Hardware reset vector */
2911 env->hreset_vector = 0x00000100UL;
2912 #endif
2913 }
2914
2915 static void init_excp_750cx (CPUPPCState *env)
2916 {
2917 #if !defined(CONFIG_USER_ONLY)
2918 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2919 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2920 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2921 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2922 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2923 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2924 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2925 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2926 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2927 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2928 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2929 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2930 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2931 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2932 /* Hardware reset vector */
2933 env->hreset_vector = 0x00000100UL;
2934 #endif
2935 }
2936
2937 /* XXX: Check if this is correct */
2938 static void init_excp_7x5 (CPUPPCState *env)
2939 {
2940 #if !defined(CONFIG_USER_ONLY)
2941 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2942 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2943 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2946 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2947 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2948 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2949 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2950 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2951 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2952 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2953 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2954 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2955 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2956 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2957 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2958 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2959 /* Hardware reset vector */
2960 env->hreset_vector = 0x00000100UL;
2961 #endif
2962 }
2963
2964 static void init_excp_7400 (CPUPPCState *env)
2965 {
2966 #if !defined(CONFIG_USER_ONLY)
2967 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2968 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2969 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2970 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2971 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2972 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2973 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2974 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2975 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2976 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2977 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2978 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2979 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2980 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2981 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2982 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2983 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2984 /* Hardware reset vector */
2985 env->hreset_vector = 0x00000100UL;
2986 #endif
2987 }
2988
2989 static void init_excp_7450 (CPUPPCState *env)
2990 {
2991 #if !defined(CONFIG_USER_ONLY)
2992 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2993 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2994 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2995 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2996 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2997 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2998 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2999 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3000 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3001 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3002 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3003 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3004 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3005 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3006 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3007 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3008 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3009 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3010 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3011 /* Hardware reset vector */
3012 env->hreset_vector = 0x00000100UL;
3013 #endif
3014 }
3015
3016 #if defined (TARGET_PPC64)
3017 static void init_excp_970 (CPUPPCState *env)
3018 {
3019 #if !defined(CONFIG_USER_ONLY)
3020 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3021 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3022 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3023 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3024 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3025 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3026 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3027 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3028 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3029 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3030 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3031 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3032 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3033 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3034 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3035 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3036 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3037 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3038 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3039 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3040 /* Hardware reset vector */
3041 env->hreset_vector = 0x0000000000000100ULL;
3042 #endif
3043 }
3044
3045 static void init_excp_POWER7 (CPUPPCState *env)
3046 {
3047 #if !defined(CONFIG_USER_ONLY)
3048 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3049 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3050 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3051 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3052 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3053 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3054 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3055 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3056 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3057 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3058 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3059 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3060 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3061 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3062 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3063 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3064 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3065 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3066 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3067 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3068 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3069 /* Hardware reset vector */
3070 env->hreset_vector = 0x0000000000000100ULL;
3071 #endif
3072 }
3073 #endif
3074
3075 /*****************************************************************************/
3076 /* Power management enable checks */
3077 static int check_pow_none (CPUPPCState *env)
3078 {
3079 return 0;
3080 }
3081
3082 static int check_pow_nocheck (CPUPPCState *env)
3083 {
3084 return 1;
3085 }
3086
3087 static int check_pow_hid0 (CPUPPCState *env)
3088 {
3089 if (env->spr[SPR_HID0] & 0x00E00000)
3090 return 1;
3091
3092 return 0;
3093 }
3094
3095 static int check_pow_hid0_74xx (CPUPPCState *env)
3096 {
3097 if (env->spr[SPR_HID0] & 0x00600000)
3098 return 1;
3099
3100 return 0;
3101 }
3102
3103 /*****************************************************************************/
3104 /* PowerPC implementations definitions */
3105
3106 #define POWERPC_FAMILY(_name) \
3107 static void \
3108 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3109 \
3110 static const TypeInfo \
3111 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3112 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3113 .parent = TYPE_POWERPC_CPU,