vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-sh4 / cpu.c
1 /*
2 * QEMU SuperH CPU
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "qemu-common.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
28
29
30 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
31 {
32 SuperHCPU *cpu = SUPERH_CPU(cs);
33
34 cpu->env.pc = value;
35 }
36
37 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
38 {
39 SuperHCPU *cpu = SUPERH_CPU(cs);
40
41 cpu->env.pc = tb->pc;
42 cpu->env.flags = tb->flags;
43 }
44
45 static bool superh_cpu_has_work(CPUState *cs)
46 {
47 return cs->interrupt_request & CPU_INTERRUPT_HARD;
48 }
49
50 /* CPUClass::reset() */
51 static void superh_cpu_reset(CPUState *s)
52 {
53 SuperHCPU *cpu = SUPERH_CPU(s);
54 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
55 CPUSH4State *env = &cpu->env;
56
57 scc->parent_reset(s);
58
59 memset(env, 0, offsetof(CPUSH4State, id));
60 tlb_flush(s, 1);
61
62 env->pc = 0xA0000000;
63 #if defined(CONFIG_USER_ONLY)
64 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
65 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
66 #else
67 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
68 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
69 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
70 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
71 set_flush_to_zero(1, &env->fp_status);
72 #endif
73 set_default_nan_mode(1, &env->fp_status);
74 }
75
76 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
77 {
78 info->mach = bfd_mach_sh4;
79 info->print_insn = print_insn_sh;
80 }
81
82 typedef struct SuperHCPUListState {
83 fprintf_function cpu_fprintf;
84 FILE *file;
85 } SuperHCPUListState;
86
87 /* Sort alphabetically by type name. */
88 static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
89 {
90 ObjectClass *class_a = (ObjectClass *)a;
91 ObjectClass *class_b = (ObjectClass *)b;
92 const char *name_a, *name_b;
93
94 name_a = object_class_get_name(class_a);
95 name_b = object_class_get_name(class_b);
96 return strcmp(name_a, name_b);
97 }
98
99 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
100 {
101 ObjectClass *oc = data;
102 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
103 SuperHCPUListState *s = user_data;
104
105 (*s->cpu_fprintf)(s->file, "%s\n",
106 scc->name);
107 }
108
109 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
110 {
111 SuperHCPUListState s = {
112 .cpu_fprintf = cpu_fprintf,
113 .file = f,
114 };
115 GSList *list;
116
117 list = object_class_get_list(TYPE_SUPERH_CPU, false);
118 list = g_slist_sort(list, superh_cpu_list_compare);
119 g_slist_foreach(list, superh_cpu_list_entry, &s);
120 g_slist_free(list);
121 }
122
123 static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
124 {
125 const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
126 const char *name = b;
127
128 return strcasecmp(scc->name, name);
129 }
130
131 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
132 {
133 ObjectClass *oc;
134 GSList *list, *item;
135
136 if (cpu_model == NULL) {
137 return NULL;
138 }
139 if (strcasecmp(cpu_model, "any") == 0) {
140 return object_class_by_name(TYPE_SH7750R_CPU);
141 }
142
143 oc = object_class_by_name(cpu_model);
144 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
145 && !object_class_is_abstract(oc)) {
146 return oc;
147 }
148
149 oc = NULL;
150 list = object_class_get_list(TYPE_SUPERH_CPU, false);
151 item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
152 if (item != NULL) {
153 oc = item->data;
154 }
155 g_slist_free(list);
156 return oc;
157 }
158
159 SuperHCPU *cpu_sh4_init(const char *cpu_model)
160 {
161 return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
162 }
163
164 static void sh7750r_cpu_initfn(Object *obj)
165 {
166 SuperHCPU *cpu = SUPERH_CPU(obj);
167 CPUSH4State *env = &cpu->env;
168
169 env->id = SH_CPU_SH7750R;
170 env->features = SH_FEATURE_BCR3_AND_BCR4;
171 }
172
173 static void sh7750r_class_init(ObjectClass *oc, void *data)
174 {
175 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
176
177 scc->name = "SH7750R";
178 scc->pvr = 0x00050000;
179 scc->prr = 0x00000100;
180 scc->cvr = 0x00110000;
181 }
182
183 static const TypeInfo sh7750r_type_info = {
184 .name = TYPE_SH7750R_CPU,
185 .parent = TYPE_SUPERH_CPU,
186 .class_init = sh7750r_class_init,
187 .instance_init = sh7750r_cpu_initfn,
188 };
189
190 static void sh7751r_cpu_initfn(Object *obj)
191 {
192 SuperHCPU *cpu = SUPERH_CPU(obj);
193 CPUSH4State *env = &cpu->env;
194
195 env->id = SH_CPU_SH7751R;
196 env->features = SH_FEATURE_BCR3_AND_BCR4;
197 }
198
199 static void sh7751r_class_init(ObjectClass *oc, void *data)
200 {
201 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
202
203 scc->name = "SH7751R";
204 scc->pvr = 0x04050005;
205 scc->prr = 0x00000113;
206 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
207 }
208
209 static const TypeInfo sh7751r_type_info = {
210 .name = TYPE_SH7751R_CPU,
211 .parent = TYPE_SUPERH_CPU,
212 .class_init = sh7751r_class_init,
213 .instance_init = sh7751r_cpu_initfn,
214 };
215
216 static void sh7785_cpu_initfn(Object *obj)
217 {
218 SuperHCPU *cpu = SUPERH_CPU(obj);
219 CPUSH4State *env = &cpu->env;
220
221 env->id = SH_CPU_SH7785;
222 env->features = SH_FEATURE_SH4A;
223 }
224
225 static void sh7785_class_init(ObjectClass *oc, void *data)
226 {
227 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
228
229 scc->name = "SH7785";
230 scc->pvr = 0x10300700;
231 scc->prr = 0x00000200;
232 scc->cvr = 0x71440211;
233 }
234
235 static const TypeInfo sh7785_type_info = {
236 .name = TYPE_SH7785_CPU,
237 .parent = TYPE_SUPERH_CPU,
238 .class_init = sh7785_class_init,
239 .instance_init = sh7785_cpu_initfn,
240 };
241
242 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
243 {
244 CPUState *cs = CPU(dev);
245 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
246
247 cpu_reset(cs);
248 qemu_init_vcpu(cs);
249
250 scc->parent_realize(dev, errp);
251 }
252
253 static void superh_cpu_initfn(Object *obj)
254 {
255 CPUState *cs = CPU(obj);
256 SuperHCPU *cpu = SUPERH_CPU(obj);
257 CPUSH4State *env = &cpu->env;
258
259 cs->env_ptr = env;
260 cpu_exec_init(cs, &error_abort);
261
262 env->movcal_backup_tail = &(env->movcal_backup);
263
264 if (tcg_enabled()) {
265 sh4_translate_init();
266 }
267 }
268
269 static const VMStateDescription vmstate_sh_cpu = {
270 .name = "cpu",
271 .unmigratable = 1,
272 };
273
274 static void superh_cpu_class_init(ObjectClass *oc, void *data)
275 {
276 DeviceClass *dc = DEVICE_CLASS(oc);
277 CPUClass *cc = CPU_CLASS(oc);
278 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
279
280 scc->parent_realize = dc->realize;
281 dc->realize = superh_cpu_realizefn;
282
283 scc->parent_reset = cc->reset;
284 cc->reset = superh_cpu_reset;
285
286 cc->class_by_name = superh_cpu_class_by_name;
287 cc->has_work = superh_cpu_has_work;
288 cc->do_interrupt = superh_cpu_do_interrupt;
289 cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
290 cc->dump_state = superh_cpu_dump_state;
291 cc->set_pc = superh_cpu_set_pc;
292 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
293 cc->gdb_read_register = superh_cpu_gdb_read_register;
294 cc->gdb_write_register = superh_cpu_gdb_write_register;
295 #ifdef CONFIG_USER_ONLY
296 cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
297 #else
298 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
299 #endif
300 cc->disas_set_info = superh_cpu_disas_set_info;
301
302 cc->gdb_num_core_regs = 59;
303
304 dc->vmsd = &vmstate_sh_cpu;
305
306 /*
307 * Reason: superh_cpu_initfn() calls cpu_exec_init(), which saves
308 * the object in cpus -> dangling pointer after final
309 * object_unref().
310 */
311 dc->cannot_destroy_with_object_finalize_yet = true;
312 }
313
314 static const TypeInfo superh_cpu_type_info = {
315 .name = TYPE_SUPERH_CPU,
316 .parent = TYPE_CPU,
317 .instance_size = sizeof(SuperHCPU),
318 .instance_init = superh_cpu_initfn,
319 .abstract = true,
320 .class_size = sizeof(SuperHCPUClass),
321 .class_init = superh_cpu_class_init,
322 };
323
324 static void superh_cpu_register_types(void)
325 {
326 type_register_static(&superh_cpu_type_info);
327 type_register_static(&sh7750r_type_info);
328 type_register_static(&sh7751r_type_info);
329 type_register_static(&sh7785_type_info);
330 }
331
332 type_init(superh_cpu_register_types)