vmsvga: don't process more than 1024 fifo commands at once
[qemu.git] / target-sh4 / cpu.h
1 /*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef _CPU_SH4_H
20 #define _CPU_SH4_H
21
22 #include "qemu-common.h"
23 #include "cpu-qom.h"
24
25 #define TARGET_LONG_BITS 32
26
27 /* CPU Subtypes */
28 #define SH_CPU_SH7750 (1 << 0)
29 #define SH_CPU_SH7750S (1 << 1)
30 #define SH_CPU_SH7750R (1 << 2)
31 #define SH_CPU_SH7751 (1 << 3)
32 #define SH_CPU_SH7751R (1 << 4)
33 #define SH_CPU_SH7785 (1 << 5)
34 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
35 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
36
37 #define CPUArchState struct CPUSH4State
38
39 #include "exec/cpu-defs.h"
40
41 #include "fpu/softfloat.h"
42
43 #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
44
45 #define TARGET_PHYS_ADDR_SPACE_BITS 32
46 #define TARGET_VIRT_ADDR_SPACE_BITS 32
47
48 #define SR_MD 30
49 #define SR_RB 29
50 #define SR_BL 28
51 #define SR_FD 15
52 #define SR_M 9
53 #define SR_Q 8
54 #define SR_I3 7
55 #define SR_I2 6
56 #define SR_I1 5
57 #define SR_I0 4
58 #define SR_S 1
59 #define SR_T 0
60
61 #define FPSCR_MASK (0x003fffff)
62 #define FPSCR_FR (1 << 21)
63 #define FPSCR_SZ (1 << 20)
64 #define FPSCR_PR (1 << 19)
65 #define FPSCR_DN (1 << 18)
66 #define FPSCR_CAUSE_MASK (0x3f << 12)
67 #define FPSCR_CAUSE_SHIFT (12)
68 #define FPSCR_CAUSE_E (1 << 17)
69 #define FPSCR_CAUSE_V (1 << 16)
70 #define FPSCR_CAUSE_Z (1 << 15)
71 #define FPSCR_CAUSE_O (1 << 14)
72 #define FPSCR_CAUSE_U (1 << 13)
73 #define FPSCR_CAUSE_I (1 << 12)
74 #define FPSCR_ENABLE_MASK (0x1f << 7)
75 #define FPSCR_ENABLE_SHIFT (7)
76 #define FPSCR_ENABLE_V (1 << 11)
77 #define FPSCR_ENABLE_Z (1 << 10)
78 #define FPSCR_ENABLE_O (1 << 9)
79 #define FPSCR_ENABLE_U (1 << 8)
80 #define FPSCR_ENABLE_I (1 << 7)
81 #define FPSCR_FLAG_MASK (0x1f << 2)
82 #define FPSCR_FLAG_SHIFT (2)
83 #define FPSCR_FLAG_V (1 << 6)
84 #define FPSCR_FLAG_Z (1 << 5)
85 #define FPSCR_FLAG_O (1 << 4)
86 #define FPSCR_FLAG_U (1 << 3)
87 #define FPSCR_FLAG_I (1 << 2)
88 #define FPSCR_RM_MASK (0x03 << 0)
89 #define FPSCR_RM_NEAREST (0 << 0)
90 #define FPSCR_RM_ZERO (1 << 0)
91
92 #define DELAY_SLOT (1 << 0)
93 #define DELAY_SLOT_CONDITIONAL (1 << 1)
94 #define DELAY_SLOT_TRUE (1 << 2)
95 #define DELAY_SLOT_CLEARME (1 << 3)
96 /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
97 * after the delay slot should be taken or not. It is calculated from SR_T.
98 *
99 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
100 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
101 */
102
103 typedef struct tlb_t {
104 uint32_t vpn; /* virtual page number */
105 uint32_t ppn; /* physical page number */
106 uint32_t size; /* mapped page size in bytes */
107 uint8_t asid; /* address space identifier */
108 uint8_t v:1; /* validity */
109 uint8_t sz:2; /* page size */
110 uint8_t sh:1; /* share status */
111 uint8_t c:1; /* cacheability */
112 uint8_t pr:2; /* protection key */
113 uint8_t d:1; /* dirty */
114 uint8_t wt:1; /* write through */
115 uint8_t sa:3; /* space attribute (PCMCIA) */
116 uint8_t tc:1; /* timing control */
117 } tlb_t;
118
119 #define UTLB_SIZE 64
120 #define ITLB_SIZE 4
121
122 #define NB_MMU_MODES 2
123 #define TARGET_INSN_START_EXTRA_WORDS 1
124
125 enum sh_features {
126 SH_FEATURE_SH4A = 1,
127 SH_FEATURE_BCR3_AND_BCR4 = 2,
128 };
129
130 typedef struct memory_content {
131 uint32_t address;
132 uint32_t value;
133 struct memory_content *next;
134 } memory_content;
135
136 typedef struct CPUSH4State {
137 uint32_t flags; /* general execution flags */
138 uint32_t gregs[24]; /* general registers */
139 float32 fregs[32]; /* floating point registers */
140 uint32_t sr; /* status register (with T split out) */
141 uint32_t sr_m; /* M bit of status register */
142 uint32_t sr_q; /* Q bit of status register */
143 uint32_t sr_t; /* T bit of status register */
144 uint32_t ssr; /* saved status register */
145 uint32_t spc; /* saved program counter */
146 uint32_t gbr; /* global base register */
147 uint32_t vbr; /* vector base register */
148 uint32_t sgr; /* saved global register 15 */
149 uint32_t dbr; /* debug base register */
150 uint32_t pc; /* program counter */
151 uint32_t delayed_pc; /* target of delayed jump */
152 uint32_t mach; /* multiply and accumulate high */
153 uint32_t macl; /* multiply and accumulate low */
154 uint32_t pr; /* procedure register */
155 uint32_t fpscr; /* floating point status/control register */
156 uint32_t fpul; /* floating point communication register */
157
158 /* float point status register */
159 float_status fp_status;
160
161 /* Those belong to the specific unit (SH7750) but are handled here */
162 uint32_t mmucr; /* MMU control register */
163 uint32_t pteh; /* page table entry high register */
164 uint32_t ptel; /* page table entry low register */
165 uint32_t ptea; /* page table entry assistance register */
166 uint32_t ttb; /* tranlation table base register */
167 uint32_t tea; /* TLB exception address register */
168 uint32_t tra; /* TRAPA exception register */
169 uint32_t expevt; /* exception event register */
170 uint32_t intevt; /* interrupt event register */
171
172 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
173 tlb_t utlb[UTLB_SIZE]; /* unified translation table */
174
175 uint32_t ldst;
176
177 CPU_COMMON
178
179 /* Fields from here on are preserved over CPU reset. */
180 int id; /* CPU model */
181
182 /* The features that we should emulate. See sh_features above. */
183 uint32_t features;
184
185 void *intc_handle;
186 int in_sleep; /* SR_BL ignored during sleep */
187 memory_content *movcal_backup;
188 memory_content **movcal_backup_tail;
189 } CPUSH4State;
190
191 /**
192 * SuperHCPU:
193 * @env: #CPUSH4State
194 *
195 * A SuperH CPU.
196 */
197 struct SuperHCPU {
198 /*< private >*/
199 CPUState parent_obj;
200 /*< public >*/
201
202 CPUSH4State env;
203 };
204
205 static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
206 {
207 return container_of(env, SuperHCPU, env);
208 }
209
210 #define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e))
211
212 #define ENV_OFFSET offsetof(SuperHCPU, env)
213
214 void superh_cpu_do_interrupt(CPUState *cpu);
215 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
216 void superh_cpu_dump_state(CPUState *cpu, FILE *f,
217 fprintf_function cpu_fprintf, int flags);
218 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
219 int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
220 int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
221
222 void sh4_translate_init(void);
223 SuperHCPU *cpu_sh4_init(const char *cpu_model);
224 int cpu_sh4_exec(CPUState *s);
225 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
226 void *puc);
227 int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
228 int mmu_idx);
229
230 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
231 #if !defined(CONFIG_USER_ONLY)
232 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
233 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
234 hwaddr addr);
235 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
236 uint32_t mem_value);
237 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
238 hwaddr addr);
239 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
240 uint32_t mem_value);
241 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
242 hwaddr addr);
243 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
244 uint32_t mem_value);
245 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
246 hwaddr addr);
247 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
248 uint32_t mem_value);
249 #endif
250
251 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
252
253 void cpu_load_tlb(CPUSH4State * env);
254
255 #define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
256
257 #define cpu_exec cpu_sh4_exec
258 #define cpu_signal_handler cpu_sh4_signal_handler
259 #define cpu_list sh4_cpu_list
260
261 /* MMU modes definitions */
262 #define MMU_MODE0_SUFFIX _kernel
263 #define MMU_MODE1_SUFFIX _user
264 #define MMU_USER_IDX 1
265 static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
266 {
267 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
268 }
269
270 #include "exec/cpu-all.h"
271
272 /* Memory access type */
273 enum {
274 /* Privilege */
275 ACCESS_PRIV = 0x01,
276 /* Direction */
277 ACCESS_WRITE = 0x02,
278 /* Type of instruction */
279 ACCESS_CODE = 0x10,
280 ACCESS_INT = 0x20
281 };
282
283 /* MMU control register */
284 #define MMUCR 0x1F000010
285 #define MMUCR_AT (1<<0)
286 #define MMUCR_TI (1<<2)
287 #define MMUCR_SV (1<<8)
288 #define MMUCR_URC_BITS (6)
289 #define MMUCR_URC_OFFSET (10)
290 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
291 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
292 static inline int cpu_mmucr_urc (uint32_t mmucr)
293 {
294 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
295 }
296
297 /* PTEH : Page Translation Entry High register */
298 #define PTEH_ASID_BITS (8)
299 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
300 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
301 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
302 #define PTEH_VPN_BITS (22)
303 #define PTEH_VPN_OFFSET (10)
304 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
305 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
306 static inline int cpu_pteh_vpn (uint32_t pteh)
307 {
308 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
309 }
310
311 /* PTEL : Page Translation Entry Low register */
312 #define PTEL_V (1 << 8)
313 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
314 #define PTEL_C (1 << 3)
315 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
316 #define PTEL_D (1 << 2)
317 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
318 #define PTEL_SH (1 << 1)
319 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
320 #define PTEL_WT (1 << 0)
321 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
322
323 #define PTEL_SZ_HIGH_OFFSET (7)
324 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
325 #define PTEL_SZ_LOW_OFFSET (4)
326 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
327 static inline int cpu_ptel_sz (uint32_t ptel)
328 {
329 int sz;
330 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
331 sz <<= 1;
332 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
333 return sz;
334 }
335
336 #define PTEL_PPN_BITS (19)
337 #define PTEL_PPN_OFFSET (10)
338 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
339 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
340 static inline int cpu_ptel_ppn (uint32_t ptel)
341 {
342 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
343 }
344
345 #define PTEL_PR_BITS (2)
346 #define PTEL_PR_OFFSET (5)
347 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
348 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
349 static inline int cpu_ptel_pr (uint32_t ptel)
350 {
351 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
352 }
353
354 /* PTEA : Page Translation Entry Assistance register */
355 #define PTEA_SA_BITS (3)
356 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
357 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
358 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
359 #define PTEA_TC (1 << 3)
360 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
361
362 #define TB_FLAG_PENDING_MOVCA (1 << 4)
363
364 static inline target_ulong cpu_read_sr(CPUSH4State *env)
365 {
366 return env->sr | (env->sr_m << SR_M) |
367 (env->sr_q << SR_Q) |
368 (env->sr_t << SR_T);
369 }
370
371 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
372 {
373 env->sr_m = (sr >> SR_M) & 1;
374 env->sr_q = (sr >> SR_Q) & 1;
375 env->sr_t = (sr >> SR_T) & 1;
376 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
377 }
378
379 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
380 target_ulong *cs_base, uint32_t *flags)
381 {
382 *pc = env->pc;
383 *cs_base = 0;
384 *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
385 | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
386 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
387 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
388 | (env->sr & (1u << SR_FD)) /* Bit 15 */
389 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
390 }
391
392 #endif /* _CPU_SH4_H */