cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / target-sh4 / helper.c
1 /*
2 * SH4 emulation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27
28 #if !defined(CONFIG_USER_ONLY)
29 #include "hw/sh4/sh_intc.h"
30 #endif
31
32 #if defined(CONFIG_USER_ONLY)
33
34 void superh_cpu_do_interrupt(CPUState *cs)
35 {
36 cs->exception_index = -1;
37 }
38
39 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
40 int mmu_idx)
41 {
42 SuperHCPU *cpu = SUPERH_CPU(cs);
43 CPUSH4State *env = &cpu->env;
44
45 env->tea = address;
46 cs->exception_index = -1;
47 switch (rw) {
48 case 0:
49 cs->exception_index = 0x0a0;
50 break;
51 case 1:
52 cs->exception_index = 0x0c0;
53 break;
54 case 2:
55 cs->exception_index = 0x0a0;
56 break;
57 }
58 return 1;
59 }
60
61 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
62 {
63 /* For user mode, only U0 area is cachable. */
64 return !(addr & 0x80000000);
65 }
66
67 #else /* !CONFIG_USER_ONLY */
68
69 #define MMU_OK 0
70 #define MMU_ITLB_MISS (-1)
71 #define MMU_ITLB_MULTIPLE (-2)
72 #define MMU_ITLB_VIOLATION (-3)
73 #define MMU_DTLB_MISS_READ (-4)
74 #define MMU_DTLB_MISS_WRITE (-5)
75 #define MMU_DTLB_INITIAL_WRITE (-6)
76 #define MMU_DTLB_VIOLATION_READ (-7)
77 #define MMU_DTLB_VIOLATION_WRITE (-8)
78 #define MMU_DTLB_MULTIPLE (-9)
79 #define MMU_DTLB_MISS (-10)
80 #define MMU_IADDR_ERROR (-11)
81 #define MMU_DADDR_ERROR_READ (-12)
82 #define MMU_DADDR_ERROR_WRITE (-13)
83
84 void superh_cpu_do_interrupt(CPUState *cs)
85 {
86 SuperHCPU *cpu = SUPERH_CPU(cs);
87 CPUSH4State *env = &cpu->env;
88 int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
89 int do_exp, irq_vector = cs->exception_index;
90
91 /* prioritize exceptions over interrupts */
92
93 do_exp = cs->exception_index != -1;
94 do_irq = do_irq && (cs->exception_index == -1);
95
96 if (env->sr & SR_BL) {
97 if (do_exp && cs->exception_index != 0x1e0) {
98 cs->exception_index = 0x000; /* masked exception -> reset */
99 }
100 if (do_irq && !env->in_sleep) {
101 return; /* masked */
102 }
103 }
104 env->in_sleep = 0;
105
106 if (do_irq) {
107 irq_vector = sh_intc_get_pending_vector(env->intc_handle,
108 (env->sr >> 4) & 0xf);
109 if (irq_vector == -1) {
110 return; /* masked */
111 }
112 }
113
114 if (qemu_loglevel_mask(CPU_LOG_INT)) {
115 const char *expname;
116 switch (cs->exception_index) {
117 case 0x0e0:
118 expname = "addr_error";
119 break;
120 case 0x040:
121 expname = "tlb_miss";
122 break;
123 case 0x0a0:
124 expname = "tlb_violation";
125 break;
126 case 0x180:
127 expname = "illegal_instruction";
128 break;
129 case 0x1a0:
130 expname = "slot_illegal_instruction";
131 break;
132 case 0x800:
133 expname = "fpu_disable";
134 break;
135 case 0x820:
136 expname = "slot_fpu";
137 break;
138 case 0x100:
139 expname = "data_write";
140 break;
141 case 0x060:
142 expname = "dtlb_miss_write";
143 break;
144 case 0x0c0:
145 expname = "dtlb_violation_write";
146 break;
147 case 0x120:
148 expname = "fpu_exception";
149 break;
150 case 0x080:
151 expname = "initial_page_write";
152 break;
153 case 0x160:
154 expname = "trapa";
155 break;
156 default:
157 expname = do_irq ? "interrupt" : "???";
158 break;
159 }
160 qemu_log("exception 0x%03x [%s] raised\n",
161 irq_vector, expname);
162 log_cpu_state(cs, 0);
163 }
164
165 env->ssr = env->sr;
166 env->spc = env->pc;
167 env->sgr = env->gregs[15];
168 env->sr |= SR_BL | SR_MD | SR_RB;
169
170 if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
171 /* Branch instruction should be executed again before delay slot. */
172 env->spc -= 2;
173 /* Clear flags for exception/interrupt routine. */
174 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
175 }
176 if (env->flags & DELAY_SLOT_CLEARME)
177 env->flags = 0;
178
179 if (do_exp) {
180 env->expevt = cs->exception_index;
181 switch (cs->exception_index) {
182 case 0x000:
183 case 0x020:
184 case 0x140:
185 env->sr &= ~SR_FD;
186 env->sr |= 0xf << 4; /* IMASK */
187 env->pc = 0xa0000000;
188 break;
189 case 0x040:
190 case 0x060:
191 env->pc = env->vbr + 0x400;
192 break;
193 case 0x160:
194 env->spc += 2; /* special case for TRAPA */
195 /* fall through */
196 default:
197 env->pc = env->vbr + 0x100;
198 break;
199 }
200 return;
201 }
202
203 if (do_irq) {
204 env->intevt = irq_vector;
205 env->pc = env->vbr + 0x600;
206 return;
207 }
208 }
209
210 static void update_itlb_use(CPUSH4State * env, int itlbnb)
211 {
212 uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
213
214 switch (itlbnb) {
215 case 0:
216 and_mask = 0x1f;
217 break;
218 case 1:
219 and_mask = 0xe7;
220 or_mask = 0x80;
221 break;
222 case 2:
223 and_mask = 0xfb;
224 or_mask = 0x50;
225 break;
226 case 3:
227 or_mask = 0x2c;
228 break;
229 }
230
231 env->mmucr &= (and_mask << 24) | 0x00ffffff;
232 env->mmucr |= (or_mask << 24);
233 }
234
235 static int itlb_replacement(CPUSH4State * env)
236 {
237 SuperHCPU *cpu = sh_env_get_cpu(env);
238
239 if ((env->mmucr & 0xe0000000) == 0xe0000000) {
240 return 0;
241 }
242 if ((env->mmucr & 0x98000000) == 0x18000000) {
243 return 1;
244 }
245 if ((env->mmucr & 0x54000000) == 0x04000000) {
246 return 2;
247 }
248 if ((env->mmucr & 0x2c000000) == 0x00000000) {
249 return 3;
250 }
251 cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
252 }
253
254 /* Find the corresponding entry in the right TLB
255 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
256 */
257 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
258 tlb_t * entries, uint8_t nbtlb, int use_asid)
259 {
260 int match = MMU_DTLB_MISS;
261 uint32_t start, end;
262 uint8_t asid;
263 int i;
264
265 asid = env->pteh & 0xff;
266
267 for (i = 0; i < nbtlb; i++) {
268 if (!entries[i].v)
269 continue; /* Invalid entry */
270 if (!entries[i].sh && use_asid && entries[i].asid != asid)
271 continue; /* Bad ASID */
272 start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
273 end = start + entries[i].size - 1;
274 if (address >= start && address <= end) { /* Match */
275 if (match != MMU_DTLB_MISS)
276 return MMU_DTLB_MULTIPLE; /* Multiple match */
277 match = i;
278 }
279 }
280 return match;
281 }
282
283 static void increment_urc(CPUSH4State * env)
284 {
285 uint8_t urb, urc;
286
287 /* Increment URC */
288 urb = ((env->mmucr) >> 18) & 0x3f;
289 urc = ((env->mmucr) >> 10) & 0x3f;
290 urc++;
291 if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
292 urc = 0;
293 env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
294 }
295
296 /* Copy and utlb entry into itlb
297 Return entry
298 */
299 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
300 {
301 int itlb;
302
303 tlb_t * ientry;
304 itlb = itlb_replacement(env);
305 ientry = &env->itlb[itlb];
306 if (ientry->v) {
307 tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
308 }
309 *ientry = env->utlb[utlb];
310 update_itlb_use(env, itlb);
311 return itlb;
312 }
313
314 /* Find itlb entry
315 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
316 */
317 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
318 int use_asid)
319 {
320 int e;
321
322 e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
323 if (e == MMU_DTLB_MULTIPLE) {
324 e = MMU_ITLB_MULTIPLE;
325 } else if (e == MMU_DTLB_MISS) {
326 e = MMU_ITLB_MISS;
327 } else if (e >= 0) {
328 update_itlb_use(env, e);
329 }
330 return e;
331 }
332
333 /* Find utlb entry
334 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
335 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
336 {
337 /* per utlb access */
338 increment_urc(env);
339
340 /* Return entry */
341 return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
342 }
343
344 /* Match address against MMU
345 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
346 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
347 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
348 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
349 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
350 */
351 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
352 int *prot, target_ulong address,
353 int rw, int access_type)
354 {
355 int use_asid, n;
356 tlb_t *matching = NULL;
357
358 use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
359
360 if (rw == 2) {
361 n = find_itlb_entry(env, address, use_asid);
362 if (n >= 0) {
363 matching = &env->itlb[n];
364 if (!(env->sr & SR_MD) && !(matching->pr & 2))
365 n = MMU_ITLB_VIOLATION;
366 else
367 *prot = PAGE_EXEC;
368 } else {
369 n = find_utlb_entry(env, address, use_asid);
370 if (n >= 0) {
371 n = copy_utlb_entry_itlb(env, n);
372 matching = &env->itlb[n];
373 if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
374 n = MMU_ITLB_VIOLATION;
375 } else {
376 *prot = PAGE_READ | PAGE_EXEC;
377 if ((matching->pr & 1) && matching->d) {
378 *prot |= PAGE_WRITE;
379 }
380 }
381 } else if (n == MMU_DTLB_MULTIPLE) {
382 n = MMU_ITLB_MULTIPLE;
383 } else if (n == MMU_DTLB_MISS) {
384 n = MMU_ITLB_MISS;
385 }
386 }
387 } else {
388 n = find_utlb_entry(env, address, use_asid);
389 if (n >= 0) {
390 matching = &env->utlb[n];
391 if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
392 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
393 MMU_DTLB_VIOLATION_READ;
394 } else if ((rw == 1) && !(matching->pr & 1)) {
395 n = MMU_DTLB_VIOLATION_WRITE;
396 } else if ((rw == 1) && !matching->d) {
397 n = MMU_DTLB_INITIAL_WRITE;
398 } else {
399 *prot = PAGE_READ;
400 if ((matching->pr & 1) && matching->d) {
401 *prot |= PAGE_WRITE;
402 }
403 }
404 } else if (n == MMU_DTLB_MISS) {
405 n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
406 MMU_DTLB_MISS_READ;
407 }
408 }
409 if (n >= 0) {
410 n = MMU_OK;
411 *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
412 (address & (matching->size - 1));
413 }
414 return n;
415 }
416
417 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
418 int *prot, target_ulong address,
419 int rw, int access_type)
420 {
421 /* P1, P2 and P4 areas do not use translation */
422 if ((address >= 0x80000000 && address < 0xc0000000) ||
423 address >= 0xe0000000) {
424 if (!(env->sr & SR_MD)
425 && (address < 0xe0000000 || address >= 0xe4000000)) {
426 /* Unauthorized access in user mode (only store queues are available) */
427 fprintf(stderr, "Unauthorized access\n");
428 if (rw == 0)
429 return MMU_DADDR_ERROR_READ;
430 else if (rw == 1)
431 return MMU_DADDR_ERROR_WRITE;
432 else
433 return MMU_IADDR_ERROR;
434 }
435 if (address >= 0x80000000 && address < 0xc0000000) {
436 /* Mask upper 3 bits for P1 and P2 areas */
437 *physical = address & 0x1fffffff;
438 } else {
439 *physical = address;
440 }
441 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
442 return MMU_OK;
443 }
444
445 /* If MMU is disabled, return the corresponding physical page */
446 if (!(env->mmucr & MMUCR_AT)) {
447 *physical = address & 0x1FFFFFFF;
448 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
449 return MMU_OK;
450 }
451
452 /* We need to resort to the MMU */
453 return get_mmu_address(env, physical, prot, address, rw, access_type);
454 }
455
456 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
457 int mmu_idx)
458 {
459 SuperHCPU *cpu = SUPERH_CPU(cs);
460 CPUSH4State *env = &cpu->env;
461 target_ulong physical;
462 int prot, ret, access_type;
463
464 access_type = ACCESS_INT;
465 ret =
466 get_physical_address(env, &physical, &prot, address, rw,
467 access_type);
468
469 if (ret != MMU_OK) {
470 env->tea = address;
471 if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
472 env->pteh = (env->pteh & PTEH_ASID_MASK) |
473 (address & PTEH_VPN_MASK);
474 }
475 switch (ret) {
476 case MMU_ITLB_MISS:
477 case MMU_DTLB_MISS_READ:
478 cs->exception_index = 0x040;
479 break;
480 case MMU_DTLB_MULTIPLE:
481 case MMU_ITLB_MULTIPLE:
482 cs->exception_index = 0x140;
483 break;
484 case MMU_ITLB_VIOLATION:
485 cs->exception_index = 0x0a0;
486 break;
487 case MMU_DTLB_MISS_WRITE:
488 cs->exception_index = 0x060;
489 break;
490 case MMU_DTLB_INITIAL_WRITE:
491 cs->exception_index = 0x080;
492 break;
493 case MMU_DTLB_VIOLATION_READ:
494 cs->exception_index = 0x0a0;
495 break;
496 case MMU_DTLB_VIOLATION_WRITE:
497 cs->exception_index = 0x0c0;
498 break;
499 case MMU_IADDR_ERROR:
500 case MMU_DADDR_ERROR_READ:
501 cs->exception_index = 0x0e0;
502 break;
503 case MMU_DADDR_ERROR_WRITE:
504 cs->exception_index = 0x100;
505 break;
506 default:
507 cpu_abort(cs, "Unhandled MMU fault");
508 }
509 return 1;
510 }
511
512 address &= TARGET_PAGE_MASK;
513 physical &= TARGET_PAGE_MASK;
514
515 tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
516 return 0;
517 }
518
519 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
520 {
521 SuperHCPU *cpu = SUPERH_CPU(cs);
522 target_ulong physical;
523 int prot;
524
525 get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
526 return physical;
527 }
528
529 void cpu_load_tlb(CPUSH4State * env)
530 {
531 SuperHCPU *cpu = sh_env_get_cpu(env);
532 int n = cpu_mmucr_urc(env->mmucr);
533 tlb_t * entry = &env->utlb[n];
534
535 if (entry->v) {
536 /* Overwriting valid entry in utlb. */
537 target_ulong address = entry->vpn << 10;
538 tlb_flush_page(CPU(cpu), address);
539 }
540
541 /* Take values into cpu status from registers. */
542 entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
543 entry->vpn = cpu_pteh_vpn(env->pteh);
544 entry->v = (uint8_t)cpu_ptel_v(env->ptel);
545 entry->ppn = cpu_ptel_ppn(env->ptel);
546 entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
547 switch (entry->sz) {
548 case 0: /* 00 */
549 entry->size = 1024; /* 1K */
550 break;
551 case 1: /* 01 */
552 entry->size = 1024 * 4; /* 4K */
553 break;
554 case 2: /* 10 */
555 entry->size = 1024 * 64; /* 64K */
556 break;
557 case 3: /* 11 */
558 entry->size = 1024 * 1024; /* 1M */
559 break;
560 default:
561 cpu_abort(CPU(cpu), "Unhandled load_tlb");
562 break;
563 }
564 entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
565 entry->c = (uint8_t)cpu_ptel_c(env->ptel);
566 entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
567 entry->d = (uint8_t)cpu_ptel_d(env->ptel);
568 entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
569 entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
570 entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
571 }
572
573 void cpu_sh4_invalidate_tlb(CPUSH4State *s)
574 {
575 int i;
576
577 /* UTLB */
578 for (i = 0; i < UTLB_SIZE; i++) {
579 tlb_t * entry = &s->utlb[i];
580 entry->v = 0;
581 }
582 /* ITLB */
583 for (i = 0; i < ITLB_SIZE; i++) {
584 tlb_t * entry = &s->itlb[i];
585 entry->v = 0;
586 }
587
588 tlb_flush(CPU(sh_env_get_cpu(s)), 1);
589 }
590
591 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
592 hwaddr addr)
593 {
594 int index = (addr & 0x00000300) >> 8;
595 tlb_t * entry = &s->itlb[index];
596
597 return (entry->vpn << 10) |
598 (entry->v << 8) |
599 (entry->asid);
600 }
601
602 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
603 uint32_t mem_value)
604 {
605 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
606 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
607 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
608
609 int index = (addr & 0x00000300) >> 8;
610 tlb_t * entry = &s->itlb[index];
611 if (entry->v) {
612 /* Overwriting valid entry in itlb. */
613 target_ulong address = entry->vpn << 10;
614 tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
615 }
616 entry->asid = asid;
617 entry->vpn = vpn;
618 entry->v = v;
619 }
620
621 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
622 hwaddr addr)
623 {
624 int array = (addr & 0x00800000) >> 23;
625 int index = (addr & 0x00000300) >> 8;
626 tlb_t * entry = &s->itlb[index];
627
628 if (array == 0) {
629 /* ITLB Data Array 1 */
630 return (entry->ppn << 10) |
631 (entry->v << 8) |
632 (entry->pr << 5) |
633 ((entry->sz & 1) << 6) |
634 ((entry->sz & 2) << 4) |
635 (entry->c << 3) |
636 (entry->sh << 1);
637 } else {
638 /* ITLB Data Array 2 */
639 return (entry->tc << 1) |
640 (entry->sa);
641 }
642 }
643
644 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
645 uint32_t mem_value)
646 {
647 int array = (addr & 0x00800000) >> 23;
648 int index = (addr & 0x00000300) >> 8;
649 tlb_t * entry = &s->itlb[index];
650
651 if (array == 0) {
652 /* ITLB Data Array 1 */
653 if (entry->v) {
654 /* Overwriting valid entry in utlb. */
655 target_ulong address = entry->vpn << 10;
656 tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
657 }
658 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
659 entry->v = (mem_value & 0x00000100) >> 8;
660 entry->sz = (mem_value & 0x00000080) >> 6 |
661 (mem_value & 0x00000010) >> 4;
662 entry->pr = (mem_value & 0x00000040) >> 5;
663 entry->c = (mem_value & 0x00000008) >> 3;
664 entry->sh = (mem_value & 0x00000002) >> 1;
665 } else {
666 /* ITLB Data Array 2 */
667 entry->tc = (mem_value & 0x00000008) >> 3;
668 entry->sa = (mem_value & 0x00000007);
669 }
670 }
671
672 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
673 hwaddr addr)
674 {
675 int index = (addr & 0x00003f00) >> 8;
676 tlb_t * entry = &s->utlb[index];
677
678 increment_urc(s); /* per utlb access */
679
680 return (entry->vpn << 10) |
681 (entry->v << 8) |
682 (entry->asid);
683 }
684
685 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
686 uint32_t mem_value)
687 {
688 int associate = addr & 0x0000080;
689 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
690 uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
691 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
692 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
693 int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
694
695 if (associate) {
696 int i;
697 tlb_t * utlb_match_entry = NULL;
698 int needs_tlb_flush = 0;
699
700 /* search UTLB */
701 for (i = 0; i < UTLB_SIZE; i++) {
702 tlb_t * entry = &s->utlb[i];
703 if (!entry->v)
704 continue;
705
706 if (entry->vpn == vpn
707 && (!use_asid || entry->asid == asid || entry->sh)) {
708 if (utlb_match_entry) {
709 CPUState *cs = CPU(sh_env_get_cpu(s));
710
711 /* Multiple TLB Exception */
712 cs->exception_index = 0x140;
713 s->tea = addr;
714 break;
715 }
716 if (entry->v && !v)
717 needs_tlb_flush = 1;
718 entry->v = v;
719 entry->d = d;
720 utlb_match_entry = entry;
721 }
722 increment_urc(s); /* per utlb access */
723 }
724
725 /* search ITLB */
726 for (i = 0; i < ITLB_SIZE; i++) {
727 tlb_t * entry = &s->itlb[i];
728 if (entry->vpn == vpn
729 && (!use_asid || entry->asid == asid || entry->sh)) {
730 if (entry->v && !v)
731 needs_tlb_flush = 1;
732 if (utlb_match_entry)
733 *entry = *utlb_match_entry;
734 else
735 entry->v = v;
736 break;
737 }
738 }
739
740 if (needs_tlb_flush) {
741 tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
742 }
743
744 } else {
745 int index = (addr & 0x00003f00) >> 8;
746 tlb_t * entry = &s->utlb[index];
747 if (entry->v) {
748 CPUState *cs = CPU(sh_env_get_cpu(s));
749
750 /* Overwriting valid entry in utlb. */
751 target_ulong address = entry->vpn << 10;
752 tlb_flush_page(cs, address);
753 }
754 entry->asid = asid;
755 entry->vpn = vpn;
756 entry->d = d;
757 entry->v = v;
758 increment_urc(s);
759 }
760 }
761
762 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
763 hwaddr addr)
764 {
765 int array = (addr & 0x00800000) >> 23;
766 int index = (addr & 0x00003f00) >> 8;
767 tlb_t * entry = &s->utlb[index];
768
769 increment_urc(s); /* per utlb access */
770
771 if (array == 0) {
772 /* ITLB Data Array 1 */
773 return (entry->ppn << 10) |
774 (entry->v << 8) |
775 (entry->pr << 5) |
776 ((entry->sz & 1) << 6) |
777 ((entry->sz & 2) << 4) |
778 (entry->c << 3) |
779 (entry->d << 2) |
780 (entry->sh << 1) |
781 (entry->wt);
782 } else {
783 /* ITLB Data Array 2 */
784 return (entry->tc << 1) |
785 (entry->sa);
786 }
787 }
788
789 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
790 uint32_t mem_value)
791 {
792 int array = (addr & 0x00800000) >> 23;
793 int index = (addr & 0x00003f00) >> 8;
794 tlb_t * entry = &s->utlb[index];
795
796 increment_urc(s); /* per utlb access */
797
798 if (array == 0) {
799 /* UTLB Data Array 1 */
800 if (entry->v) {
801 /* Overwriting valid entry in utlb. */
802 target_ulong address = entry->vpn << 10;
803 tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
804 }
805 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
806 entry->v = (mem_value & 0x00000100) >> 8;
807 entry->sz = (mem_value & 0x00000080) >> 6 |
808 (mem_value & 0x00000010) >> 4;
809 entry->pr = (mem_value & 0x00000060) >> 5;
810 entry->c = (mem_value & 0x00000008) >> 3;
811 entry->d = (mem_value & 0x00000004) >> 2;
812 entry->sh = (mem_value & 0x00000002) >> 1;
813 entry->wt = (mem_value & 0x00000001);
814 } else {
815 /* UTLB Data Array 2 */
816 entry->tc = (mem_value & 0x00000008) >> 3;
817 entry->sa = (mem_value & 0x00000007);
818 }
819 }
820
821 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
822 {
823 int n;
824 int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
825
826 /* check area */
827 if (env->sr & SR_MD) {
828 /* For previledged mode, P2 and P4 area is not cachable. */
829 if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
830 return 0;
831 } else {
832 /* For user mode, only U0 area is cachable. */
833 if (0x80000000 <= addr)
834 return 0;
835 }
836
837 /*
838 * TODO : Evaluate CCR and check if the cache is on or off.
839 * Now CCR is not in CPUSH4State, but in SH7750State.
840 * When you move the ccr into CPUSH4State, the code will be
841 * as follows.
842 */
843 #if 0
844 /* check if operand cache is enabled or not. */
845 if (!(env->ccr & 1))
846 return 0;
847 #endif
848
849 /* if MMU is off, no check for TLB. */
850 if (env->mmucr & MMUCR_AT)
851 return 1;
852
853 /* check TLB */
854 n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
855 if (n >= 0)
856 return env->itlb[n].c;
857
858 n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
859 if (n >= 0)
860 return env->utlb[n].c;
861
862 return 0;
863 }
864
865 #endif