scsi: pvscsi: check command descriptor ring buffer size (CVE-2016-4952)
[qemu.git] / target-sparc / cpu.h
1 #ifndef CPU_SPARC_H
2 #define CPU_SPARC_H
3
4 #include "qemu-common.h"
5 #include "qemu/bswap.h"
6 #include "cpu-qom.h"
7
8 #define ALIGNED_ONLY
9
10 #if !defined(TARGET_SPARC64)
11 #define TARGET_LONG_BITS 32
12 #define TARGET_DPREGS 16
13 #define TARGET_PAGE_BITS 12 /* 4k */
14 #define TARGET_PHYS_ADDR_SPACE_BITS 36
15 #define TARGET_VIRT_ADDR_SPACE_BITS 32
16 #else
17 #define TARGET_LONG_BITS 64
18 #define TARGET_DPREGS 32
19 #define TARGET_PAGE_BITS 13 /* 8k */
20 #define TARGET_PHYS_ADDR_SPACE_BITS 41
21 # ifdef TARGET_ABI32
22 # define TARGET_VIRT_ADDR_SPACE_BITS 32
23 # else
24 # define TARGET_VIRT_ADDR_SPACE_BITS 44
25 # endif
26 #endif
27
28 #define CPUArchState struct CPUSPARCState
29
30 #include "exec/cpu-defs.h"
31
32 #include "fpu/softfloat.h"
33
34 /*#define EXCP_INTERRUPT 0x100*/
35
36 /* trap definitions */
37 #ifndef TARGET_SPARC64
38 #define TT_TFAULT 0x01
39 #define TT_ILL_INSN 0x02
40 #define TT_PRIV_INSN 0x03
41 #define TT_NFPU_INSN 0x04
42 #define TT_WIN_OVF 0x05
43 #define TT_WIN_UNF 0x06
44 #define TT_UNALIGNED 0x07
45 #define TT_FP_EXCP 0x08
46 #define TT_DFAULT 0x09
47 #define TT_TOVF 0x0a
48 #define TT_EXTINT 0x10
49 #define TT_CODE_ACCESS 0x21
50 #define TT_UNIMP_FLUSH 0x25
51 #define TT_DATA_ACCESS 0x29
52 #define TT_DIV_ZERO 0x2a
53 #define TT_NCP_INSN 0x24
54 #define TT_TRAP 0x80
55 #else
56 #define TT_POWER_ON_RESET 0x01
57 #define TT_TFAULT 0x08
58 #define TT_CODE_ACCESS 0x0a
59 #define TT_ILL_INSN 0x10
60 #define TT_UNIMP_FLUSH TT_ILL_INSN
61 #define TT_PRIV_INSN 0x11
62 #define TT_NFPU_INSN 0x20
63 #define TT_FP_EXCP 0x21
64 #define TT_TOVF 0x23
65 #define TT_CLRWIN 0x24
66 #define TT_DIV_ZERO 0x28
67 #define TT_DFAULT 0x30
68 #define TT_DATA_ACCESS 0x32
69 #define TT_UNALIGNED 0x34
70 #define TT_PRIV_ACT 0x37
71 #define TT_EXTINT 0x40
72 #define TT_IVEC 0x60
73 #define TT_TMISS 0x64
74 #define TT_DMISS 0x68
75 #define TT_DPROT 0x6c
76 #define TT_SPILL 0x80
77 #define TT_FILL 0xc0
78 #define TT_WOTHER (1 << 5)
79 #define TT_TRAP 0x100
80 #endif
81
82 #define PSR_NEG_SHIFT 23
83 #define PSR_NEG (1 << PSR_NEG_SHIFT)
84 #define PSR_ZERO_SHIFT 22
85 #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
86 #define PSR_OVF_SHIFT 21
87 #define PSR_OVF (1 << PSR_OVF_SHIFT)
88 #define PSR_CARRY_SHIFT 20
89 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
90 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
91 #if !defined(TARGET_SPARC64)
92 #define PSR_EF (1<<12)
93 #define PSR_PIL 0xf00
94 #define PSR_S (1<<7)
95 #define PSR_PS (1<<6)
96 #define PSR_ET (1<<5)
97 #define PSR_CWP 0x1f
98 #endif
99
100 #define CC_SRC (env->cc_src)
101 #define CC_SRC2 (env->cc_src2)
102 #define CC_DST (env->cc_dst)
103 #define CC_OP (env->cc_op)
104
105 enum {
106 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
107 CC_OP_FLAGS, /* all cc are back in status register */
108 CC_OP_DIV, /* modify N, Z and V, C = 0*/
109 CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
110 CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
111 CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
112 CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
113 CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
114 CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
115 CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
116 CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
117 CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
118 CC_OP_NB,
119 };
120
121 /* Trap base register */
122 #define TBR_BASE_MASK 0xfffff000
123
124 #if defined(TARGET_SPARC64)
125 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
126 #define PS_IG (1<<11) /* v9, zero on UA2007 */
127 #define PS_MG (1<<10) /* v9, zero on UA2007 */
128 #define PS_CLE (1<<9) /* UA2007 */
129 #define PS_TLE (1<<8) /* UA2007 */
130 #define PS_RMO (1<<7)
131 #define PS_RED (1<<5) /* v9, zero on UA2007 */
132 #define PS_PEF (1<<4) /* enable fpu */
133 #define PS_AM (1<<3) /* address mask */
134 #define PS_PRIV (1<<2)
135 #define PS_IE (1<<1)
136 #define PS_AG (1<<0) /* v9, zero on UA2007 */
137
138 #define FPRS_FEF (1<<2)
139
140 #define HS_PRIV (1<<2)
141 #endif
142
143 /* Fcc */
144 #define FSR_RD1 (1ULL << 31)
145 #define FSR_RD0 (1ULL << 30)
146 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
147 #define FSR_RD_NEAREST 0
148 #define FSR_RD_ZERO FSR_RD0
149 #define FSR_RD_POS FSR_RD1
150 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
151
152 #define FSR_NVM (1ULL << 27)
153 #define FSR_OFM (1ULL << 26)
154 #define FSR_UFM (1ULL << 25)
155 #define FSR_DZM (1ULL << 24)
156 #define FSR_NXM (1ULL << 23)
157 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
158
159 #define FSR_NVA (1ULL << 9)
160 #define FSR_OFA (1ULL << 8)
161 #define FSR_UFA (1ULL << 7)
162 #define FSR_DZA (1ULL << 6)
163 #define FSR_NXA (1ULL << 5)
164 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
165
166 #define FSR_NVC (1ULL << 4)
167 #define FSR_OFC (1ULL << 3)
168 #define FSR_UFC (1ULL << 2)
169 #define FSR_DZC (1ULL << 1)
170 #define FSR_NXC (1ULL << 0)
171 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
172
173 #define FSR_FTT2 (1ULL << 16)
174 #define FSR_FTT1 (1ULL << 15)
175 #define FSR_FTT0 (1ULL << 14)
176 //gcc warns about constant overflow for ~FSR_FTT_MASK
177 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
178 #ifdef TARGET_SPARC64
179 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
180 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
181 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
182 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
183 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
184 #else
185 #define FSR_FTT_NMASK 0xfffe3fffULL
186 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
187 #define FSR_LDFSR_OLDMASK 0x000fc000ULL
188 #endif
189 #define FSR_LDFSR_MASK 0xcfc00fffULL
190 #define FSR_FTT_IEEE_EXCP (1ULL << 14)
191 #define FSR_FTT_UNIMPFPOP (3ULL << 14)
192 #define FSR_FTT_SEQ_ERROR (4ULL << 14)
193 #define FSR_FTT_INVAL_FPR (6ULL << 14)
194
195 #define FSR_FCC1_SHIFT 11
196 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
197 #define FSR_FCC0_SHIFT 10
198 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
199
200 /* MMU */
201 #define MMU_E (1<<0)
202 #define MMU_NF (1<<1)
203
204 #define PTE_ENTRYTYPE_MASK 3
205 #define PTE_ACCESS_MASK 0x1c
206 #define PTE_ACCESS_SHIFT 2
207 #define PTE_PPN_SHIFT 7
208 #define PTE_ADDR_MASK 0xffffff00
209
210 #define PG_ACCESSED_BIT 5
211 #define PG_MODIFIED_BIT 6
212 #define PG_CACHE_BIT 7
213
214 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
215 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
216 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
217
218 /* 3 <= NWINDOWS <= 32. */
219 #define MIN_NWINDOWS 3
220 #define MAX_NWINDOWS 32
221
222 #if !defined(TARGET_SPARC64)
223 #define NB_MMU_MODES 2
224 #else
225 #define NB_MMU_MODES 6
226 typedef struct trap_state {
227 uint64_t tpc;
228 uint64_t tnpc;
229 uint64_t tstate;
230 uint32_t tt;
231 } trap_state;
232 #endif
233 #define TARGET_INSN_START_EXTRA_WORDS 1
234
235 typedef struct sparc_def_t {
236 const char *name;
237 target_ulong iu_version;
238 uint32_t fpu_version;
239 uint32_t mmu_version;
240 uint32_t mmu_bm;
241 uint32_t mmu_ctpr_mask;
242 uint32_t mmu_cxr_mask;
243 uint32_t mmu_sfsr_mask;
244 uint32_t mmu_trcr_mask;
245 uint32_t mxcc_version;
246 uint32_t features;
247 uint32_t nwindows;
248 uint32_t maxtl;
249 } sparc_def_t;
250
251 #define CPU_FEATURE_FLOAT (1 << 0)
252 #define CPU_FEATURE_FLOAT128 (1 << 1)
253 #define CPU_FEATURE_SWAP (1 << 2)
254 #define CPU_FEATURE_MUL (1 << 3)
255 #define CPU_FEATURE_DIV (1 << 4)
256 #define CPU_FEATURE_FLUSH (1 << 5)
257 #define CPU_FEATURE_FSQRT (1 << 6)
258 #define CPU_FEATURE_FMUL (1 << 7)
259 #define CPU_FEATURE_VIS1 (1 << 8)
260 #define CPU_FEATURE_VIS2 (1 << 9)
261 #define CPU_FEATURE_FSMULD (1 << 10)
262 #define CPU_FEATURE_HYPV (1 << 11)
263 #define CPU_FEATURE_CMT (1 << 12)
264 #define CPU_FEATURE_GL (1 << 13)
265 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
266 #define CPU_FEATURE_ASR17 (1 << 15)
267 #define CPU_FEATURE_CACHE_CTRL (1 << 16)
268 #define CPU_FEATURE_POWERDOWN (1 << 17)
269 #define CPU_FEATURE_CASA (1 << 18)
270
271 #ifndef TARGET_SPARC64
272 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
273 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
274 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
275 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
276 #else
277 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
278 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
279 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
280 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
281 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
282 CPU_FEATURE_CASA)
283 enum {
284 mmu_us_12, // Ultrasparc < III (64 entry TLB)
285 mmu_us_3, // Ultrasparc III (512 entry TLB)
286 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
287 mmu_sun4v, // T1, T2
288 };
289 #endif
290
291 #define TTE_VALID_BIT (1ULL << 63)
292 #define TTE_NFO_BIT (1ULL << 60)
293 #define TTE_USED_BIT (1ULL << 41)
294 #define TTE_LOCKED_BIT (1ULL << 6)
295 #define TTE_SIDEEFFECT_BIT (1ULL << 3)
296 #define TTE_PRIV_BIT (1ULL << 2)
297 #define TTE_W_OK_BIT (1ULL << 1)
298 #define TTE_GLOBAL_BIT (1ULL << 0)
299
300 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
301 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
302 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
303 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
304 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
305 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
306 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
307 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
308
309 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
310 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
311
312 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
313 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
314
315 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
316 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */
317 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */
318 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */
319 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */
320 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */
321 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */
322 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */
323 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */
324 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */
325 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */
326 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */
327 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */
328
329 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */
330 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT)
331 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */
332 #define SFSR_CT_SECONDARY (1ULL << 4)
333 #define SFSR_CT_NUCLEUS (2ULL << 4)
334 #define SFSR_CT_NOTRANS (3ULL << 4)
335 #define SFSR_CT_MASK (3ULL << 4)
336
337 /* Leon3 cache control */
338
339 /* Cache control: emulate the behavior of cache control registers but without
340 any effect on the emulated */
341
342 #define CACHE_STATE_MASK 0x3
343 #define CACHE_DISABLED 0x0
344 #define CACHE_FROZEN 0x1
345 #define CACHE_ENABLED 0x3
346
347 /* Cache Control register fields */
348
349 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
350 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
351 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
352 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
353 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
354 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
355 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
356 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
357
358 typedef struct SparcTLBEntry {
359 uint64_t tag;
360 uint64_t tte;
361 } SparcTLBEntry;
362
363 struct CPUTimer
364 {
365 const char *name;
366 uint32_t frequency;
367 uint32_t disabled;
368 uint64_t disabled_mask;
369 uint32_t npt;
370 uint64_t npt_mask;
371 int64_t clock_offset;
372 QEMUTimer *qtimer;
373 };
374
375 typedef struct CPUTimer CPUTimer;
376
377 typedef struct CPUSPARCState CPUSPARCState;
378
379 struct CPUSPARCState {
380 target_ulong gregs[8]; /* general registers */
381 target_ulong *regwptr; /* pointer to current register window */
382 target_ulong pc; /* program counter */
383 target_ulong npc; /* next program counter */
384 target_ulong y; /* multiply/divide register */
385
386 /* emulator internal flags handling */
387 target_ulong cc_src, cc_src2;
388 target_ulong cc_dst;
389 uint32_t cc_op;
390
391 target_ulong cond; /* conditional branch result (XXX: save it in a
392 temporary register when possible) */
393
394 uint32_t psr; /* processor state register */
395 target_ulong fsr; /* FPU state register */
396 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */
397 uint32_t cwp; /* index of current register window (extracted
398 from PSR) */
399 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
400 uint32_t wim; /* window invalid mask */
401 #endif
402 target_ulong tbr; /* trap base register */
403 #if !defined(TARGET_SPARC64)
404 int psrs; /* supervisor mode (extracted from PSR) */
405 int psrps; /* previous supervisor mode */
406 int psret; /* enable traps */
407 #endif
408 uint32_t psrpil; /* interrupt blocking level */
409 uint32_t pil_in; /* incoming interrupt level bitmap */
410 #if !defined(TARGET_SPARC64)
411 int psref; /* enable fpu */
412 #endif
413 int interrupt_index;
414 /* NOTE: we allow 8 more registers to handle wrapping */
415 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
416
417 CPU_COMMON
418
419 /* Fields from here on are preserved across CPU reset. */
420 target_ulong version;
421 uint32_t nwindows;
422
423 /* MMU regs */
424 #if defined(TARGET_SPARC64)
425 uint64_t lsu;
426 #define DMMU_E 0x8
427 #define IMMU_E 0x4
428 //typedef struct SparcMMU
429 union {
430 uint64_t immuregs[16];
431 struct {
432 uint64_t tsb_tag_target;
433 uint64_t unused_mmu_primary_context; // use DMMU
434 uint64_t unused_mmu_secondary_context; // use DMMU
435 uint64_t sfsr;
436 uint64_t sfar;
437 uint64_t tsb;
438 uint64_t tag_access;
439 } immu;
440 };
441 union {
442 uint64_t dmmuregs[16];
443 struct {
444 uint64_t tsb_tag_target;
445 uint64_t mmu_primary_context;
446 uint64_t mmu_secondary_context;
447 uint64_t sfsr;
448 uint64_t sfar;
449 uint64_t tsb;
450 uint64_t tag_access;
451 } dmmu;
452 };
453 SparcTLBEntry itlb[64];
454 SparcTLBEntry dtlb[64];
455 uint32_t mmu_version;
456 #else
457 uint32_t mmuregs[32];
458 uint64_t mxccdata[4];
459 uint64_t mxccregs[8];
460 uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
461 uint64_t mmubpaction;
462 uint64_t mmubpregs[4];
463 uint64_t prom_addr;
464 #endif
465 /* temporary float registers */
466 float128 qt0, qt1;
467 float_status fp_status;
468 #if defined(TARGET_SPARC64)
469 #define MAXTL_MAX 8
470 #define MAXTL_MASK (MAXTL_MAX - 1)
471 trap_state ts[MAXTL_MAX];
472 uint32_t xcc; /* Extended integer condition codes */
473 uint32_t asi;
474 uint32_t pstate;
475 uint32_t tl;
476 uint32_t maxtl;
477 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
478 uint64_t agregs[8]; /* alternate general registers */
479 uint64_t bgregs[8]; /* backup for normal global registers */
480 uint64_t igregs[8]; /* interrupt general registers */
481 uint64_t mgregs[8]; /* mmu general registers */
482 uint64_t fprs;
483 uint64_t tick_cmpr, stick_cmpr;
484 CPUTimer *tick, *stick;
485 #define TICK_NPT_MASK 0x8000000000000000ULL
486 #define TICK_INT_DIS 0x8000000000000000ULL
487 uint64_t gsr;
488 uint32_t gl; // UA2005
489 /* UA 2005 hyperprivileged registers */
490 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
491 CPUTimer *hstick; // UA 2005
492 /* Interrupt vector registers */
493 uint64_t ivec_status;
494 uint64_t ivec_data[3];
495 uint32_t softint;
496 #define SOFTINT_TIMER 1
497 #define SOFTINT_STIMER (1 << 16)
498 #define SOFTINT_INTRMASK (0xFFFE)
499 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
500 #endif
501 sparc_def_t *def;
502
503 void *irq_manager;
504 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
505
506 /* Leon3 cache control */
507 uint32_t cache_control;
508 };
509
510 /**
511 * SPARCCPU:
512 * @env: #CPUSPARCState
513 *
514 * A SPARC CPU.
515 */
516 struct SPARCCPU {
517 /*< private >*/
518 CPUState parent_obj;
519 /*< public >*/
520
521 CPUSPARCState env;
522 };
523
524 static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
525 {
526 return container_of(env, SPARCCPU, env);
527 }
528
529 #define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e))
530
531 #define ENV_OFFSET offsetof(SPARCCPU, env)
532
533 #ifndef CONFIG_USER_ONLY
534 extern const struct VMStateDescription vmstate_sparc_cpu;
535 #endif
536
537 void sparc_cpu_do_interrupt(CPUState *cpu);
538 void sparc_cpu_dump_state(CPUState *cpu, FILE *f,
539 fprintf_function cpu_fprintf, int flags);
540 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
541 int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
542 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
543 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu,
544 vaddr addr, int is_write,
545 int is_user, uintptr_t retaddr);
546
547 #ifndef NO_CPU_IO_DEFS
548 /* cpu_init.c */
549 SPARCCPU *cpu_sparc_init(const char *cpu_model);
550 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
551 void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
552 /* mmu_helper.c */
553 int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
554 int mmu_idx);
555 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
556 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
557
558 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
559 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
560 uint8_t *buf, int len, bool is_write);
561 #endif
562
563
564 /* translate.c */
565 void gen_intermediate_code_init(CPUSPARCState *env);
566
567 /* cpu-exec.c */
568 int cpu_sparc_exec(CPUState *cpu);
569
570 /* win_helper.c */
571 target_ulong cpu_get_psr(CPUSPARCState *env1);
572 void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
573 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
574 #ifdef TARGET_SPARC64
575 target_ulong cpu_get_ccr(CPUSPARCState *env1);
576 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
577 target_ulong cpu_get_cwp64(CPUSPARCState *env1);
578 void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
579 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
580 #endif
581 int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
582 int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
583 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
584
585 /* int_helper.c */
586 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
587
588 /* sun4m.c, sun4u.c */
589 void cpu_check_irqs(CPUSPARCState *env);
590
591 /* leon3.c */
592 void leon3_irq_ack(void *irq_manager, int intno);
593
594 #if defined (TARGET_SPARC64)
595
596 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
597 {
598 return (x & mask) == (y & mask);
599 }
600
601 #define MMU_CONTEXT_BITS 13
602 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
603
604 static inline int tlb_compare_context(const SparcTLBEntry *tlb,
605 uint64_t context)
606 {
607 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
608 }
609
610 #endif
611 #endif
612
613 /* cpu-exec.c */
614 #if !defined(CONFIG_USER_ONLY)
615 void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
616 bool is_write, bool is_exec, int is_asi,
617 unsigned size);
618 #if defined(TARGET_SPARC64)
619 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
620 int mmu_idx);
621 #endif
622 #endif
623 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
624
625 #ifndef NO_CPU_IO_DEFS
626 #define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model))
627 #endif
628
629 #define cpu_exec cpu_sparc_exec
630 #define cpu_signal_handler cpu_sparc_signal_handler
631 #define cpu_list sparc_cpu_list
632
633 /* MMU modes definitions */
634 #if defined (TARGET_SPARC64)
635 #define MMU_USER_IDX 0
636 #define MMU_MODE0_SUFFIX _user
637 #define MMU_USER_SECONDARY_IDX 1
638 #define MMU_MODE1_SUFFIX _user_secondary
639 #define MMU_KERNEL_IDX 2
640 #define MMU_MODE2_SUFFIX _kernel
641 #define MMU_KERNEL_SECONDARY_IDX 3
642 #define MMU_MODE3_SUFFIX _kernel_secondary
643 #define MMU_NUCLEUS_IDX 4
644 #define MMU_MODE4_SUFFIX _nucleus
645 #define MMU_HYPV_IDX 5
646 #define MMU_MODE5_SUFFIX _hypv
647 #else
648 #define MMU_USER_IDX 0
649 #define MMU_MODE0_SUFFIX _user
650 #define MMU_KERNEL_IDX 1
651 #define MMU_MODE1_SUFFIX _kernel
652 #endif
653
654 #if defined (TARGET_SPARC64)
655 static inline int cpu_has_hypervisor(CPUSPARCState *env1)
656 {
657 return env1->def->features & CPU_FEATURE_HYPV;
658 }
659
660 static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
661 {
662 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
663 }
664
665 static inline int cpu_supervisor_mode(CPUSPARCState *env1)
666 {
667 return env1->pstate & PS_PRIV;
668 }
669 #endif
670
671 static inline int cpu_mmu_index(CPUSPARCState *env1, bool ifetch)
672 {
673 #if defined(CONFIG_USER_ONLY)
674 return MMU_USER_IDX;
675 #elif !defined(TARGET_SPARC64)
676 return env1->psrs;
677 #else
678 if (env1->tl > 0) {
679 return MMU_NUCLEUS_IDX;
680 } else if (cpu_hypervisor_mode(env1)) {
681 return MMU_HYPV_IDX;
682 } else if (cpu_supervisor_mode(env1)) {
683 return MMU_KERNEL_IDX;
684 } else {
685 return MMU_USER_IDX;
686 }
687 #endif
688 }
689
690 static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
691 {
692 #if !defined (TARGET_SPARC64)
693 if (env1->psret != 0)
694 return 1;
695 #else
696 if (env1->pstate & PS_IE)
697 return 1;
698 #endif
699
700 return 0;
701 }
702
703 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
704 {
705 #if !defined(TARGET_SPARC64)
706 /* level 15 is non-maskable on sparc v8 */
707 return pil == 15 || pil > env1->psrpil;
708 #else
709 return pil > env1->psrpil;
710 #endif
711 }
712
713 #include "exec/cpu-all.h"
714
715 #ifdef TARGET_SPARC64
716 /* sun4u.c */
717 void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
718 uint64_t cpu_tick_get_count(CPUTimer *timer);
719 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
720 trap_state* cpu_tsptr(CPUSPARCState* env);
721 #endif
722
723 #define TB_FLAG_FPU_ENABLED (1 << 4)
724 #define TB_FLAG_AM_ENABLED (1 << 5)
725
726 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
727 target_ulong *cs_base, uint32_t *flags)
728 {
729 *pc = env->pc;
730 *cs_base = env->npc;
731 #ifdef TARGET_SPARC64
732 // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
733 *flags = (env->pstate & PS_PRIV) /* 2 */
734 | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
735 | ((env->tl & 0xff) << 8)
736 | (env->dmmu.mmu_primary_context << 16); /* 16... */
737 if (env->pstate & PS_AM) {
738 *flags |= TB_FLAG_AM_ENABLED;
739 }
740 if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
741 && (env->fprs & FPRS_FEF)) {
742 *flags |= TB_FLAG_FPU_ENABLED;
743 }
744 #else
745 // FPU enable . Supervisor
746 *flags = env->psrs;
747 if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
748 *flags |= TB_FLAG_FPU_ENABLED;
749 }
750 #endif
751 }
752
753 static inline bool tb_fpu_enabled(int tb_flags)
754 {
755 #if defined(CONFIG_USER_ONLY)
756 return true;
757 #else
758 return tb_flags & TB_FLAG_FPU_ENABLED;
759 #endif
760 }
761
762 static inline bool tb_am_enabled(int tb_flags)
763 {
764 #ifndef TARGET_SPARC64
765 return false;
766 #else
767 return tb_flags & TB_FLAG_AM_ENABLED;
768 #endif
769 }
770
771 #endif